cmd/compile/internal/ssa: add support for GOARCH=mips{,le}

Change-Id: I632d4aef7295778ba5018d98bcb06a68bcf07ce1
Reviewed-on: https://go-review.googlesource.com/31478
Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>

diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go
index 933672d0079cc0b20de021de0525bb7ed1308d5e..919386e88931d799a82fca516744dc59a6b24183 100644 (file)
--- a/src/cmd/compile/internal/ssa/config.go
+++ b/src/cmd/compile/internal/ssa/config.go
@@ -36,6 +36,7 @@ type Config struct {
        use387          bool                       // GO386=387
        OldArch         bool                       // True for older versions of architecture, e.g. true for PPC64BE, false for PPC64LE
        NeedsFpScratch  bool                       // No direct move between GP and FP register sets
+       BigEndian       bool                       //
        DebugTest       bool                       // default true unless $GOSSAHASH != ""; as a debugging aid, make new code conditional on this and use GOSSAHASH to binary search for failing cases
        sparsePhiCutoff uint64                     // Sparse phi location algorithm used above this #blocks*#variables score
        curFunc         *Func
@@ -204,6 +205,7 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
                c.noDuffDevice = obj.GOOS == "darwin" // darwin linker cannot handle BR26 reloc with non-zero addend
        case "ppc64":
                c.OldArch = true
+               c.BigEndian = true
                fallthrough
        case "ppc64le":
                c.IntSize = 8
@@ -219,7 +221,10 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
                c.noDuffDevice = true // TODO: Resolve PPC64 DuffDevice (has zero, but not copy)
                c.NeedsFpScratch = true
                c.hasGReg = true
-       case "mips64", "mips64le":
+       case "mips64":
+               c.BigEndian = true
+               fallthrough
+       case "mips64le":
                c.IntSize = 8
                c.PtrSize = 8
                c.RegSize = 8
@@ -245,6 +250,24 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
                c.LinkReg = linkRegS390X
                c.hasGReg = true
                c.noDuffDevice = true
+               c.BigEndian = true
+       case "mips":
+               c.BigEndian = true
+               fallthrough
+       case "mipsle":
+               c.IntSize = 4
+               c.PtrSize = 4
+               c.RegSize = 4
+               c.lowerBlock = rewriteBlockMIPS
+               c.lowerValue = rewriteValueMIPS
+               c.registers = registersMIPS[:]
+               c.gpRegMask = gpRegMaskMIPS
+               c.fpRegMask = fpRegMaskMIPS
+               c.specialRegMask = specialRegMaskMIPS
+               c.FPReg = framepointerRegMIPS
+               c.LinkReg = linkRegMIPS
+               c.hasGReg = true
+               c.noDuffDevice = true
        default:
                fe.Fatalf(0, "arch %s not implemented", arch)
        }

diff --git a/src/cmd/compile/internal/ssa/gen/MIPS.rules b/src/cmd/compile/internal/ssa/gen/MIPS.rules
new file mode 100644 (file)
index 0000000..008f1b1
--- /dev/null
+++ b/src/cmd/compile/internal/ssa/gen/MIPS.rules
@@ -0,0 +1,739 @@
+// Copyright 2016 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+(AddPtr x y) -> (ADD x y)
+(Add32 x y) -> (ADD x y)
+(Add16 x y) -> (ADD x y)
+(Add8 x y) -> (ADD x y)
+(Add32F x y) -> (ADDF x y)
+(Add64F x y) -> (ADDD x y)
+
+(Select0 (Add32carry <t> x y)) -> (ADD <t.FieldType(0)> x y)
+(Select1 (Add32carry <t> x y)) -> (SGTU <config.fe.TypeBool()> x (ADD <t.FieldType(0)> x y))
+(Add32withcarry <t> x y c) -> (ADD c (ADD <t> x y))
+
+(SubPtr x y) -> (SUB x y)
+(Sub32 x y) -> (SUB x y)
+(Sub16 x y) -> (SUB x y)
+(Sub8 x y) -> (SUB x y)
+(Sub32F x y) -> (SUBF x y)
+(Sub64F x y) -> (SUBD x y)
+
+(Select0 (Sub32carry <t> x y)) -> (SUB <t.FieldType(0)> x y)
+(Select1 (Sub32carry <t> x y)) -> (SGTU <config.fe.TypeBool()> (SUB <t.FieldType(0)> x y) x)
+(Sub32withcarry <t> x y c) -> (SUB (SUB <t> x y) c)
+
+(Mul32 x y) -> (MUL x y)
+(Mul16 x y) -> (MUL x y)
+(Mul8 x y) -> (MUL x y)
+(Mul32F x y) -> (MULF x y)
+(Mul64F x y) -> (MULD x y)
+
+(Hmul32 x y) -> (Select0 (MULT x y))
+(Hmul32u x y) -> (Select0 (MULTU x y))
+(Hmul16 x y) -> (SRAconst (MUL <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
+(Hmul16u x y) -> (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
+(Hmul8 x y) -> (SRAconst  (MUL <config.fe.TypeInt32()> (SignExt8to32 x) (SignExt8to32 y)) [8])
+(Hmul8u x y) -> (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
+
+(Mul32uhilo x y) -> (MULTU x y)
+
+(Div32 x y) -> (Select1 (DIV x y))
+(Div32u x y) -> (Select1 (DIVU x y))
+(Div16 x y) -> (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
+(Div16u x y) -> (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
+(Div8 x y) -> (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))
+(Div8u x y) -> (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
+(Div32F x y) -> (DIVF x y)
+(Div64F x y) -> (DIVD x y)
+
+(Mod32 x y) -> (Select0 (DIV x y))
+(Mod32u x y) -> (Select0 (DIVU x y))
+(Mod16 x y) -> (Select0 (DIV (SignExt16to32 x) (SignExt16to32 y)))
+(Mod16u x y) -> (Select0 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
+(Mod8 x y) -> (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y)))
+(Mod8u x y) -> (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
+
+(And32 x y) -> (AND x y)
+(And16 x y) -> (AND x y)
+(And8 x y) -> (AND x y)
+
+(Or32 x y) -> (OR x y)
+(Or16 x y) -> (OR x y)
+(Or8 x y) -> (OR x y)
+
+(Xor32 x y) -> (XOR x y)
+(Xor16 x y) -> (XOR x y)
+(Xor8 x y) -> (XOR x y)
+
+// constant shifts
+// generic opt rewrites all constant shifts to shift by Const64
+(Lsh32x64 x (Const64 [c])) && uint32(c) < 32 -> (SLLconst x [c])
+(Rsh32x64 x (Const64 [c])) && uint32(c) < 32 -> (SRAconst x [c])
+(Rsh32Ux64 x (Const64 [c])) && uint32(c) < 32 -> (SRLconst x [c])
+(Lsh16x64 x (Const64 [c])) && uint32(c) < 16 -> (SLLconst x [c])
+(Rsh16x64 x (Const64 [c])) && uint32(c) < 16 -> (SRAconst (SLLconst <config.fe.TypeUInt32()> x [16]) [c+16])
+(Rsh16Ux64 x (Const64 [c])) && uint32(c) < 16 -> (SRLconst (SLLconst <config.fe.TypeUInt32()> x [16]) [c+16])
+(Lsh8x64 x (Const64 [c])) && uint32(c) < 8 -> (SLLconst x [c])
+(Rsh8x64 x (Const64 [c])) && uint32(c) < 8 -> (SRAconst (SLLconst <config.fe.TypeUInt32()> x [24]) [c+24])
+(Rsh8Ux64 x (Const64 [c])) && uint32(c) < 8 -> (SRLconst (SLLconst <config.fe.TypeUInt32()> x [24]) [c+24])
+
+// large constant shifts
+(Lsh32x64 _ (Const64 [c])) && uint32(c) >= 32 -> (MOVWconst [0])
+(Rsh32Ux64 _ (Const64 [c])) && uint32(c) >= 32 -> (MOVWconst [0])
+(Lsh16x64 _ (Const64 [c])) && uint32(c) >= 16 -> (MOVWconst [0])
+(Rsh16Ux64 _ (Const64 [c])) && uint32(c) >= 16 -> (MOVWconst [0])
+(Lsh8x64 _ (Const64 [c])) && uint32(c) >= 8 -> (MOVWconst [0])
+(Rsh8Ux64 _ (Const64 [c])) && uint32(c) >= 8 -> (MOVWconst [0])
+
+// large constant signed right shift, we leave the sign bit
+(Rsh32x64 x (Const64 [c])) && uint32(c) >= 32 -> (SRAconst x [31])
+(Rsh16x64 x (Const64 [c])) && uint32(c) >= 16 -> (SRAconst (SLLconst <config.fe.TypeUInt32()> x [16]) [31])
+(Rsh8x64 x (Const64 [c])) && uint32(c) >= 8 -> (SRAconst (SLLconst <config.fe.TypeUInt32()> x [24]) [31])
+
+// shifts
+// hardware instruction uses only the low 5 bits of the shift
+// we compare to 32 to ensure Go semantics for large shifts
+(Lsh32x32 <t> x y) -> (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+(Lsh32x16 <t> x y) -> (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+(Lsh32x8 <t> x y) -> (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+
+(Lsh16x32 <t> x y) -> (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+(Lsh16x16 <t> x y) -> (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+(Lsh16x8 <t> x y) -> (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+
+(Lsh8x32 <t> x y) -> (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+(Lsh8x16 <t> x y) -> (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+(Lsh8x8 <t> x y) -> (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+
+(Rsh32Ux32 <t> x y) -> (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+(Rsh32Ux16 <t> x y) -> (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+(Rsh32Ux8 <t> x y) -> (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+
+(Rsh16Ux32 <t> x y) -> (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
+(Rsh16Ux16 <t> x y) -> (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+(Rsh16Ux8 <t> x y) -> (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+
+(Rsh8Ux32 <t> x y) -> (CMOVZ (SRL <t> (ZeroExt8to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
+(Rsh8Ux16 <t> x y) -> (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+(Rsh8Ux8 <t> x y) -> (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+
+(Rsh32x32 x y) -> (SRA x ( CMOVZ <config.fe.TypeUInt32()> y (MOVWconst [-1]) (SGTUconst [32] y)))
+(Rsh32x16 x y) -> (SRA x ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt16to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt16to32 y))))
+(Rsh32x8 x y) -> (SRA x ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt8to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt8to32 y))))
+
+(Rsh16x32 x y) -> (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> y (MOVWconst [-1]) (SGTUconst [32] y)))
+(Rsh16x16 x y) -> (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt16to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt16to32 y))))
+(Rsh16x8 x y) -> (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt8to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt8to32 y))))
+
+(Rsh8x32 x y) -> (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> y (MOVWconst [-1]) (SGTUconst [32] y)))
+(Rsh8x16 x y) -> (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt16to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt16to32 y))))
+(Rsh8x8 x y) -> (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt8to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt8to32 y))))
+
+// unary ops
+(Neg32 x) -> (NEG x)
+(Neg16 x) -> (NEG x)
+(Neg8 x) -> (NEG x)
+(Neg32F x) -> (NEGF x)
+(Neg64F x) -> (NEGD x)
+
+(Com32 x) -> (NORconst [0] x)
+(Com16 x) -> (NORconst [0] x)
+(Com8 x) -> (NORconst [0] x)
+
+(Sqrt x) -> (SQRTD x)
+
+// count trailing zero
+// 32 - CLZ(x&-x - 1)
+(Ctz32 <t> x) -> (SUB (MOVWconst [32]) (CLZ <t> (SUBconst <t> [1] (AND <t> x (NEG <t> x)))))
+
+// boolean ops -- booleans are represented with 0=false, 1=true
+(AndB x y) -> (AND x y)
+(OrB x y) -> (OR x y)
+(EqB x y) -> (XORconst [1] (XOR <config.fe.TypeBool()> x y))
+(NeqB x y) -> (XOR x y)
+(Not x) -> (XORconst [1] x)
+
+// constants
+(Const32 [val]) -> (MOVWconst [val])
+(Const16 [val]) -> (MOVWconst [val])
+(Const8 [val]) -> (MOVWconst [val])
+(Const32F [val]) -> (MOVFconst [val])
+(Const64F [val]) -> (MOVDconst [val])
+(ConstNil) -> (MOVWconst [0])
+(ConstBool [b]) -> (MOVWconst [b])
+
+// truncations
+// Because we ignore high parts of registers, truncates are just copies.
+(Trunc16to8 x) -> x
+(Trunc32to8 x) -> x
+(Trunc32to16 x) -> x
+
+// Zero-/Sign-extensions
+(ZeroExt8to16 x) -> (MOVBUreg x)
+(ZeroExt8to32 x) -> (MOVBUreg x)
+(ZeroExt16to32 x) -> (MOVHUreg x)
+
+(SignExt8to16 x) -> (MOVBreg x)
+(SignExt8to32 x) -> (MOVBreg x)
+(SignExt16to32 x) -> (MOVHreg x)
+
+(Signmask x) -> (SRAconst x [31])
+(Zeromask x) -> (NEG (SGTU x (MOVWconst [0])))
+(Slicemask x) -> (NEG (SGT x (MOVWconst [0])))
+
+// float <-> int conversion
+(Cvt32to32F x) -> (MOVWF x)
+(Cvt32to64F x) -> (MOVWD x)
+(Cvt32Fto32 x) -> (TRUNCFW x)
+(Cvt64Fto32 x) -> (TRUNCDW x)
+(Cvt32Fto64F x) -> (MOVFD x)
+(Cvt64Fto32F x) -> (MOVDF x)
+
+// comparisons
+(Eq8 x y)  -> (SGTUconst [1] (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)))
+(Eq16 x y) -> (SGTUconst [1] (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)))
+(Eq32 x y) -> (SGTUconst [1] (XOR x y))
+(EqPtr x y) -> (SGTUconst [1] (XOR x y))
+(Eq32F x y) -> (FPFlagTrue (CMPEQF x y))
+(Eq64F x y) -> (FPFlagTrue (CMPEQD x y))
+
+(Neq8 x y)  -> (SGTU (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)) (MOVWconst [0]))
+(Neq16 x y) -> (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)) (MOVWconst [0]))
+(Neq32 x y) -> (SGTU (XOR x y) (MOVWconst [0]))
+(NeqPtr x y) -> (SGTU (XOR x y) (MOVWconst [0]))
+(Neq32F x y) -> (FPFlagFalse (CMPEQF x y))
+(Neq64F x y) -> (FPFlagFalse (CMPEQD x y))
+
+(Less8 x y)  -> (SGT (SignExt8to32 y) (SignExt8to32 x))
+(Less16 x y) -> (SGT (SignExt16to32 y) (SignExt16to32 x))
+(Less32 x y) -> (SGT y x)
+(Less32F x y) -> (FPFlagTrue (CMPGTF y x)) // reverse operands to work around NaN
+(Less64F x y) -> (FPFlagTrue (CMPGTD y x)) // reverse operands to work around NaN
+
+(Less8U x y)  -> (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x))
+(Less16U x y) -> (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x))
+(Less32U x y) -> (SGTU y x)
+
+(Leq8 x y)  -> (XORconst [1] (SGT (SignExt8to32 x) (SignExt8to32 y)))
+(Leq16 x y) -> (XORconst [1] (SGT (SignExt16to32 x) (SignExt16to32 y)))
+(Leq32 x y) -> (XORconst [1] (SGT x y))
+(Leq32F x y) -> (FPFlagTrue (CMPGEF y x)) // reverse operands to work around NaN
+(Leq64F x y) -> (FPFlagTrue (CMPGED y x)) // reverse operands to work around NaN
+
+(Leq8U x y)  -> (XORconst [1] (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y)))
+(Leq16U x y) -> (XORconst [1] (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y)))
+(Leq32U x y) -> (XORconst [1] (SGTU x y))
+
+(Greater8 x y)  -> (SGT (SignExt8to32 x) (SignExt8to32 y))
+(Greater16 x y) -> (SGT (SignExt16to32 x) (SignExt16to32 y))
+(Greater32 x y) -> (SGT x y)
+(Greater32F x y) -> (FPFlagTrue (CMPGTF x y))
+(Greater64F x y) -> (FPFlagTrue (CMPGTD x y))
+
+(Greater8U x y)  -> (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y))
+(Greater16U x y) -> (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y))
+(Greater32U x y) -> (SGTU x y)
+
+(Geq8 x y)  -> (XORconst [1] (SGT (SignExt8to32 y) (SignExt8to32 x)))
+(Geq16 x y) -> (XORconst [1] (SGT (SignExt16to32 y) (SignExt16to32 x)))
+(Geq32 x y) -> (XORconst [1] (SGT y x))
+(Geq32F x y) -> (FPFlagTrue (CMPGEF x y))
+(Geq64F x y) -> (FPFlagTrue (CMPGED x y))
+
+(Geq8U x y)  -> (XORconst [1] (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x)))
+(Geq16U x y) -> (XORconst [1] (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x)))
+(Geq32U x y) -> (XORconst [1] (SGTU y x))
+
+(OffPtr [off] ptr:(SP)) -> (MOVWaddr [off] ptr)
+(OffPtr [off] ptr) -> (ADDconst [off] ptr)
+
+(Addr {sym} base) -> (MOVWaddr {sym} base)
+
+// loads
+(Load <t> ptr mem) && t.IsBoolean() -> (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) -> (MOVBload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) -> (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) -> (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) -> (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) -> (MOVWload ptr mem)
+(Load <t> ptr mem) && is32BitFloat(t) -> (MOVFload ptr mem)
+(Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem)
+
+// stores
+(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
+(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
+(Store [4] ptr val mem) && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
+(Store [8] ptr val mem) && !is64BitFloat(val.Type) -> (MOVWstore ptr val mem)
+(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
+(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
+
+// zero instructions
+(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVWconst [0]) mem)
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore ptr (MOVWconst [0]) mem)
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 ->
+       (MOVBstore [1] ptr (MOVWconst [0])
+               (MOVBstore [0] ptr (MOVWconst [0]) mem))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore ptr (MOVWconst [0]) mem)
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore [2] ptr (MOVWconst [0])
+               (MOVHstore [0] ptr (MOVWconst [0]) mem))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 ->
+       (MOVBstore [3] ptr (MOVWconst [0])
+               (MOVBstore [2] ptr (MOVWconst [0])
+                       (MOVBstore [1] ptr (MOVWconst [0])
+                               (MOVBstore [0] ptr (MOVWconst [0]) mem))))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 ->
+       (MOVBstore [2] ptr (MOVWconst [0])
+               (MOVBstore [1] ptr (MOVWconst [0])
+                       (MOVBstore [0] ptr (MOVWconst [0]) mem)))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore [4] ptr (MOVWconst [0])
+               (MOVHstore [2] ptr (MOVWconst [0])
+                       (MOVHstore [0] ptr (MOVWconst [0]) mem)))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+               (MOVWstore [4] ptr (MOVWconst [0])
+                       (MOVWstore [0] ptr (MOVWconst [0]) mem))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore [8] ptr (MOVWconst [0])
+               (MOVWstore [4] ptr (MOVWconst [0])
+                       (MOVWstore [0] ptr (MOVWconst [0]) mem)))
+(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore [12] ptr (MOVWconst [0])
+               (MOVWstore [8] ptr (MOVWconst [0])
+                       (MOVWstore [4] ptr (MOVWconst [0])
+                               (MOVWstore [0] ptr (MOVWconst [0]) mem))))
+
+// large or unaligned zeroing uses a loop
+(Zero [s] ptr mem)
+       && (SizeAndAlign(s).Size() > 16  || SizeAndAlign(s).Align()%4 != 0) ->
+       (LoweredZero [SizeAndAlign(s).Align()]
+               ptr
+               (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+               mem)
+
+// moves
+(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBUload src mem) mem)
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore dst (MOVHUload src mem) mem)
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 ->
+       (MOVBstore [1] dst (MOVBUload [1] src mem)
+               (MOVBstore dst (MOVBUload src mem) mem))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore dst (MOVWload src mem) mem)
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore [2] dst (MOVHUload [2] src mem)
+               (MOVHstore dst (MOVHUload src mem) mem))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 ->
+       (MOVBstore [3] dst (MOVBUload [3] src mem)
+               (MOVBstore [2] dst (MOVBUload [2] src mem)
+                       (MOVBstore [1] dst (MOVBUload [1] src mem)
+                               (MOVBstore dst (MOVBUload src mem) mem))))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+       (MOVBstore [2] dst (MOVBUload [2] src mem)
+               (MOVBstore [1] dst (MOVBUload [1] src mem)
+                       (MOVBstore dst (MOVBUload src mem) mem)))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore [4] dst (MOVWload [4] src mem)
+               (MOVWstore dst (MOVWload src mem) mem))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore [6] dst (MOVHload [6] src mem)
+               (MOVHstore [4] dst (MOVHload [4] src mem)
+                       (MOVHstore [2] dst (MOVHload [2] src mem)
+                               (MOVHstore dst (MOVHload src mem) mem))))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 ->
+       (MOVHstore [4] dst (MOVHload [4] src mem)
+               (MOVHstore [2] dst (MOVHload [2] src mem)
+                       (MOVHstore dst (MOVHload src mem) mem)))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore [8] dst (MOVWload [8] src mem)
+               (MOVWstore [4] dst (MOVWload [4] src mem)
+                       (MOVWstore dst (MOVWload src mem) mem)))
+(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0 ->
+       (MOVWstore [12] dst (MOVWload [12] src mem)
+               (MOVWstore [8] dst (MOVWload [8] src mem)
+                       (MOVWstore [4] dst (MOVWload [4] src mem)
+                               (MOVWstore dst (MOVWload src mem) mem))))
+
+
+// large or unaligned move uses a loop
+(Move [s] dst src mem)
+       && (SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) ->
+       (LoweredMove [SizeAndAlign(s).Align()]
+               dst
+               src
+               (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+               mem)
+
+// calls
+(StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem)
+(ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem)
+(DeferCall [argwid] mem) -> (CALLdefer [argwid] mem)
+(GoCall [argwid] mem) -> (CALLgo [argwid] mem)
+(InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem)
+
+// atomic intrinsics
+(AtomicLoad32  ptr mem) -> (LoweredAtomicLoad ptr mem)
+(AtomicLoadPtr ptr mem) -> (LoweredAtomicLoad  ptr mem)
+
+(AtomicStore32      ptr val mem) -> (LoweredAtomicStore ptr val mem)
+(AtomicStorePtrNoWB ptr val mem) -> (LoweredAtomicStore  ptr val mem)
+
+(AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange ptr val mem)
+(AtomicAdd32 ptr val mem) -> (LoweredAtomicAdd ptr val mem)
+
+(AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas ptr old new_ mem)
+
+// AtomicOr8(ptr,val) -> LoweredAtomicOr(ptr&^3,uint32(val) << ((ptr & 3) * 8))
+(AtomicOr8 ptr val mem) && !config.BigEndian ->
+       (LoweredAtomicOr (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)
+               (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)
+                       (SLLconst <config.fe.TypeUInt32()> [3]
+                               (ANDconst <config.fe.TypeUInt32()> [3] ptr))) mem)
+
+// AtomicAnd8(ptr,val) -> LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
+(AtomicAnd8  ptr val mem) && !config.BigEndian ->
+       (LoweredAtomicAnd (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)
+               (OR <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)
+                       (SLLconst <config.fe.TypeUInt32()> [3]
+                               (ANDconst  <config.fe.TypeUInt32()> [3] ptr)))
+               (NORconst [0] <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()>
+                       (MOVWconst [0xff]) (SLLconst <config.fe.TypeUInt32()> [3]
+                               (ANDconst <config.fe.TypeUInt32()> [3]
+                                       (XORconst <config.fe.TypeUInt32()> [3] ptr)))))) mem)
+
+// AtomicOr8(ptr,val) -> LoweredAtomicOr(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
+(AtomicOr8 ptr val mem) && config.BigEndian ->
+       (LoweredAtomicOr (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)
+               (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)
+                       (SLLconst <config.fe.TypeUInt32()> [3]
+                               (ANDconst <config.fe.TypeUInt32()> [3]
+                                       (XORconst <config.fe.TypeUInt32()> [3] ptr)))) mem)
+
+// AtomicAnd8(ptr,val) -> LoweredAtomicAnd(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
+(AtomicAnd8  ptr val mem) && config.BigEndian ->
+       (LoweredAtomicAnd (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)
+               (OR <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)
+                       (SLLconst <config.fe.TypeUInt32()> [3]
+                               (ANDconst  <config.fe.TypeUInt32()> [3]
+                                       (XORconst <config.fe.TypeUInt32()> [3] ptr))))
+               (NORconst [0] <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()>
+                       (MOVWconst [0xff]) (SLLconst <config.fe.TypeUInt32()> [3]
+                               (ANDconst <config.fe.TypeUInt32()> [3]
+                                       (XORconst <config.fe.TypeUInt32()> [3] ptr)))))) mem)
+
+
+// checks
+(NilCheck ptr mem) -> (LoweredNilCheck ptr mem)
+(IsNonNil ptr) -> (SGTU ptr (MOVWconst [0]))
+(IsInBounds idx len) -> (SGTU len idx)
+(IsSliceInBounds idx len) -> (XORconst [1] (SGTU idx len))
+
+// pseudo-ops
+(GetClosurePtr) -> (LoweredGetClosurePtr)
+(Convert x mem) -> (MOVWconvert x mem)
+
+(If cond yes no) -> (NE cond yes no)
+
+
+// Optimizations
+
+// Absorb boolean tests into block
+(NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no)
+(NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no)
+(EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no)
+(EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no)
+(NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no)
+(NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no)
+(NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no)
+(NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no)
+(NE (XORconst [1] cmp:(SGTzero _)) yes no) -> (EQ cmp yes no)
+(NE (XORconst [1] cmp:(SGTUzero _)) yes no) -> (EQ cmp yes no)
+(EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no)
+(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no)
+(EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no)
+(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no)
+(EQ (XORconst [1] cmp:(SGTzero _)) yes no) -> (NE cmp yes no)
+(EQ (XORconst [1] cmp:(SGTUzero _)) yes no) -> (NE cmp yes no)
+(NE (SGTUconst [1] x) yes no) -> (EQ x yes no)
+(EQ (SGTUconst [1] x) yes no) -> (NE x yes no)
+(NE (SGTUzero x) yes no) -> (NE x yes no)
+(EQ (SGTUzero x) yes no) -> (EQ x yes no)
+(NE (SGTconst [0] x) yes no) -> (LTZ x yes no)
+(EQ (SGTconst [0] x) yes no) -> (GEZ x yes no)
+(NE (SGTzero x) yes no) -> (GTZ x yes no)
+(EQ (SGTzero x) yes no) -> (LEZ x yes no)
+
+// fold offset into address
+(ADDconst [off1] (MOVWaddr [off2] {sym} ptr)) -> (MOVWaddr [off1+off2] {sym} ptr)
+
+// fold address into load/store
+(MOVBload  [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBload  [off1+off2] {sym} ptr mem)
+(MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBUload [off1+off2] {sym} ptr mem)
+(MOVHload  [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHload  [off1+off2] {sym} ptr mem)
+(MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHUload [off1+off2] {sym} ptr mem)
+(MOVWload  [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVWload  [off1+off2] {sym} ptr mem)
+(MOVFload  [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVFload  [off1+off2] {sym} ptr mem)
+(MOVDload  [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVDload  [off1+off2] {sym} ptr mem)
+
+(MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBstore [off1+off2] {sym} ptr val mem)
+(MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHstore [off1+off2] {sym} ptr val mem)
+(MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVWstore [off1+off2] {sym} ptr val mem)
+(MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVFstore [off1+off2] {sym} ptr val mem)
+(MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVDstore [off1+off2] {sym} ptr val mem)
+
+(MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVBstorezero [off1+off2] {sym} ptr mem)
+(MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVHstorezero [off1+off2] {sym} ptr mem)
+(MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(off1+off2) || x.Uses == 1) -> (MOVWstorezero [off1+off2] {sym} ptr mem)
+
+(MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+
+(MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
+       (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+(MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
+       (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+(MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
+       (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+(MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
+       (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+(MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
+       (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+(MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+(MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
+       (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+
+// replace load from same location as preceding store with copy
+(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && isSigned(x.Type) -> x
+(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && !isSigned(x.Type) -> x
+(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && isSigned(x.Type) -> x
+(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && !isSigned(x.Type) -> x
+(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
+(MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
+(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
+
+// store zero
+(MOVBstore [off] {sym} ptr (MOVWconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem)
+(MOVHstore [off] {sym} ptr (MOVWconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem)
+(MOVWstore [off] {sym} ptr (MOVWconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem)
+
+// don't extend after proper load
+(MOVBreg x:(MOVBload _ _)) -> (MOVWreg x)
+(MOVBUreg x:(MOVBUload _ _)) -> (MOVWreg x)
+(MOVHreg x:(MOVBload _ _)) -> (MOVWreg x)
+(MOVHreg x:(MOVBUload _ _)) -> (MOVWreg x)
+(MOVHreg x:(MOVHload _ _)) -> (MOVWreg x)
+(MOVHUreg x:(MOVBUload _ _)) -> (MOVWreg x)
+(MOVHUreg x:(MOVHUload _ _)) -> (MOVWreg x)
+
+// fold double extensions
+(MOVBreg x:(MOVBreg _)) -> (MOVWreg x)
+(MOVBUreg x:(MOVBUreg _)) -> (MOVWreg x)
+(MOVHreg x:(MOVBreg _)) -> (MOVWreg x)
+(MOVHreg x:(MOVBUreg _)) -> (MOVWreg x)
+(MOVHreg x:(MOVHreg _)) -> (MOVWreg x)
+(MOVHUreg x:(MOVBUreg _)) -> (MOVWreg x)
+(MOVHUreg x:(MOVHUreg _)) -> (MOVWreg x)
+
+// sign extended loads
+// Note: The combined instruction must end up in the same block
+// as the original load. If not, we end up making a value with
+// memory type live in two different blocks, which can lead to
+// multiple memory values alive simultaneously.
+// Make sure we don't combine these ops if the load has another use.
+// This prevents a single load from being split into multiple loads
+// which then might return different values.  See test/atomicload.go.
+(MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <t> [off] {sym} ptr mem)
+(MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBUload <t> [off] {sym} ptr mem)
+(MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <t> [off] {sym} ptr mem)
+(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHUload <t> [off] {sym} ptr mem)
+
+// fold extensions and ANDs together
+(MOVBUreg (ANDconst [c] x)) -> (ANDconst [c&0xff] x)
+(MOVHUreg (ANDconst [c] x)) -> (ANDconst [c&0xffff] x)
+(MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 -> (ANDconst [c&0x7f] x)
+(MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 -> (ANDconst [c&0x7fff] x)
+
+// don't extend before store
+(MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
+(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
+(MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
+(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
+(MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem)
+(MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
+(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
+(MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem)
+(MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem)
+
+// if a register move has only 1 use, just use the same register without emitting instruction
+// MOVWnop doesn't emit instruction, only for ensuring the type.
+(MOVWreg x) && x.Uses == 1 -> (MOVWnop x)
+
+// fold constant into arithmatic ops
+(ADD (MOVWconst [c]) x) -> (ADDconst [c] x)
+(ADD x (MOVWconst [c])) -> (ADDconst [c] x)
+(SUB x (MOVWconst [c])) -> (SUBconst [c] x)
+(AND (MOVWconst [c]) x) -> (ANDconst [c] x)
+(AND x (MOVWconst [c])) -> (ANDconst [c] x)
+(OR  (MOVWconst [c]) x) -> (ORconst  [c] x)
+(OR  x (MOVWconst [c])) -> (ORconst  [c] x)
+(XOR (MOVWconst [c]) x) -> (XORconst [c] x)
+(XOR x (MOVWconst [c])) -> (XORconst [c] x)
+(NOR (MOVWconst [c]) x) -> (NORconst [c] x)
+(NOR x (MOVWconst [c])) -> (NORconst [c] x)
+
+(SLL _ (MOVWconst [c])) && uint32(c)>=32 -> (MOVWconst [0])
+(SRL _ (MOVWconst [c])) && uint32(c)>=32 -> (MOVWconst [0])
+(SRA x (MOVWconst [c])) && uint32(c)>=32 -> (SRAconst x [31])
+(SLL x (MOVWconst [c])) -> (SLLconst x [c])
+(SRL x (MOVWconst [c])) -> (SRLconst x [c])
+(SRA x (MOVWconst [c])) -> (SRAconst x [c])
+
+(SGT  (MOVWconst [c]) x) -> (SGTconst  [c] x)
+(SGTU (MOVWconst [c]) x) -> (SGTUconst [c] x)
+(SGT x (MOVWconst [0])) -> (SGTzero x)
+(SGTU x (MOVWconst [0])) -> (SGTUzero x)
+
+// mul with constant
+(Select1 (MULTU x (MOVWconst [c]))) && x.Op != OpMIPSMOVWconst-> (Select1 (MULTU (MOVWconst [c]) x ))
+(Select0 (MULTU x (MOVWconst [c]))) && x.Op != OpMIPSMOVWconst-> (Select0 (MULTU (MOVWconst [c]) x ))
+
+(Select1 (MULTU (MOVWconst [0]) _ )) -> (MOVWconst [0])
+(Select0 (MULTU (MOVWconst [0]) _ )) -> (MOVWconst [0])
+(Select1 (MULTU (MOVWconst [1]) x )) -> x
+(Select0 (MULTU (MOVWconst [1]) _ )) -> (MOVWconst [0])
+(Select1 (MULTU (MOVWconst [-1]) x )) -> (NEG <x.Type> x)
+(Select0 (MULTU (MOVWconst [-1]) x )) -> (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
+(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) -> (SLLconst [log2(int64(uint32(c)))] x)
+(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) -> (SRLconst [32-log2(int64(uint32(c)))] x)
+
+(MUL (MOVWconst [0]) _ ) -> (MOVWconst [0])
+(MUL (MOVWconst [1]) x ) -> x
+(MUL (MOVWconst [-1]) x ) -> (NEG x)
+(MUL (MOVWconst [c]) x ) && isPowerOfTwo(int64(uint32(c))) -> (SLLconst [log2(int64(uint32(c)))] x)
+
+// generic simplifications
+(ADD x (NEG y)) -> (SUB x y)
+(ADD (NEG y) x) -> (SUB x y)
+(SUB x x) -> (MOVWconst [0])
+(SUB (MOVWconst [0]) x) -> (NEG x)
+(AND x x) -> x
+(OR  x x) -> x
+(XOR x x) -> (MOVWconst [0])
+
+// miscellaneous patterns generated by dec64
+(AND (SGTUconst [1] x) (SGTUconst [1] y)) ->  (SGTUconst [1] (OR <x.Type> x y))
+(OR (SGTUzero x) (SGTUzero y)) ->  (SGTUzero (OR <x.Type> x y))
+
+// remove redundant *const ops
+(ADDconst [0]  x) -> x
+(SUBconst [0]  x) -> x
+(ANDconst [0]  _) -> (MOVWconst [0])
+(ANDconst [-1] x) -> x
+(ORconst  [0]  x) -> x
+(ORconst  [-1] _) -> (MOVWconst [-1])
+(XORconst [0]  x) -> x
+(XORconst [-1] x) -> (NORconst [0] x)
+
+// generic constant folding
+(ADDconst [c] (MOVWconst [d]))  -> (MOVWconst [int64(int32(c+d))])
+(ADDconst [c] (ADDconst [d] x)) -> (ADDconst [int64(int32(c+d))] x)
+(ADDconst [c] (SUBconst [d] x)) -> (ADDconst [int64(int32(c-d))] x)
+(SUBconst [c] (MOVWconst [d]))  -> (MOVWconst [int64(int32(d-c))])
+(SUBconst [c] (SUBconst [d] x)) -> (ADDconst [int64(int32(-c-d))] x)
+(SUBconst [c] (ADDconst [d] x)) -> (ADDconst [int64(int32(-c+d))] x)
+(SLLconst [c] (MOVWconst [d]))  -> (MOVWconst [int64(int32(uint32(d)<<uint32(c)))])
+(SRLconst [c] (MOVWconst [d]))  -> (MOVWconst [int64(uint32(d)>>uint32(c))])
+(SRAconst [c] (MOVWconst [d]))  -> (MOVWconst [int64(int32(d)>>uint32(c))])
+(MUL (MOVWconst [c]) (MOVWconst [d])) -> (MOVWconst [int64(int32(c)*int32(d))])
+(Select1 (MULTU  (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(uint32(c)*uint32(d)))])
+(Select0 (MULTU  (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [(c*d)>>32])
+(Select1 (DIV  (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(c)/int32(d))])
+(Select1 (DIVU (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(uint32(c)/uint32(d)))])
+(Select0 (DIV  (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(c)%int32(d))])
+(Select0 (DIVU (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(int32(uint32(c)%uint32(d)))])
+(ANDconst [c] (MOVWconst [d])) -> (MOVWconst [c&d])
+(ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x)
+(ORconst [c] (MOVWconst [d])) -> (MOVWconst [c|d])
+(ORconst [c] (ORconst [d] x)) -> (ORconst [c|d] x)
+(XORconst [c] (MOVWconst [d])) -> (MOVWconst [c^d])
+(XORconst [c] (XORconst [d] x)) -> (XORconst [c^d] x)
+(NORconst [c] (MOVWconst [d])) -> (MOVWconst [^(c|d)])
+(NEG (MOVWconst [c])) -> (MOVWconst [int64(int32(-c))])
+(MOVBreg  (MOVWconst [c])) -> (MOVWconst [int64(int8(c))])
+(MOVBUreg (MOVWconst [c])) -> (MOVWconst [int64(uint8(c))])
+(MOVHreg  (MOVWconst [c])) -> (MOVWconst [int64(int16(c))])
+(MOVHUreg (MOVWconst [c])) -> (MOVWconst [int64(uint16(c))])
+(MOVWreg  (MOVWconst [c])) -> (MOVWconst [c])
+
+// constant comparisons
+(SGTconst [c] (MOVWconst [d])) && int32(c) > int32(d) -> (MOVWconst [1])
+(SGTconst [c] (MOVWconst [d])) && int32(c) <= int32(d) -> (MOVWconst [0])
+(SGTUconst [c] (MOVWconst [d])) && uint32(c)>uint32(d) -> (MOVWconst [1])
+(SGTUconst [c] (MOVWconst [d])) && uint32(c)<=uint32(d) -> (MOVWconst [0])
+(SGTzero (MOVWconst [d])) && int32(d) > 0 -> (MOVWconst [1])
+(SGTzero (MOVWconst [d])) && int32(d) <= 0 -> (MOVWconst [0])
+(SGTUzero (MOVWconst [d])) && uint32(d) != 0 -> (MOVWconst [1])
+(SGTUzero (MOVWconst [d])) && uint32(d) == 0 -> (MOVWconst [0])
+
+// other known comparisons
+(SGTconst [c] (MOVBreg _)) && 0x7f < int32(c) -> (MOVWconst [1])
+(SGTconst [c] (MOVBreg _)) && int32(c) <= -0x80 -> (MOVWconst [0])
+(SGTconst [c] (MOVBUreg _)) && 0xff < int32(c) -> (MOVWconst [1])
+(SGTconst [c] (MOVBUreg _)) && int32(c) < 0 -> (MOVWconst [0])
+(SGTUconst [c] (MOVBUreg _)) && 0xff < uint32(c) -> (MOVWconst [1])
+(SGTconst [c] (MOVHreg _)) && 0x7fff < int32(c) -> (MOVWconst [1])
+(SGTconst [c] (MOVHreg _)) && int32(c) <= -0x8000 -> (MOVWconst [0])
+(SGTconst [c] (MOVHUreg _)) && 0xffff < int32(c) -> (MOVWconst [1])
+(SGTconst [c] (MOVHUreg _)) && int32(c) < 0 -> (MOVWconst [0])
+(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint32(c) -> (MOVWconst [1])
+(SGTconst [c] (ANDconst [m] _)) && 0 <= int32(m) && int32(m) < int32(c) -> (MOVWconst [1])
+(SGTUconst [c] (ANDconst [m] _)) && uint32(m) < uint32(c) -> (MOVWconst [1])
+(SGTconst [c] (SRLconst _ [d])) && 0 <= int32(c) && uint32(d) <= 31 && 1<<(32-uint32(d)) <= int32(c) -> (MOVWconst [1])
+(SGTUconst [c] (SRLconst _ [d])) && uint32(d) <= 31 && 1<<(32-uint32(d)) <= uint32(c) -> (MOVWconst [1])
+
+// absorb constants into branches
+(EQ  (MOVWconst [0]) yes no) -> (First nil yes no)
+(EQ  (MOVWconst [c]) yes no) && c != 0 -> (First nil no yes)
+(NE  (MOVWconst [0]) yes no) -> (First nil no yes)
+(NE  (MOVWconst [c]) yes no) && c != 0 -> (First nil yes no)
+(LTZ (MOVWconst [c]) yes no) && int32(c) <  0 -> (First nil yes no)
+(LTZ (MOVWconst [c]) yes no) && int32(c) >= 0 -> (First nil no yes)
+(LEZ (MOVWconst [c]) yes no) && int32(c) <= 0 -> (First nil yes no)
+(LEZ (MOVWconst [c]) yes no) && int32(c) >  0 -> (First nil no yes)
+(GTZ (MOVWconst [c]) yes no) && int32(c) >  0 -> (First nil yes no)
+(GTZ (MOVWconst [c]) yes no) && int32(c) <= 0 -> (First nil no yes)
+(GEZ (MOVWconst [c]) yes no) && int32(c) >= 0 -> (First nil yes no)
+(GEZ (MOVWconst [c]) yes no) && int32(c) <  0 -> (First nil no yes)
+
+// conditional move
+(CMOVZ _ b (MOVWconst [0])) -> b
+(CMOVZ a _ (MOVWconst [c])) && c!=0-> a
+(CMOVZzero _ (MOVWconst [0])) -> (MOVWconst [0])
+(CMOVZzero a (MOVWconst [c])) && c!=0-> a
+(CMOVZ a (MOVWconst [0]) c) -> (CMOVZzero a c)
+
+// atomic
+(LoweredAtomicStore ptr (MOVWconst [0]) mem) -> (LoweredAtomicStorezero ptr mem)
+(LoweredAtomicAdd ptr (MOVWconst [c]) mem) && is16Bit(c)-> (LoweredAtomicAddconst [c] ptr mem)
+

diff --git a/src/cmd/compile/internal/ssa/gen/MIPSOps.go b/src/cmd/compile/internal/ssa/gen/MIPSOps.go
new file mode 100644 (file)
index 0000000..c803c49
--- /dev/null
+++ b/src/cmd/compile/internal/ssa/gen/MIPSOps.go
@@ -0,0 +1,413 @@
+// Copyright 2016 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build ignore
+
+package main
+
+import "strings"
+
+// Notes:
+//  - Integer types live in the low portion of registers. Upper portions are junk.
+//  - Boolean types use the low-order byte of a register. 0=false, 1=true.
+//    Upper bytes are junk.
+//  - Unused portions of AuxInt are filled by sign-extending the used portion.
+//  - *const instructions may use a constant larger than the instuction can encode.
+//    In this case the assembler expands to multiple instructions and uses tmp
+//    register (R23).
+
+// Suffixes encode the bit width of various instructions.
+// W (word)      = 32 bit
+// H (half word) = 16 bit
+// HU            = 16 bit unsigned
+// B (byte)      = 8 bit
+// BU            = 8 bit unsigned
+// F (float)     = 32 bit float
+// D (double)    = 64 bit float
+
+// Note: registers not used in regalloc are not included in this list,
+// so that regmask stays within int64
+// Be careful when hand coding regmasks.
+var regNamesMIPS = []string{
+       "R0", // constant 0
+       "R1",
+       "R2",
+       "R3",
+       "R4",
+       "R5",
+       "R6",
+       "R7",
+       "R8",
+       "R9",
+       "R10",
+       "R11",
+       "R12",
+       "R13",
+       "R14",
+       "R15",
+       "R16",
+       "R17",
+       "R18",
+       "R19",
+       "R20",
+       "R21",
+       "R22",
+       //REGTMP
+       "R24",
+       "R25",
+       // R26 reserved by kernel
+       // R27 reserved by kernel
+       "R28",
+       "SP",  // aka R29
+       "g",   // aka R30
+       "R31", // REGLINK
+
+       // odd FP registers contain high parts of 64-bit FP values
+       "F0",
+       "F2",
+       "F4",
+       "F6",
+       "F8",
+       "F10",
+       "F12",
+       "F14",
+       "F16",
+       "F18",
+       "F20",
+       "F22",
+       "F24",
+       "F26",
+       "F28",
+       "F30",
+
+       "HI", // high bits of multiplication
+       "LO", // low bits of multiplication
+
+       // pseudo-registers
+       "SB",
+}
+
+func init() {
+       // Make map from reg names to reg integers.
+       if len(regNamesMIPS) > 64 {
+               panic("too many registers")
+       }
+       num := map[string]int{}
+       for i, name := range regNamesMIPS {
+               num[name] = i
+       }
+       buildReg := func(s string) regMask {
+               m := regMask(0)
+               for _, r := range strings.Split(s, " ") {
+                       if n, ok := num[r]; ok {
+                               m |= regMask(1) << uint(n)
+                               continue
+                       }
+                       panic("register " + r + " not found")
+               }
+               return m
+       }
+
+       // Common individual register masks
+       var (
+               gp         = buildReg("R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31")
+               gpg        = gp | buildReg("g")
+               gpsp       = gp | buildReg("SP")
+               gpspg      = gpg | buildReg("SP")
+               gpspsbg    = gpspg | buildReg("SB")
+               fp         = buildReg("F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30")
+               lo         = buildReg("LO")
+               hi         = buildReg("HI")
+               callerSave = gp | fp | lo | hi | buildReg("g") // runtime.setg (and anything calling it) may clobber g
+       )
+       // Common regInfo
+       var (
+               gp01      = regInfo{inputs: nil, outputs: []regMask{gp}}
+               gp11      = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
+               gp11sp    = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
+               gp21      = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
+               gp31      = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
+               gp2hilo   = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{hi, lo}}
+               gpload    = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
+               gpstore   = regInfo{inputs: []regMask{gpspsbg, gpg}}
+               gpxchg    = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
+               gpcas     = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}}
+               gpstore0  = regInfo{inputs: []regMask{gpspsbg}}
+               fp01      = regInfo{inputs: nil, outputs: []regMask{fp}}
+               fp11      = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
+               fp21      = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
+               fp2flags  = regInfo{inputs: []regMask{fp, fp}}
+               fpload    = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}}
+               fpstore   = regInfo{inputs: []regMask{gpspsbg, fp}}
+               readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
+       )
+       ops := []opData{
+               {name: "ADD", argLength: 2, reg: gp21, asm: "ADDU", commutative: true},                                                                           // arg0 + arg1
+               {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADDU", aux: "Int32"},                                                                         // arg0 + auxInt
+               {name: "SUB", argLength: 2, reg: gp21, asm: "SUBU"},                                                                                              // arg0 - arg1
+               {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUBU", aux: "Int32"},                                                                           // arg0 - auxInt
+               {name: "MUL", argLength: 2, reg: regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}, clobbers: hi | lo}, asm: "MUL", commutative: true}, // arg0 * arg1
+               {name: "MULT", argLength: 2, reg: gp2hilo, asm: "MUL", commutative: true, typ: "(Int32,Int32)"},                                                  // arg0 * arg1, signed, results hi,lo
+               {name: "MULTU", argLength: 2, reg: gp2hilo, asm: "MULU", commutative: true, typ: "(UInt32,UInt32)"},                                              // arg0 * arg1, unsigned, results hi,lo
+               {name: "DIV", argLength: 2, reg: gp2hilo, asm: "DIV", typ: "(Int32,Int32)"},                                                                      // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1
+               {name: "DIVU", argLength: 2, reg: gp2hilo, asm: "DIVU", typ: "(UInt32,UInt32)"},                                                                  // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1
+
+               {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1
+               {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1
+               {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"},                    // arg0 - arg1
+               {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"},                    // arg0 - arg1
+               {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
+               {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
+               {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
+               {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
+
+               {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
+               {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32"},                // arg0 & auxInt
+               {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true},                  // arg0 | arg1
+               {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int32"},                  // arg0 | auxInt
+               {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt32"}, // arg0 ^ arg1
+               {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int32", typ: "UInt32"}, // arg0 ^ auxInt
+               {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true},                // ^(arg0 | arg1)
+               {name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int32"},                // ^(arg0 | auxInt)
+
+               {name: "NEG", argLength: 1, reg: gp11},                 // -arg0
+               {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"},   // -arg0, float32
+               {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"},   // -arg0, float64
+               {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
+
+               // shifts
+               {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"},                    // arg0 << arg1, shift amount is mod 32
+               {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt
+               {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"},                    // arg0 >> arg1, unsigned, shift amount is mod 32
+               {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, unsigned
+               {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},                    // arg0 >> arg1, signed, shift amount is mod 32
+               {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int32"}, // arg0 >> auxInt, signed
+
+               {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"},
+
+               // comparisons
+               {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"},                      // 1 if arg0 > arg1 (signed), 0 otherwise
+               {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int32", typ: "Bool"},   // 1 if auxInt > arg0 (signed), 0 otherwise
+               {name: "SGTzero", argLength: 1, reg: gp11, asm: "SGT", typ: "Bool"},                  // 1 if arg0 > 0 (signed), 0 otherwise
+               {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"},                    // 1 if arg0 > arg1 (unsigned), 0 otherwise
+               {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int32", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
+               {name: "SGTUzero", argLength: 1, reg: gp11, asm: "SGTU", typ: "Bool"},                // 1 if arg0 > 0 (unsigned), 0 otherwise
+
+               {name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
+               {name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
+               {name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"}, // flags=true if arg0 >= arg1, float32
+               {name: "CMPGED", argLength: 2, reg: fp2flags, asm: "CMPGED", typ: "Flags"}, // flags=true if arg0 >= arg1, float64
+               {name: "CMPGTF", argLength: 2, reg: fp2flags, asm: "CMPGTF", typ: "Flags"}, // flags=true if arg0 > arg1, float32
+               {name: "CMPGTD", argLength: 2, reg: fp2flags, asm: "CMPGTD", typ: "Flags"}, // flags=true if arg0 > arg1, float64
+
+               // moves
+               {name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", typ: "UInt32", rematerializeable: true},    // auxint
+               {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float32", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float
+               {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float
+
+               {name: "MOVWaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVW", rematerializeable: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB
+
+               {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true},     // load from arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true},  // load from arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true},    // load from arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true}, // load from arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "UInt32", faultOnNilArg0: true},   // load from arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true},  // load from arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true},  // load from arg0 + auxInt + aux.  arg1=mem.
+
+               {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true}, // store 1 byte of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true}, // store 2 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true}, // store 4 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+               {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true}, // store 8 bytes of arg1 to arg0 + auxInt + aux.  arg2=mem.
+
+               {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true}, // store 1 byte of zero to arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true}, // store 2 bytes of zero to arg0 + auxInt + aux.  arg1=mem.
+               {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true}, // store 4 bytes of zero to arg0 + auxInt + aux.  arg1=mem.
+
+               // conversions
+               {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"},   // move from arg0, sign-extended from byte
+               {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
+               {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"},   // move from arg0, sign-extended from half
+               {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
+               {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"},   // move from arg0
+
+               {name: "MOVWnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register
+
+               // conditional move on zero (returns arg1 if arg2 is 0, otherwise arg0)
+               // order of parameters is reversed so we can use resultInArg0 (OpCMOVZ result arg1 arg2-> CMOVZ arg2reg, arg1reg, resultReg)
+               {name: "CMOVZ", argLength: 3, reg: gp31, asm: "CMOVZ", resultInArg0: true},
+               {name: "CMOVZzero", argLength: 2, reg: regInfo{inputs: []regMask{gp, gpg}, outputs: []regMask{gp}}, asm: "CMOVZ", resultInArg0: true},
+
+               {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"},     // int32 -> float32
+               {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"},     // int32 -> float64
+               {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"}, // float32 -> int32
+               {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"}, // float64 -> int32
+               {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"},     // float32 -> float64
+               {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"},     // float64 -> float32
+
+               // function calls
+               {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true, call: true},                                              // call static function aux.(*gc.Sym).  arg0=mem, auxint=argsize, returns mem
+               {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R22"), 0}, clobbers: callerSave}, aux: "Int32", clobberFlags: true, call: true}, // call function via closure.  arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
+               {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int32", clobberFlags: true, call: true},                                                // call deferproc.  arg0=mem, auxint=argsize, returns mem
+               {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int32", clobberFlags: true, call: true},                                                   // call newproc.  arg0=mem, auxint=argsize, returns mem
+               {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int32", clobberFlags: true, call: true},                         // call fn by pointer.  arg0=codeptr, arg1=mem, auxint=argsize, returns mem
+
+               // atomic ops
+
+               // load from arg0. arg1=mem.
+               // returns <value,memory> so they can be properly ordered with other loads.
+               // SYNC
+               // MOVW (Rarg0), Rout
+               // SYNC
+               {name: "LoweredAtomicLoad", argLength: 2, reg: gpload, faultOnNilArg0: true},
+
+               // store arg1 to arg0. arg2=mem. returns memory.
+               // SYNC
+               // MOVW Rarg1, (Rarg0)
+               // SYNC
+               {name: "LoweredAtomicStore", argLength: 3, reg: gpstore, faultOnNilArg0: true},
+               {name: "LoweredAtomicStorezero", argLength: 2, reg: gpstore0, faultOnNilArg0: true},
+
+               // atomic exchange.
+               // store arg1 to arg0. arg2=mem. returns <old content of *arg0, memory>.
+               // SYNC
+               // LL   (Rarg0), Rout
+               // MOVW Rarg1, Rtmp
+               // SC   Rtmp, (Rarg0)
+               // BEQ  Rtmp, -3(PC)
+               // SYNC
+               {name: "LoweredAtomicExchange", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true},
+
+               // atomic add.
+               // *arg0 += arg1. arg2=mem. returns <new content of *arg0, memory>.
+               // SYNC
+               // LL   (Rarg0), Rout
+               // ADDU Rarg1, Rout, Rtmp
+               // SC   Rtmp, (Rarg0)
+               // BEQ  Rtmp, -3(PC)
+               // SYNC
+               // ADDU Rarg1, Rout
+               {name: "LoweredAtomicAdd", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true},
+               {name: "LoweredAtomicAddconst", argLength: 2, reg: regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}, aux: "Int32", resultNotInArgs: true, faultOnNilArg0: true},
+
+               // atomic compare and swap.
+               // arg0 = pointer, arg1 = old value, arg2 = new value, arg3 = memory.
+               // if *arg0 == arg1 {
+               //   *arg0 = arg2
+               //   return (true, memory)
+               // } else {
+               //   return (false, memory)
+               // }
+               // SYNC
+               // MOVW $0, Rout
+               // LL   (Rarg0), Rtmp
+               // BNE  Rtmp, Rarg1, 4(PC)
+               // MOVW Rarg2, Rout
+               // SC   Rout, (Rarg0)
+               // BEQ  Rout, -4(PC)
+               // SYNC
+               {name: "LoweredAtomicCas", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true},
+
+               // atomic and/or.
+               // *arg0 &= (|=) arg1. arg2=mem. returns memory.
+               // SYNC
+               // LL   (Rarg0), Rtmp
+               // AND  Rarg1, Rtmp
+               // SC   Rtmp, (Rarg0)
+               // BEQ  Rtmp, -3(PC)
+               // SYNC
+               {name: "LoweredAtomicAnd", argLength: 3, reg: gpstore, asm: "AND", faultOnNilArg0: true},
+               {name: "LoweredAtomicOr", argLength: 3, reg: gpstore, asm: "OR", faultOnNilArg0: true},
+
+               // large or unaligned zeroing
+               // arg0 = address of memory to zero (in R1, changed as side effect)
+               // arg1 = address of the last element to zero
+               // arg2 = mem
+               // auxint = alignment
+               // returns mem
+               //      SUBU    $4, R1
+               //      MOVW    R0, 4(R1)
+               //      ADDU    $4, R1
+               //      BNE     Rarg1, R1, -2(PC)
+               {
+                       name:      "LoweredZero",
+                       aux:       "Int32",
+                       argLength: 3,
+                       reg: regInfo{
+                               inputs:   []regMask{buildReg("R1"), gp},
+                               clobbers: buildReg("R1"),
+                       },
+                       faultOnNilArg0: true,
+               },
+
+               // large or unaligned move
+               // arg0 = address of dst memory (in R2, changed as side effect)
+               // arg1 = address of src memory (in R1, changed as side effect)
+               // arg2 = address of the last element of src
+               // arg3 = mem
+               // auxint = alignment
+               // returns mem
+               //      SUBU    $4, R1
+               //      MOVW    4(R1), Rtmp
+               //      MOVW    Rtmp, (R2)
+               //      ADDU    $4, R1
+               //      ADDU    $4, R2
+               //      BNE     Rarg2, R1, -4(PC)
+               {
+                       name:      "LoweredMove",
+                       aux:       "Int32",
+                       argLength: 4,
+                       reg: regInfo{
+                               inputs:   []regMask{buildReg("R2"), buildReg("R1"), gp},
+                               clobbers: buildReg("R1 R2"),
+                       },
+                       faultOnNilArg0: true,
+                       faultOnNilArg1: true,
+               },
+
+               // pseudo-ops
+               {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil.  arg1=mem.
+
+               {name: "FPFlagTrue", argLength: 1, reg: readflags},  // bool, true if FP flag is true
+               {name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false
+
+               // Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
+               // and sorts it to the very beginning of the block to prevent other
+               // use of R22 (mips.REGCTXT, the closure pointer)
+               {name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R22")}}},
+
+               // MOVWconvert converts between pointers and integers.
+               // We have a special op for this so as to not confuse GC
+               // (particularly stack maps).  It takes a memory arg so it
+               // gets correctly ordered with respect to GC safepoints.
+               // arg0=ptr/int arg1=mem, output=int/ptr
+               {name: "MOVWconvert", argLength: 2, reg: gp11, asm: "MOVW"},
+       }
+
+       blocks := []blockData{
+               {name: "EQ"},
+               {name: "NE"},
+               {name: "LTZ"}, // < 0
+               {name: "LEZ"}, // <= 0
+               {name: "GTZ"}, // > 0
+               {name: "GEZ"}, // >= 0
+               {name: "FPT"}, // FP flag is true
+               {name: "FPF"}, // FP flag is false
+       }
+
+       archs = append(archs, arch{
+               name:            "MIPS",
+               pkg:             "cmd/internal/obj/mips",
+               genfile:         "../../mips/ssa.go",
+               ops:             ops,
+               blocks:          blocks,
+               regnames:        regNamesMIPS,
+               gpregmask:       gp,
+               fpregmask:       fp,
+               specialregmask:  hi | lo,
+               framepointerreg: -1, // not used
+               linkreg:         int8(num["R31"]),
+       })
+}

diff --git a/src/cmd/compile/internal/ssa/gen/dec64.rules b/src/cmd/compile/internal/ssa/gen/dec64.rules
index 9945ae5c6c9533e8ad4e0097c98e1bb4f31226ca..961ffc7d6d05017972f045b2ef4436606f81b602 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/dec64.rules
+++ b/src/cmd/compile/internal/ssa/gen/dec64.rules
@@ -9,31 +9,57 @@
 (Int64Hi (Int64Make hi _)) -> hi
 (Int64Lo (Int64Make _ lo)) -> lo
 
-// Assuming little endian (we don't support big endian 32-bit architecture yet)
-(Load <t> ptr mem) && is64BitInt(t) && t.IsSigned() ->
+
+(Load <t> ptr mem) && is64BitInt(t) && !config.BigEndian && t.IsSigned() ->
        (Int64Make
                (Load <config.fe.TypeInt32()> (OffPtr <config.fe.TypeInt32().PtrTo()> [4] ptr) mem)
                (Load <config.fe.TypeUInt32()> ptr mem))
-(Load <t> ptr mem) && is64BitInt(t) && !t.IsSigned() ->
+
+(Load <t> ptr mem) && is64BitInt(t) && !config.BigEndian && !t.IsSigned() ->
        (Int64Make
                (Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem)
                (Load <config.fe.TypeUInt32()> ptr mem))
 
-(Store [8] dst (Int64Make hi lo) mem) ->
+(Load <t> ptr mem) && is64BitInt(t) && config.BigEndian && t.IsSigned() ->
+       (Int64Make
+               (Load <config.fe.TypeInt32()> ptr mem)
+               (Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
+
+(Load <t> ptr mem) && is64BitInt(t) && config.BigEndian && !t.IsSigned() ->
+       (Int64Make
+               (Load <config.fe.TypeUInt32()> ptr mem)
+               (Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
+
+(Store [8] dst (Int64Make hi lo) mem) && !config.BigEndian ->
        (Store [4]
                (OffPtr <hi.Type.PtrTo()> [4] dst)
                hi
                (Store [4] dst lo mem))
 
-(Arg {n} [off]) && is64BitInt(v.Type) && v.Type.IsSigned() ->
+(Store [8] dst (Int64Make hi lo) mem) && config.BigEndian ->
+       (Store [4]
+               (OffPtr <lo.Type.PtrTo()> [4] dst)
+               lo
+               (Store [4] dst hi mem))
+
+(Arg {n} [off]) && is64BitInt(v.Type) && !config.BigEndian && v.Type.IsSigned() ->
   (Int64Make
     (Arg <config.fe.TypeInt32()> {n} [off+4])
     (Arg <config.fe.TypeUInt32()> {n} [off]))
-(Arg {n} [off]) && is64BitInt(v.Type) && !v.Type.IsSigned() ->
+(Arg {n} [off]) && is64BitInt(v.Type) && !config.BigEndian && !v.Type.IsSigned() ->
   (Int64Make
     (Arg <config.fe.TypeUInt32()> {n} [off+4])
     (Arg <config.fe.TypeUInt32()> {n} [off]))
 
+(Arg {n} [off]) && is64BitInt(v.Type) && config.BigEndian && v.Type.IsSigned() ->
+  (Int64Make
+    (Arg <config.fe.TypeInt32()> {n} [off])
+    (Arg <config.fe.TypeUInt32()> {n} [off+4]))
+(Arg {n} [off]) && is64BitInt(v.Type) && config.BigEndian && !v.Type.IsSigned() ->
+  (Int64Make
+    (Arg <config.fe.TypeUInt32()> {n} [off])
+    (Arg <config.fe.TypeUInt32()> {n} [off+4]))
+
 (Add64 x y) ->
        (Int64Make
                (Add32withcarry <config.fe.TypeInt32()>

diff --git a/src/cmd/compile/internal/ssa/gen/main.go b/src/cmd/compile/internal/ssa/gen/main.go
index ac9a87ea96acfe620a025b144de8899dbda5e9a6..41199f792262ab43da0d39968e540c954656927a 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/main.go
+++ b/src/cmd/compile/internal/ssa/gen/main.go
@@ -195,13 +195,13 @@ func genOp() {
                        }
                        if v.faultOnNilArg0 {
                                fmt.Fprintln(w, "faultOnNilArg0: true,")
-                               if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "" {
+                               if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "" {
                                        log.Fatalf("faultOnNilArg0 with aux %s not allowed", v.aux)
                                }
                        }
                        if v.faultOnNilArg1 {
                                fmt.Fprintln(w, "faultOnNilArg1: true,")
-                               if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "" {
+                               if v.aux != "SymOff" && v.aux != "SymValAndOff" && v.aux != "Int64" && v.aux != "Int32" && v.aux != "" {
                                        log.Fatalf("faultOnNilArg1 with aux %s not allowed", v.aux)
                                }
                        }

diff --git a/src/cmd/compile/internal/ssa/nilcheck.go b/src/cmd/compile/internal/ssa/nilcheck.go
index a89132e65883ee21a3ebe195b556f3cc269fee28..eb2d297f802609ec94939f403dab304410a8914a 100644 (file)
--- a/src/cmd/compile/internal/ssa/nilcheck.go
+++ b/src/cmd/compile/internal/ssa/nilcheck.go
@@ -184,6 +184,8 @@ func nilcheckelim2(f *Func) {
                                        if v.Aux != nil || off < 0 || off >= minZeroPage {
                                                continue
                                        }
+                               case auxInt32:
+                                       // Mips uses this auxType for atomic add constant. It does not affect the effective address.
                                case auxInt64:
                                        // ARM uses this auxType for duffcopy/duffzero/alignment info.
                                        // It does not affect the effective address.

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index c95131dbcd8b835e278ceb67c5aabcdeaf136ed3..a63c5b9953ba724c4552562d9e8f41971ae6cc22 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -72,6 +72,15 @@ const (
        BlockARM64ZW
        BlockARM64NZW
 
+       BlockMIPSEQ
+       BlockMIPSNE
+       BlockMIPSLTZ
+       BlockMIPSLEZ
+       BlockMIPSGTZ
+       BlockMIPSGEZ
+       BlockMIPSFPT
+       BlockMIPSFPF
+
        BlockMIPS64EQ
        BlockMIPS64NE
        BlockMIPS64LTZ
@@ -169,6 +178,15 @@ var blockString = [...]string{
        BlockARM64ZW:  "ZW",
        BlockARM64NZW: "NZW",
 
+       BlockMIPSEQ:  "EQ",
+       BlockMIPSNE:  "NE",
+       BlockMIPSLTZ: "LTZ",
+       BlockMIPSLEZ: "LEZ",
+       BlockMIPSGTZ: "GTZ",
+       BlockMIPSGEZ: "GEZ",
+       BlockMIPSFPT: "FPT",
+       BlockMIPSFPF: "FPF",
+
        BlockMIPS64EQ:  "EQ",
        BlockMIPS64NE:  "NE",
        BlockMIPS64LTZ: "LTZ",
@@ -1026,6 +1044,109 @@ const (
        OpARM64LoweredAtomicAnd8
        OpARM64LoweredAtomicOr8
 
+       OpMIPSADD
+       OpMIPSADDconst
+       OpMIPSSUB
+       OpMIPSSUBconst
+       OpMIPSMUL
+       OpMIPSMULT
+       OpMIPSMULTU
+       OpMIPSDIV
+       OpMIPSDIVU
+       OpMIPSADDF
+       OpMIPSADDD
+       OpMIPSSUBF
+       OpMIPSSUBD
+       OpMIPSMULF
+       OpMIPSMULD
+       OpMIPSDIVF
+       OpMIPSDIVD
+       OpMIPSAND
+       OpMIPSANDconst
+       OpMIPSOR
+       OpMIPSORconst
+       OpMIPSXOR
+       OpMIPSXORconst
+       OpMIPSNOR
+       OpMIPSNORconst
+       OpMIPSNEG
+       OpMIPSNEGF
+       OpMIPSNEGD
+       OpMIPSSQRTD
+       OpMIPSSLL
+       OpMIPSSLLconst
+       OpMIPSSRL
+       OpMIPSSRLconst
+       OpMIPSSRA
+       OpMIPSSRAconst
+       OpMIPSCLZ
+       OpMIPSSGT
+       OpMIPSSGTconst
+       OpMIPSSGTzero
+       OpMIPSSGTU
+       OpMIPSSGTUconst
+       OpMIPSSGTUzero
+       OpMIPSCMPEQF
+       OpMIPSCMPEQD
+       OpMIPSCMPGEF
+       OpMIPSCMPGED
+       OpMIPSCMPGTF
+       OpMIPSCMPGTD
+       OpMIPSMOVWconst
+       OpMIPSMOVFconst
+       OpMIPSMOVDconst
+       OpMIPSMOVWaddr
+       OpMIPSMOVBload
+       OpMIPSMOVBUload
+       OpMIPSMOVHload
+       OpMIPSMOVHUload
+       OpMIPSMOVWload
+       OpMIPSMOVFload
+       OpMIPSMOVDload
+       OpMIPSMOVBstore
+       OpMIPSMOVHstore
+       OpMIPSMOVWstore
+       OpMIPSMOVFstore
+       OpMIPSMOVDstore
+       OpMIPSMOVBstorezero
+       OpMIPSMOVHstorezero
+       OpMIPSMOVWstorezero
+       OpMIPSMOVBreg
+       OpMIPSMOVBUreg
+       OpMIPSMOVHreg
+       OpMIPSMOVHUreg
+       OpMIPSMOVWreg
+       OpMIPSMOVWnop
+       OpMIPSCMOVZ
+       OpMIPSCMOVZzero
+       OpMIPSMOVWF
+       OpMIPSMOVWD
+       OpMIPSTRUNCFW
+       OpMIPSTRUNCDW
+       OpMIPSMOVFD
+       OpMIPSMOVDF
+       OpMIPSCALLstatic
+       OpMIPSCALLclosure
+       OpMIPSCALLdefer
+       OpMIPSCALLgo
+       OpMIPSCALLinter
+       OpMIPSLoweredAtomicLoad
+       OpMIPSLoweredAtomicStore
+       OpMIPSLoweredAtomicStorezero
+       OpMIPSLoweredAtomicExchange
+       OpMIPSLoweredAtomicAdd
+       OpMIPSLoweredAtomicAddconst
+       OpMIPSLoweredAtomicCas
+       OpMIPSLoweredAtomicAnd
+       OpMIPSLoweredAtomicOr
+       OpMIPSLoweredZero
+       OpMIPSLoweredMove
+       OpMIPSLoweredNilCheck
+       OpMIPSFPFlagTrue
+       OpMIPSFPFlagFalse
+       OpMIPSLoweredGetClosurePtr
+       OpMIPSMOVWconvert
+
        OpMIPS64ADDV
        OpMIPS64ADDVconst
        OpMIPS64SUBV
@@ -12674,121 +12795,137 @@ var opcodeTable = [...]opInfo{
        },
 
        {
-               name:        "ADDV",
+               name:        "ADD",
                argLen:      2,
                commutative: true,
-               asm:         mips.AADDVU,
+               asm:         mips.AADDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "ADDVconst",
-               auxType: auxInt64,
+               name:    "ADDconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.AADDVU,
+               asm:     mips.AADDU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
+                               {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "SUBV",
+               name:   "SUB",
                argLen: 2,
-               asm:    mips.ASUBVU,
+               asm:    mips.ASUBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SUBVconst",
-               auxType: auxInt64,
+               name:    "SUBconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASUBVU,
+               asm:     mips.ASUBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:        "MULV",
+               name:        "MUL",
                argLen:      2,
                commutative: true,
-               asm:         mips.AMULV,
+               asm:         mips.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
+                       clobbers: 105553116266496, // HI LO
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:        "MULVU",
+               name:        "MULT",
                argLen:      2,
                commutative: true,
-               asm:         mips.AMULVU,
+               asm:         mips.AMUL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
                        },
                },
        },
        {
-               name:   "DIVV",
+               name:        "MULTU",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
+                       },
+               },
+       },
+       {
+               name:   "DIV",
                argLen: 2,
-               asm:    mips.ADIVV,
+               asm:    mips.ADIV,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
                        },
                },
        },
        {
-               name:   "DIVVU",
+               name:   "DIVU",
                argLen: 2,
-               asm:    mips.ADIVVU,
+               asm:    mips.ADIVU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504606846976}, // HI
-                               {1, 2305843009213693952}, // LO
+                               {0, 35184372088832}, // HI
+                               {1, 70368744177664}, // LO
                        },
                },
        },
@@ -12799,11 +12936,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AADDF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12814,11 +12951,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AADDD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12828,11 +12965,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASUBF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12842,11 +12979,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASUBD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12857,11 +12994,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AMULF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12872,11 +13009,11 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AMULD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12886,11 +13023,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ADIVF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12900,11 +13037,11 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ADIVD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -12915,25 +13052,25 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "ANDconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.AAND,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -12944,25 +13081,25 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "ORconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.AOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -12973,25 +13110,25 @@ var opcodeTable = [...]opInfo{
                asm:         mips.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "XORconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.AXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13002,37 +13139,37 @@ var opcodeTable = [...]opInfo{
                asm:         mips.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "NORconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.ANOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "NEGV",
+               name:   "NEG",
                argLen: 1,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13042,10 +13179,10 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ANEGF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13055,94 +13192,120 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ANEGD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:   "SLLV",
+               name:   "SQRTD",
+               argLen: 1,
+               asm:    mips.ASQRTD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:   "SLL",
                argLen: 2,
-               asm:    mips.ASLLV,
+               asm:    mips.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SLLVconst",
-               auxType: auxInt64,
+               name:    "SLLconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASLLV,
+               asm:     mips.ASLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "SRLV",
+               name:   "SRL",
                argLen: 2,
-               asm:    mips.ASRLV,
+               asm:    mips.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SRLVconst",
-               auxType: auxInt64,
+               name:    "SRLconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASRLV,
+               asm:     mips.ASRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:   "SRAV",
+               name:   "SRA",
                argLen: 2,
-               asm:    mips.ASRAV,
+               asm:    mips.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:    "SRAVconst",
-               auxType: auxInt64,
+               name:    "SRAconst",
+               auxType: auxInt32,
                argLen:  1,
-               asm:     mips.ASRAV,
+               asm:     mips.ASRA,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "CLZ",
+               argLen: 1,
+               asm:    mips.ACLZ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13152,25 +13315,38 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "SGTconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.ASGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "SGTzero",
+               argLen: 1,
+               asm:    mips.ASGT,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13180,25 +13356,38 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
-                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:    "SGTUconst",
-               auxType: auxInt64,
+               auxType: auxInt32,
                argLen:  1,
                asm:     mips.ASGTU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "SGTUzero",
+               argLen: 1,
+               asm:    mips.ASGTU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13208,8 +13397,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPEQF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13219,8 +13408,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPEQD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13230,8 +13419,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGEF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13241,8 +13430,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGED,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13252,8 +13441,8 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGTF,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13263,32 +13452,32 @@ var opcodeTable = [...]opInfo{
                asm:    mips.ACMPGTD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
-                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:              "MOVVconst",
-               auxType:           auxInt64,
+               name:              "MOVWconst",
+               auxType:           auxInt32,
                argLen:            0,
                rematerializeable: true,
-               asm:               mips.AMOVV,
+               asm:               mips.AMOVW,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
                name:              "MOVFconst",
-               auxType:           auxFloat64,
+               auxType:           auxFloat32,
                argLen:            0,
                rematerializeable: true,
                asm:               mips.AMOVF,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
@@ -13300,22 +13489,22 @@ var opcodeTable = [...]opInfo{
                asm:               mips.AMOVD,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
                        },
                },
        },
        {
-               name:              "MOVVaddr",
+               name:              "MOVWaddr",
                auxType:           auxSymOff,
                argLen:            1,
                rematerializeable: true,
-               asm:               mips.AMOVV,
+               asm:               mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018460942336}, // SP SB
+                               {0, 140737555464192}, // SP SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13327,10 +13516,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13342,10 +13531,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVBU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13357,10 +13546,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVH,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13372,10 +13561,10 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVHU,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
@@ -13387,15 +13576,1310 @@ var opcodeTable = [...]opInfo{
                asm:            mips.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
                        },
                        outputs: []outputInfo{
-                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
                        },
                },
        },
        {
-               name:           "MOVWUload",
+               name:           "MOVFload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:           "MOVDload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:           "MOVBstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVHstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVH,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVWstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVFstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVDstore",
+               auxType:        auxSymOff,
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVBstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVHstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVH,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "MOVWstorezero",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:   "MOVBreg",
+               argLen: 1,
+               asm:    mips.AMOVB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "MOVBUreg",
+               argLen: 1,
+               asm:    mips.AMOVBU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "MOVHreg",
+               argLen: 1,
+               asm:    mips.AMOVH,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "MOVHUreg",
+               argLen: 1,
+               asm:    mips.AMOVHU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "MOVWreg",
+               argLen: 1,
+               asm:    mips.AMOVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:         "MOVWnop",
+               argLen:       1,
+               resultInArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:         "CMOVZ",
+               argLen:       3,
+               resultInArg0: true,
+               asm:          mips.ACMOVZ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:         "CMOVZzero",
+               argLen:       2,
+               resultInArg0: true,
+               asm:          mips.ACMOVZ,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                               {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "MOVWF",
+               argLen: 1,
+               asm:    mips.AMOVWF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:   "MOVWD",
+               argLen: 1,
+               asm:    mips.AMOVWD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:   "TRUNCFW",
+               argLen: 1,
+               asm:    mips.ATRUNCFW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:   "TRUNCDW",
+               argLen: 1,
+               asm:    mips.ATRUNCDW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:   "MOVFD",
+               argLen: 1,
+               asm:    mips.AMOVFD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:   "MOVDF",
+               argLen: 1,
+               asm:    mips.AMOVDF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+                       outputs: []outputInfo{
+                               {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
+                       },
+               },
+       },
+       {
+               name:         "CALLstatic",
+               auxType:      auxSymOff,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+               },
+       },
+       {
+               name:         "CALLclosure",
+               auxType:      auxInt32,
+               argLen:       3,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 4194304},   // R22
+                               {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
+                       },
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+               },
+       },
+       {
+               name:         "CALLdefer",
+               auxType:      auxInt32,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+               },
+       },
+       {
+               name:         "CALLgo",
+               auxType:      auxInt32,
+               argLen:       1,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+               },
+       },
+       {
+               name:         "CALLinter",
+               auxType:      auxInt32,
+               argLen:       2,
+               clobberFlags: true,
+               call:         true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+                       clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
+               },
+       },
+       {
+               name:           "LoweredAtomicLoad",
+               argLen:         2,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStore",
+               argLen:         3,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicStorezero",
+               argLen:         2,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicExchange",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAdd",
+               argLen:          3,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicAddconst",
+               auxType:         auxInt32,
+               argLen:          2,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:            "LoweredAtomicCas",
+               argLen:          4,
+               resultNotInArgs: true,
+               faultOnNilArg0:  true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicAnd",
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AAND,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredAtomicOr",
+               argLen:         3,
+               faultOnNilArg0: true,
+               asm:            mips.AOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                               {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
+                       },
+               },
+       },
+       {
+               name:           "LoweredZero",
+               auxType:        auxInt32,
+               argLen:         3,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 2},         // R1
+                               {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+                       clobbers: 2, // R1
+               },
+       },
+       {
+               name:           "LoweredMove",
+               auxType:        auxInt32,
+               argLen:         4,
+               faultOnNilArg0: true,
+               faultOnNilArg1: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4},         // R2
+                               {1, 2},         // R1
+                               {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+                       clobbers: 6, // R1 R2
+               },
+       },
+       {
+               name:           "LoweredNilCheck",
+               argLen:         2,
+               nilCheck:       true,
+               faultOnNilArg0: true,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+               },
+       },
+       {
+               name:   "FPFlagTrue",
+               argLen: 1,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "FPFlagFalse",
+               argLen: 1,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+       {
+               name:   "LoweredGetClosurePtr",
+               argLen: 0,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 4194304}, // R22
+                       },
+               },
+       },
+       {
+               name:   "MOVWconvert",
+               argLen: 2,
+               asm:    mips.AMOVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
+                       },
+               },
+       },
+
+       {
+               name:        "ADDV",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AADDVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "ADDVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AADDVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "SUBV",
+               argLen: 2,
+               asm:    mips.ASUBVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SUBVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASUBVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:        "MULV",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
+                       },
+               },
+       },
+       {
+               name:        "MULVU",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
+                       },
+               },
+       },
+       {
+               name:   "DIVV",
+               argLen: 2,
+               asm:    mips.ADIVV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
+                       },
+               },
+       },
+       {
+               name:   "DIVVU",
+               argLen: 2,
+               asm:    mips.ADIVVU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504606846976}, // HI
+                               {1, 2305843009213693952}, // LO
+                       },
+               },
+       },
+       {
+               name:        "ADDF",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AADDF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:        "ADDD",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AADDD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "SUBF",
+               argLen: 2,
+               asm:    mips.ASUBF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "SUBD",
+               argLen: 2,
+               asm:    mips.ASUBD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:        "MULF",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:        "MULD",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AMULD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "DIVF",
+               argLen: 2,
+               asm:    mips.ADIVF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "DIVD",
+               argLen: 2,
+               asm:    mips.ADIVD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:        "AND",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AAND,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "ANDconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AAND,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:        "OR",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "ORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:        "XOR",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.AXOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "XORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.AXOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:        "NOR",
+               argLen:      2,
+               commutative: true,
+               asm:         mips.ANOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "NORconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ANOR,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "NEGV",
+               argLen: 1,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "NEGF",
+               argLen: 1,
+               asm:    mips.ANEGF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "NEGD",
+               argLen: 1,
+               asm:    mips.ANEGD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "SLLV",
+               argLen: 2,
+               asm:    mips.ASLLV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SLLVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASLLV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "SRLV",
+               argLen: 2,
+               asm:    mips.ASRLV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SRLVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASRLV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "SRAV",
+               argLen: 2,
+               asm:    mips.ASRAV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SRAVconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASRAV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "SGT",
+               argLen: 2,
+               asm:    mips.ASGT,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SGTconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASGT,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "SGTU",
+               argLen: 2,
+               asm:    mips.ASGTU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                               {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:    "SGTUconst",
+               auxType: auxInt64,
+               argLen:  1,
+               asm:     mips.ASGTU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:   "CMPEQF",
+               argLen: 2,
+               asm:    mips.ACMPEQF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "CMPEQD",
+               argLen: 2,
+               asm:    mips.ACMPEQD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "CMPGEF",
+               argLen: 2,
+               asm:    mips.ACMPGEF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "CMPGED",
+               argLen: 2,
+               asm:    mips.ACMPGED,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "CMPGTF",
+               argLen: 2,
+               asm:    mips.ACMPGTF,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:   "CMPGTD",
+               argLen: 2,
+               asm:    mips.ACMPGTD,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                               {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:              "MOVVconst",
+               auxType:           auxInt64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               mips.AMOVV,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:              "MOVFconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               mips.AMOVF,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:              "MOVDconst",
+               auxType:           auxFloat64,
+               argLen:            0,
+               rematerializeable: true,
+               asm:               mips.AMOVD,
+               reg: regInfo{
+                       outputs: []outputInfo{
+                               {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+                       },
+               },
+       },
+       {
+               name:              "MOVVaddr",
+               auxType:           auxSymOff,
+               argLen:            1,
+               rematerializeable: true,
+               asm:               mips.AMOVV,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018460942336}, // SP SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:           "MOVBload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVB,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:           "MOVBUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVBU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:           "MOVHload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVH,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:           "MOVHUload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVHU,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:           "MOVWload",
+               auxType:        auxSymOff,
+               argLen:         2,
+               faultOnNilArg0: true,
+               asm:            mips.AMOVW,
+               reg: regInfo{
+                       inputs: []inputInfo{
+                               {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
+                       },
+                       outputs: []outputInfo{
+                               {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
+                       },
+               },
+       },
+       {
+               name:           "MOVWUload",
                auxType:        auxSymOff,
                argLen:         2,
                faultOnNilArg0: true,
@@ -20138,6 +21622,61 @@ var fpRegMaskARM64 = regMask(9223372034707292160)
 var specialRegMaskARM64 = regMask(0)
 var framepointerRegARM64 = int8(-1)
 var linkRegARM64 = int8(29)
+var registersMIPS = [...]Register{
+       {0, mips.REG_R0, "R0"},
+       {1, mips.REG_R1, "R1"},
+       {2, mips.REG_R2, "R2"},
+       {3, mips.REG_R3, "R3"},
+       {4, mips.REG_R4, "R4"},
+       {5, mips.REG_R5, "R5"},
+       {6, mips.REG_R6, "R6"},
+       {7, mips.REG_R7, "R7"},
+       {8, mips.REG_R8, "R8"},
+       {9, mips.REG_R9, "R9"},
+       {10, mips.REG_R10, "R10"},
+       {11, mips.REG_R11, "R11"},
+       {12, mips.REG_R12, "R12"},
+       {13, mips.REG_R13, "R13"},
+       {14, mips.REG_R14, "R14"},
+       {15, mips.REG_R15, "R15"},
+       {16, mips.REG_R16, "R16"},
+       {17, mips.REG_R17, "R17"},
+       {18, mips.REG_R18, "R18"},
+       {19, mips.REG_R19, "R19"},
+       {20, mips.REG_R20, "R20"},
+       {21, mips.REG_R21, "R21"},
+       {22, mips.REG_R22, "R22"},
+       {23, mips.REG_R24, "R24"},
+       {24, mips.REG_R25, "R25"},
+       {25, mips.REG_R28, "R28"},
+       {26, mips.REGSP, "SP"},
+       {27, mips.REGG, "g"},
+       {28, mips.REG_R31, "R31"},
+       {29, mips.REG_F0, "F0"},
+       {30, mips.REG_F2, "F2"},
+       {31, mips.REG_F4, "F4"},
+       {32, mips.REG_F6, "F6"},
+       {33, mips.REG_F8, "F8"},
+       {34, mips.REG_F10, "F10"},
+       {35, mips.REG_F12, "F12"},
+       {36, mips.REG_F14, "F14"},
+       {37, mips.REG_F16, "F16"},
+       {38, mips.REG_F18, "F18"},
+       {39, mips.REG_F20, "F20"},
+       {40, mips.REG_F22, "F22"},
+       {41, mips.REG_F24, "F24"},
+       {42, mips.REG_F26, "F26"},
+       {43, mips.REG_F28, "F28"},
+       {44, mips.REG_F30, "F30"},
+       {45, mips.REG_HI, "HI"},
+       {46, mips.REG_LO, "LO"},
+       {47, 0, "SB"},
+}
+var gpRegMaskMIPS = regMask(335544318)
+var fpRegMaskMIPS = regMask(35183835217920)
+var specialRegMaskMIPS = regMask(105553116266496)
+var framepointerRegMIPS = int8(-1)
+var linkRegMIPS = int8(28)
 var registersMIPS64 = [...]Register{
        {0, mips.REG_R0, "R0"},
        {1, mips.REG_R1, "R1"},

diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS.go b/src/cmd/compile/internal/ssa/rewriteMIPS.go
new file mode 100644 (file)
index 0000000..cbe9f1b
--- /dev/null
+++ b/src/cmd/compile/internal/ssa/rewriteMIPS.go
@@ -0,0 +1,9831 @@
+// autogenerated from gen/MIPS.rules: do not edit!
+// generated with: cd gen; go run *.go
+
+package ssa
+
+import "math"
+
+var _ = math.MinInt8 // in case not otherwise used
+func rewriteValueMIPS(v *Value, config *Config) bool {
+       switch v.Op {
+       case OpAdd16:
+               return rewriteValueMIPS_OpAdd16(v, config)
+       case OpAdd32:
+               return rewriteValueMIPS_OpAdd32(v, config)
+       case OpAdd32F:
+               return rewriteValueMIPS_OpAdd32F(v, config)
+       case OpAdd32withcarry:
+               return rewriteValueMIPS_OpAdd32withcarry(v, config)
+       case OpAdd64F:
+               return rewriteValueMIPS_OpAdd64F(v, config)
+       case OpAdd8:
+               return rewriteValueMIPS_OpAdd8(v, config)
+       case OpAddPtr:
+               return rewriteValueMIPS_OpAddPtr(v, config)
+       case OpAddr:
+               return rewriteValueMIPS_OpAddr(v, config)
+       case OpAnd16:
+               return rewriteValueMIPS_OpAnd16(v, config)
+       case OpAnd32:
+               return rewriteValueMIPS_OpAnd32(v, config)
+       case OpAnd8:
+               return rewriteValueMIPS_OpAnd8(v, config)
+       case OpAndB:
+               return rewriteValueMIPS_OpAndB(v, config)
+       case OpAtomicAdd32:
+               return rewriteValueMIPS_OpAtomicAdd32(v, config)
+       case OpAtomicAnd8:
+               return rewriteValueMIPS_OpAtomicAnd8(v, config)
+       case OpAtomicCompareAndSwap32:
+               return rewriteValueMIPS_OpAtomicCompareAndSwap32(v, config)
+       case OpAtomicExchange32:
+               return rewriteValueMIPS_OpAtomicExchange32(v, config)
+       case OpAtomicLoad32:
+               return rewriteValueMIPS_OpAtomicLoad32(v, config)
+       case OpAtomicLoadPtr:
+               return rewriteValueMIPS_OpAtomicLoadPtr(v, config)
+       case OpAtomicOr8:
+               return rewriteValueMIPS_OpAtomicOr8(v, config)
+       case OpAtomicStore32:
+               return rewriteValueMIPS_OpAtomicStore32(v, config)
+       case OpAtomicStorePtrNoWB:
+               return rewriteValueMIPS_OpAtomicStorePtrNoWB(v, config)
+       case OpClosureCall:
+               return rewriteValueMIPS_OpClosureCall(v, config)
+       case OpCom16:
+               return rewriteValueMIPS_OpCom16(v, config)
+       case OpCom32:
+               return rewriteValueMIPS_OpCom32(v, config)
+       case OpCom8:
+               return rewriteValueMIPS_OpCom8(v, config)
+       case OpConst16:
+               return rewriteValueMIPS_OpConst16(v, config)
+       case OpConst32:
+               return rewriteValueMIPS_OpConst32(v, config)
+       case OpConst32F:
+               return rewriteValueMIPS_OpConst32F(v, config)
+       case OpConst64F:
+               return rewriteValueMIPS_OpConst64F(v, config)
+       case OpConst8:
+               return rewriteValueMIPS_OpConst8(v, config)
+       case OpConstBool:
+               return rewriteValueMIPS_OpConstBool(v, config)
+       case OpConstNil:
+               return rewriteValueMIPS_OpConstNil(v, config)
+       case OpConvert:
+               return rewriteValueMIPS_OpConvert(v, config)
+       case OpCtz32:
+               return rewriteValueMIPS_OpCtz32(v, config)
+       case OpCvt32Fto32:
+               return rewriteValueMIPS_OpCvt32Fto32(v, config)
+       case OpCvt32Fto64F:
+               return rewriteValueMIPS_OpCvt32Fto64F(v, config)
+       case OpCvt32to32F:
+               return rewriteValueMIPS_OpCvt32to32F(v, config)
+       case OpCvt32to64F:
+               return rewriteValueMIPS_OpCvt32to64F(v, config)
+       case OpCvt64Fto32:
+               return rewriteValueMIPS_OpCvt64Fto32(v, config)
+       case OpCvt64Fto32F:
+               return rewriteValueMIPS_OpCvt64Fto32F(v, config)
+       case OpDeferCall:
+               return rewriteValueMIPS_OpDeferCall(v, config)
+       case OpDiv16:
+               return rewriteValueMIPS_OpDiv16(v, config)
+       case OpDiv16u:
+               return rewriteValueMIPS_OpDiv16u(v, config)
+       case OpDiv32:
+               return rewriteValueMIPS_OpDiv32(v, config)
+       case OpDiv32F:
+               return rewriteValueMIPS_OpDiv32F(v, config)
+       case OpDiv32u:
+               return rewriteValueMIPS_OpDiv32u(v, config)
+       case OpDiv64F:
+               return rewriteValueMIPS_OpDiv64F(v, config)
+       case OpDiv8:
+               return rewriteValueMIPS_OpDiv8(v, config)
+       case OpDiv8u:
+               return rewriteValueMIPS_OpDiv8u(v, config)
+       case OpEq16:
+               return rewriteValueMIPS_OpEq16(v, config)
+       case OpEq32:
+               return rewriteValueMIPS_OpEq32(v, config)
+       case OpEq32F:
+               return rewriteValueMIPS_OpEq32F(v, config)
+       case OpEq64F:
+               return rewriteValueMIPS_OpEq64F(v, config)
+       case OpEq8:
+               return rewriteValueMIPS_OpEq8(v, config)
+       case OpEqB:
+               return rewriteValueMIPS_OpEqB(v, config)
+       case OpEqPtr:
+               return rewriteValueMIPS_OpEqPtr(v, config)
+       case OpGeq16:
+               return rewriteValueMIPS_OpGeq16(v, config)
+       case OpGeq16U:
+               return rewriteValueMIPS_OpGeq16U(v, config)
+       case OpGeq32:
+               return rewriteValueMIPS_OpGeq32(v, config)
+       case OpGeq32F:
+               return rewriteValueMIPS_OpGeq32F(v, config)
+       case OpGeq32U:
+               return rewriteValueMIPS_OpGeq32U(v, config)
+       case OpGeq64F:
+               return rewriteValueMIPS_OpGeq64F(v, config)
+       case OpGeq8:
+               return rewriteValueMIPS_OpGeq8(v, config)
+       case OpGeq8U:
+               return rewriteValueMIPS_OpGeq8U(v, config)
+       case OpGetClosurePtr:
+               return rewriteValueMIPS_OpGetClosurePtr(v, config)
+       case OpGoCall:
+               return rewriteValueMIPS_OpGoCall(v, config)
+       case OpGreater16:
+               return rewriteValueMIPS_OpGreater16(v, config)
+       case OpGreater16U:
+               return rewriteValueMIPS_OpGreater16U(v, config)
+       case OpGreater32:
+               return rewriteValueMIPS_OpGreater32(v, config)
+       case OpGreater32F:
+               return rewriteValueMIPS_OpGreater32F(v, config)
+       case OpGreater32U:
+               return rewriteValueMIPS_OpGreater32U(v, config)
+       case OpGreater64F:
+               return rewriteValueMIPS_OpGreater64F(v, config)
+       case OpGreater8:
+               return rewriteValueMIPS_OpGreater8(v, config)
+       case OpGreater8U:
+               return rewriteValueMIPS_OpGreater8U(v, config)
+       case OpHmul16:
+               return rewriteValueMIPS_OpHmul16(v, config)
+       case OpHmul16u:
+               return rewriteValueMIPS_OpHmul16u(v, config)
+       case OpHmul32:
+               return rewriteValueMIPS_OpHmul32(v, config)
+       case OpHmul32u:
+               return rewriteValueMIPS_OpHmul32u(v, config)
+       case OpHmul8:
+               return rewriteValueMIPS_OpHmul8(v, config)
+       case OpHmul8u:
+               return rewriteValueMIPS_OpHmul8u(v, config)
+       case OpInterCall:
+               return rewriteValueMIPS_OpInterCall(v, config)
+       case OpIsInBounds:
+               return rewriteValueMIPS_OpIsInBounds(v, config)
+       case OpIsNonNil:
+               return rewriteValueMIPS_OpIsNonNil(v, config)
+       case OpIsSliceInBounds:
+               return rewriteValueMIPS_OpIsSliceInBounds(v, config)
+       case OpLeq16:
+               return rewriteValueMIPS_OpLeq16(v, config)
+       case OpLeq16U:
+               return rewriteValueMIPS_OpLeq16U(v, config)
+       case OpLeq32:
+               return rewriteValueMIPS_OpLeq32(v, config)
+       case OpLeq32F:
+               return rewriteValueMIPS_OpLeq32F(v, config)
+       case OpLeq32U:
+               return rewriteValueMIPS_OpLeq32U(v, config)
+       case OpLeq64F:
+               return rewriteValueMIPS_OpLeq64F(v, config)
+       case OpLeq8:
+               return rewriteValueMIPS_OpLeq8(v, config)
+       case OpLeq8U:
+               return rewriteValueMIPS_OpLeq8U(v, config)
+       case OpLess16:
+               return rewriteValueMIPS_OpLess16(v, config)
+       case OpLess16U:
+               return rewriteValueMIPS_OpLess16U(v, config)
+       case OpLess32:
+               return rewriteValueMIPS_OpLess32(v, config)
+       case OpLess32F:
+               return rewriteValueMIPS_OpLess32F(v, config)
+       case OpLess32U:
+               return rewriteValueMIPS_OpLess32U(v, config)
+       case OpLess64F:
+               return rewriteValueMIPS_OpLess64F(v, config)
+       case OpLess8:
+               return rewriteValueMIPS_OpLess8(v, config)
+       case OpLess8U:
+               return rewriteValueMIPS_OpLess8U(v, config)
+       case OpLoad:
+               return rewriteValueMIPS_OpLoad(v, config)
+       case OpLsh16x16:
+               return rewriteValueMIPS_OpLsh16x16(v, config)
+       case OpLsh16x32:
+               return rewriteValueMIPS_OpLsh16x32(v, config)
+       case OpLsh16x64:
+               return rewriteValueMIPS_OpLsh16x64(v, config)
+       case OpLsh16x8:
+               return rewriteValueMIPS_OpLsh16x8(v, config)
+       case OpLsh32x16:
+               return rewriteValueMIPS_OpLsh32x16(v, config)
+       case OpLsh32x32:
+               return rewriteValueMIPS_OpLsh32x32(v, config)
+       case OpLsh32x64:
+               return rewriteValueMIPS_OpLsh32x64(v, config)
+       case OpLsh32x8:
+               return rewriteValueMIPS_OpLsh32x8(v, config)
+       case OpLsh8x16:
+               return rewriteValueMIPS_OpLsh8x16(v, config)
+       case OpLsh8x32:
+               return rewriteValueMIPS_OpLsh8x32(v, config)
+       case OpLsh8x64:
+               return rewriteValueMIPS_OpLsh8x64(v, config)
+       case OpLsh8x8:
+               return rewriteValueMIPS_OpLsh8x8(v, config)
+       case OpMIPSADD:
+               return rewriteValueMIPS_OpMIPSADD(v, config)
+       case OpMIPSADDconst:
+               return rewriteValueMIPS_OpMIPSADDconst(v, config)
+       case OpMIPSAND:
+               return rewriteValueMIPS_OpMIPSAND(v, config)
+       case OpMIPSANDconst:
+               return rewriteValueMIPS_OpMIPSANDconst(v, config)
+       case OpMIPSCMOVZ:
+               return rewriteValueMIPS_OpMIPSCMOVZ(v, config)
+       case OpMIPSCMOVZzero:
+               return rewriteValueMIPS_OpMIPSCMOVZzero(v, config)
+       case OpMIPSLoweredAtomicAdd:
+               return rewriteValueMIPS_OpMIPSLoweredAtomicAdd(v, config)
+       case OpMIPSLoweredAtomicStore:
+               return rewriteValueMIPS_OpMIPSLoweredAtomicStore(v, config)
+       case OpMIPSMOVBUload:
+               return rewriteValueMIPS_OpMIPSMOVBUload(v, config)
+       case OpMIPSMOVBUreg:
+               return rewriteValueMIPS_OpMIPSMOVBUreg(v, config)
+       case OpMIPSMOVBload:
+               return rewriteValueMIPS_OpMIPSMOVBload(v, config)
+       case OpMIPSMOVBreg:
+               return rewriteValueMIPS_OpMIPSMOVBreg(v, config)
+       case OpMIPSMOVBstore:
+               return rewriteValueMIPS_OpMIPSMOVBstore(v, config)
+       case OpMIPSMOVBstorezero:
+               return rewriteValueMIPS_OpMIPSMOVBstorezero(v, config)
+       case OpMIPSMOVDload:
+               return rewriteValueMIPS_OpMIPSMOVDload(v, config)
+       case OpMIPSMOVDstore:
+               return rewriteValueMIPS_OpMIPSMOVDstore(v, config)
+       case OpMIPSMOVFload:
+               return rewriteValueMIPS_OpMIPSMOVFload(v, config)
+       case OpMIPSMOVFstore:
+               return rewriteValueMIPS_OpMIPSMOVFstore(v, config)
+       case OpMIPSMOVHUload:
+               return rewriteValueMIPS_OpMIPSMOVHUload(v, config)
+       case OpMIPSMOVHUreg:
+               return rewriteValueMIPS_OpMIPSMOVHUreg(v, config)
+       case OpMIPSMOVHload:
+               return rewriteValueMIPS_OpMIPSMOVHload(v, config)
+       case OpMIPSMOVHreg:
+               return rewriteValueMIPS_OpMIPSMOVHreg(v, config)
+       case OpMIPSMOVHstore:
+               return rewriteValueMIPS_OpMIPSMOVHstore(v, config)
+       case OpMIPSMOVHstorezero:
+               return rewriteValueMIPS_OpMIPSMOVHstorezero(v, config)
+       case OpMIPSMOVWload:
+               return rewriteValueMIPS_OpMIPSMOVWload(v, config)
+       case OpMIPSMOVWreg:
+               return rewriteValueMIPS_OpMIPSMOVWreg(v, config)
+       case OpMIPSMOVWstore:
+               return rewriteValueMIPS_OpMIPSMOVWstore(v, config)
+       case OpMIPSMOVWstorezero:
+               return rewriteValueMIPS_OpMIPSMOVWstorezero(v, config)
+       case OpMIPSMUL:
+               return rewriteValueMIPS_OpMIPSMUL(v, config)
+       case OpMIPSNEG:
+               return rewriteValueMIPS_OpMIPSNEG(v, config)
+       case OpMIPSNOR:
+               return rewriteValueMIPS_OpMIPSNOR(v, config)
+       case OpMIPSNORconst:
+               return rewriteValueMIPS_OpMIPSNORconst(v, config)
+       case OpMIPSOR:
+               return rewriteValueMIPS_OpMIPSOR(v, config)
+       case OpMIPSORconst:
+               return rewriteValueMIPS_OpMIPSORconst(v, config)
+       case OpMIPSSGT:
+               return rewriteValueMIPS_OpMIPSSGT(v, config)
+       case OpMIPSSGTU:
+               return rewriteValueMIPS_OpMIPSSGTU(v, config)
+       case OpMIPSSGTUconst:
+               return rewriteValueMIPS_OpMIPSSGTUconst(v, config)
+       case OpMIPSSGTUzero:
+               return rewriteValueMIPS_OpMIPSSGTUzero(v, config)
+       case OpMIPSSGTconst:
+               return rewriteValueMIPS_OpMIPSSGTconst(v, config)
+       case OpMIPSSGTzero:
+               return rewriteValueMIPS_OpMIPSSGTzero(v, config)
+       case OpMIPSSLL:
+               return rewriteValueMIPS_OpMIPSSLL(v, config)
+       case OpMIPSSLLconst:
+               return rewriteValueMIPS_OpMIPSSLLconst(v, config)
+       case OpMIPSSRA:
+               return rewriteValueMIPS_OpMIPSSRA(v, config)
+       case OpMIPSSRAconst:
+               return rewriteValueMIPS_OpMIPSSRAconst(v, config)
+       case OpMIPSSRL:
+               return rewriteValueMIPS_OpMIPSSRL(v, config)
+       case OpMIPSSRLconst:
+               return rewriteValueMIPS_OpMIPSSRLconst(v, config)
+       case OpMIPSSUB:
+               return rewriteValueMIPS_OpMIPSSUB(v, config)
+       case OpMIPSSUBconst:
+               return rewriteValueMIPS_OpMIPSSUBconst(v, config)
+       case OpMIPSXOR:
+               return rewriteValueMIPS_OpMIPSXOR(v, config)
+       case OpMIPSXORconst:
+               return rewriteValueMIPS_OpMIPSXORconst(v, config)
+       case OpMod16:
+               return rewriteValueMIPS_OpMod16(v, config)
+       case OpMod16u:
+               return rewriteValueMIPS_OpMod16u(v, config)
+       case OpMod32:
+               return rewriteValueMIPS_OpMod32(v, config)
+       case OpMod32u:
+               return rewriteValueMIPS_OpMod32u(v, config)
+       case OpMod8:
+               return rewriteValueMIPS_OpMod8(v, config)
+       case OpMod8u:
+               return rewriteValueMIPS_OpMod8u(v, config)
+       case OpMove:
+               return rewriteValueMIPS_OpMove(v, config)
+       case OpMul16:
+               return rewriteValueMIPS_OpMul16(v, config)
+       case OpMul32:
+               return rewriteValueMIPS_OpMul32(v, config)
+       case OpMul32F:
+               return rewriteValueMIPS_OpMul32F(v, config)
+       case OpMul32uhilo:
+               return rewriteValueMIPS_OpMul32uhilo(v, config)
+       case OpMul64F:
+               return rewriteValueMIPS_OpMul64F(v, config)
+       case OpMul8:
+               return rewriteValueMIPS_OpMul8(v, config)
+       case OpNeg16:
+               return rewriteValueMIPS_OpNeg16(v, config)
+       case OpNeg32:
+               return rewriteValueMIPS_OpNeg32(v, config)
+       case OpNeg32F:
+               return rewriteValueMIPS_OpNeg32F(v, config)
+       case OpNeg64F:
+               return rewriteValueMIPS_OpNeg64F(v, config)
+       case OpNeg8:
+               return rewriteValueMIPS_OpNeg8(v, config)
+       case OpNeq16:
+               return rewriteValueMIPS_OpNeq16(v, config)
+       case OpNeq32:
+               return rewriteValueMIPS_OpNeq32(v, config)
+       case OpNeq32F:
+               return rewriteValueMIPS_OpNeq32F(v, config)
+       case OpNeq64F:
+               return rewriteValueMIPS_OpNeq64F(v, config)
+       case OpNeq8:
+               return rewriteValueMIPS_OpNeq8(v, config)
+       case OpNeqB:
+               return rewriteValueMIPS_OpNeqB(v, config)
+       case OpNeqPtr:
+               return rewriteValueMIPS_OpNeqPtr(v, config)
+       case OpNilCheck:
+               return rewriteValueMIPS_OpNilCheck(v, config)
+       case OpNot:
+               return rewriteValueMIPS_OpNot(v, config)
+       case OpOffPtr:
+               return rewriteValueMIPS_OpOffPtr(v, config)
+       case OpOr16:
+               return rewriteValueMIPS_OpOr16(v, config)
+       case OpOr32:
+               return rewriteValueMIPS_OpOr32(v, config)
+       case OpOr8:
+               return rewriteValueMIPS_OpOr8(v, config)
+       case OpOrB:
+               return rewriteValueMIPS_OpOrB(v, config)
+       case OpRsh16Ux16:
+               return rewriteValueMIPS_OpRsh16Ux16(v, config)
+       case OpRsh16Ux32:
+               return rewriteValueMIPS_OpRsh16Ux32(v, config)
+       case OpRsh16Ux64:
+               return rewriteValueMIPS_OpRsh16Ux64(v, config)
+       case OpRsh16Ux8:
+               return rewriteValueMIPS_OpRsh16Ux8(v, config)
+       case OpRsh16x16:
+               return rewriteValueMIPS_OpRsh16x16(v, config)
+       case OpRsh16x32:
+               return rewriteValueMIPS_OpRsh16x32(v, config)
+       case OpRsh16x64:
+               return rewriteValueMIPS_OpRsh16x64(v, config)
+       case OpRsh16x8:
+               return rewriteValueMIPS_OpRsh16x8(v, config)
+       case OpRsh32Ux16:
+               return rewriteValueMIPS_OpRsh32Ux16(v, config)
+       case OpRsh32Ux32:
+               return rewriteValueMIPS_OpRsh32Ux32(v, config)
+       case OpRsh32Ux64:
+               return rewriteValueMIPS_OpRsh32Ux64(v, config)
+       case OpRsh32Ux8:
+               return rewriteValueMIPS_OpRsh32Ux8(v, config)
+       case OpRsh32x16:
+               return rewriteValueMIPS_OpRsh32x16(v, config)
+       case OpRsh32x32:
+               return rewriteValueMIPS_OpRsh32x32(v, config)
+       case OpRsh32x64:
+               return rewriteValueMIPS_OpRsh32x64(v, config)
+       case OpRsh32x8:
+               return rewriteValueMIPS_OpRsh32x8(v, config)
+       case OpRsh8Ux16:
+               return rewriteValueMIPS_OpRsh8Ux16(v, config)
+       case OpRsh8Ux32:
+               return rewriteValueMIPS_OpRsh8Ux32(v, config)
+       case OpRsh8Ux64:
+               return rewriteValueMIPS_OpRsh8Ux64(v, config)
+       case OpRsh8Ux8:
+               return rewriteValueMIPS_OpRsh8Ux8(v, config)
+       case OpRsh8x16:
+               return rewriteValueMIPS_OpRsh8x16(v, config)
+       case OpRsh8x32:
+               return rewriteValueMIPS_OpRsh8x32(v, config)
+       case OpRsh8x64:
+               return rewriteValueMIPS_OpRsh8x64(v, config)
+       case OpRsh8x8:
+               return rewriteValueMIPS_OpRsh8x8(v, config)
+       case OpSelect0:
+               return rewriteValueMIPS_OpSelect0(v, config)
+       case OpSelect1:
+               return rewriteValueMIPS_OpSelect1(v, config)
+       case OpSignExt16to32:
+               return rewriteValueMIPS_OpSignExt16to32(v, config)
+       case OpSignExt8to16:
+               return rewriteValueMIPS_OpSignExt8to16(v, config)
+       case OpSignExt8to32:
+               return rewriteValueMIPS_OpSignExt8to32(v, config)
+       case OpSignmask:
+               return rewriteValueMIPS_OpSignmask(v, config)
+       case OpSlicemask:
+               return rewriteValueMIPS_OpSlicemask(v, config)
+       case OpSqrt:
+               return rewriteValueMIPS_OpSqrt(v, config)
+       case OpStaticCall:
+               return rewriteValueMIPS_OpStaticCall(v, config)
+       case OpStore:
+               return rewriteValueMIPS_OpStore(v, config)
+       case OpSub16:
+               return rewriteValueMIPS_OpSub16(v, config)
+       case OpSub32:
+               return rewriteValueMIPS_OpSub32(v, config)
+       case OpSub32F:
+               return rewriteValueMIPS_OpSub32F(v, config)
+       case OpSub32withcarry:
+               return rewriteValueMIPS_OpSub32withcarry(v, config)
+       case OpSub64F:
+               return rewriteValueMIPS_OpSub64F(v, config)
+       case OpSub8:
+               return rewriteValueMIPS_OpSub8(v, config)
+       case OpSubPtr:
+               return rewriteValueMIPS_OpSubPtr(v, config)
+       case OpTrunc16to8:
+               return rewriteValueMIPS_OpTrunc16to8(v, config)
+       case OpTrunc32to16:
+               return rewriteValueMIPS_OpTrunc32to16(v, config)
+       case OpTrunc32to8:
+               return rewriteValueMIPS_OpTrunc32to8(v, config)
+       case OpXor16:
+               return rewriteValueMIPS_OpXor16(v, config)
+       case OpXor32:
+               return rewriteValueMIPS_OpXor32(v, config)
+       case OpXor8:
+               return rewriteValueMIPS_OpXor8(v, config)
+       case OpZero:
+               return rewriteValueMIPS_OpZero(v, config)
+       case OpZeroExt16to32:
+               return rewriteValueMIPS_OpZeroExt16to32(v, config)
+       case OpZeroExt8to16:
+               return rewriteValueMIPS_OpZeroExt8to16(v, config)
+       case OpZeroExt8to32:
+               return rewriteValueMIPS_OpZeroExt8to32(v, config)
+       case OpZeromask:
+               return rewriteValueMIPS_OpZeromask(v, config)
+       }
+       return false
+}
+func rewriteValueMIPS_OpAdd16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Add16 x y)
+       // cond:
+       // result: (ADD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSADD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAdd32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Add32 x y)
+       // cond:
+       // result: (ADD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSADD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAdd32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Add32F x y)
+       // cond:
+       // result: (ADDF x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSADDF)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAdd32withcarry(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Add32withcarry <t> x y c)
+       // cond:
+       // result: (ADD c (ADD <t> x y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               c := v.Args[2]
+               v.reset(OpMIPSADD)
+               v.AddArg(c)
+               v0 := b.NewValue0(v.Line, OpMIPSADD, t)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAdd64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Add64F x y)
+       // cond:
+       // result: (ADDD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSADDD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAdd8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Add8 x y)
+       // cond:
+       // result: (ADD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSADD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAddPtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AddPtr x y)
+       // cond:
+       // result: (ADD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSADD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAddr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Addr {sym} base)
+       // cond:
+       // result: (MOVWaddr {sym} base)
+       for {
+               sym := v.Aux
+               base := v.Args[0]
+               v.reset(OpMIPSMOVWaddr)
+               v.Aux = sym
+               v.AddArg(base)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAnd16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (And16 x y)
+       // cond:
+       // result: (AND x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSAND)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAnd32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (And32 x y)
+       // cond:
+       // result: (AND x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSAND)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAnd8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (And8 x y)
+       // cond:
+       // result: (AND x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSAND)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAndB(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AndB x y)
+       // cond:
+       // result: (AND x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSAND)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicAdd32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicAdd32 ptr val mem)
+       // cond:
+       // result: (LoweredAtomicAdd ptr val mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSLoweredAtomicAdd)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicAnd8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicAnd8  ptr val mem)
+       // cond: !config.BigEndian
+       // result: (LoweredAtomicAnd (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)                (OR <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)                   (SLLconst <config.fe.TypeUInt32()> [3]                          (ANDconst  <config.fe.TypeUInt32()> [3] ptr)))          (NORconst [0] <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()>                    (MOVWconst [0xff]) (SLLconst <config.fe.TypeUInt32()> [3]                               (ANDconst <config.fe.TypeUInt32()> [3]                                  (XORconst <config.fe.TypeUInt32()> [3] ptr)))))) mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(!config.BigEndian) {
+                       break
+               }
+               v.reset(OpMIPSLoweredAtomicAnd)
+               v0 := b.NewValue0(v.Line, OpMIPSAND, config.fe.TypeUInt32().PtrTo())
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = ^3
+               v0.AddArg(v1)
+               v0.AddArg(ptr)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSOR, config.fe.TypeUInt32())
+               v3 := b.NewValue0(v.Line, OpMIPSSLL, config.fe.TypeUInt32())
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(val)
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v5.AuxInt = 3
+               v6 := b.NewValue0(v.Line, OpMIPSANDconst, config.fe.TypeUInt32())
+               v6.AuxInt = 3
+               v6.AddArg(ptr)
+               v5.AddArg(v6)
+               v3.AddArg(v5)
+               v2.AddArg(v3)
+               v7 := b.NewValue0(v.Line, OpMIPSNORconst, config.fe.TypeUInt32())
+               v7.AuxInt = 0
+               v8 := b.NewValue0(v.Line, OpMIPSSLL, config.fe.TypeUInt32())
+               v9 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v9.AuxInt = 0xff
+               v8.AddArg(v9)
+               v10 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v10.AuxInt = 3
+               v11 := b.NewValue0(v.Line, OpMIPSANDconst, config.fe.TypeUInt32())
+               v11.AuxInt = 3
+               v12 := b.NewValue0(v.Line, OpMIPSXORconst, config.fe.TypeUInt32())
+               v12.AuxInt = 3
+               v12.AddArg(ptr)
+               v11.AddArg(v12)
+               v10.AddArg(v11)
+               v8.AddArg(v10)
+               v7.AddArg(v8)
+               v2.AddArg(v7)
+               v.AddArg(v2)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (AtomicAnd8  ptr val mem)
+       // cond: config.BigEndian
+       // result: (LoweredAtomicAnd (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)                (OR <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)                   (SLLconst <config.fe.TypeUInt32()> [3]                          (ANDconst  <config.fe.TypeUInt32()> [3]                                         (XORconst <config.fe.TypeUInt32()> [3] ptr))))          (NORconst [0] <config.fe.TypeUInt32()> (SLL <config.fe.TypeUInt32()>                    (MOVWconst [0xff]) (SLLconst <config.fe.TypeUInt32()> [3]                               (ANDconst <config.fe.TypeUInt32()> [3]                                  (XORconst <config.fe.TypeUInt32()> [3] ptr)))))) mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(config.BigEndian) {
+                       break
+               }
+               v.reset(OpMIPSLoweredAtomicAnd)
+               v0 := b.NewValue0(v.Line, OpMIPSAND, config.fe.TypeUInt32().PtrTo())
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = ^3
+               v0.AddArg(v1)
+               v0.AddArg(ptr)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSOR, config.fe.TypeUInt32())
+               v3 := b.NewValue0(v.Line, OpMIPSSLL, config.fe.TypeUInt32())
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(val)
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v5.AuxInt = 3
+               v6 := b.NewValue0(v.Line, OpMIPSANDconst, config.fe.TypeUInt32())
+               v6.AuxInt = 3
+               v7 := b.NewValue0(v.Line, OpMIPSXORconst, config.fe.TypeUInt32())
+               v7.AuxInt = 3
+               v7.AddArg(ptr)
+               v6.AddArg(v7)
+               v5.AddArg(v6)
+               v3.AddArg(v5)
+               v2.AddArg(v3)
+               v8 := b.NewValue0(v.Line, OpMIPSNORconst, config.fe.TypeUInt32())
+               v8.AuxInt = 0
+               v9 := b.NewValue0(v.Line, OpMIPSSLL, config.fe.TypeUInt32())
+               v10 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v10.AuxInt = 0xff
+               v9.AddArg(v10)
+               v11 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v11.AuxInt = 3
+               v12 := b.NewValue0(v.Line, OpMIPSANDconst, config.fe.TypeUInt32())
+               v12.AuxInt = 3
+               v13 := b.NewValue0(v.Line, OpMIPSXORconst, config.fe.TypeUInt32())
+               v13.AuxInt = 3
+               v13.AddArg(ptr)
+               v12.AddArg(v13)
+               v11.AddArg(v12)
+               v9.AddArg(v11)
+               v8.AddArg(v9)
+               v2.AddArg(v8)
+               v.AddArg(v2)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpAtomicCompareAndSwap32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicCompareAndSwap32 ptr old new_ mem)
+       // cond:
+       // result: (LoweredAtomicCas ptr old new_ mem)
+       for {
+               ptr := v.Args[0]
+               old := v.Args[1]
+               new_ := v.Args[2]
+               mem := v.Args[3]
+               v.reset(OpMIPSLoweredAtomicCas)
+               v.AddArg(ptr)
+               v.AddArg(old)
+               v.AddArg(new_)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicExchange32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicExchange32 ptr val mem)
+       // cond:
+       // result: (LoweredAtomicExchange ptr val mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSLoweredAtomicExchange)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicLoad32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicLoad32  ptr mem)
+       // cond:
+       // result: (LoweredAtomicLoad ptr mem)
+       for {
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               v.reset(OpMIPSLoweredAtomicLoad)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicLoadPtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicLoadPtr ptr mem)
+       // cond:
+       // result: (LoweredAtomicLoad  ptr mem)
+       for {
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               v.reset(OpMIPSLoweredAtomicLoad)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicOr8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicOr8 ptr val mem)
+       // cond: !config.BigEndian
+       // result: (LoweredAtomicOr (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)                 (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)                        (SLLconst <config.fe.TypeUInt32()> [3]                          (ANDconst <config.fe.TypeUInt32()> [3] ptr))) mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(!config.BigEndian) {
+                       break
+               }
+               v.reset(OpMIPSLoweredAtomicOr)
+               v0 := b.NewValue0(v.Line, OpMIPSAND, config.fe.TypeUInt32().PtrTo())
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = ^3
+               v0.AddArg(v1)
+               v0.AddArg(ptr)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSSLL, config.fe.TypeUInt32())
+               v3 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v3.AddArg(val)
+               v2.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v4.AuxInt = 3
+               v5 := b.NewValue0(v.Line, OpMIPSANDconst, config.fe.TypeUInt32())
+               v5.AuxInt = 3
+               v5.AddArg(ptr)
+               v4.AddArg(v5)
+               v2.AddArg(v4)
+               v.AddArg(v2)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (AtomicOr8 ptr val mem)
+       // cond: config.BigEndian
+       // result: (LoweredAtomicOr (AND <config.fe.TypeUInt32().PtrTo()> (MOVWconst [^3]) ptr)                 (SLL <config.fe.TypeUInt32()> (ZeroExt8to32 val)                        (SLLconst <config.fe.TypeUInt32()> [3]                          (ANDconst <config.fe.TypeUInt32()> [3]                                  (XORconst <config.fe.TypeUInt32()> [3] ptr)))) mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(config.BigEndian) {
+                       break
+               }
+               v.reset(OpMIPSLoweredAtomicOr)
+               v0 := b.NewValue0(v.Line, OpMIPSAND, config.fe.TypeUInt32().PtrTo())
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = ^3
+               v0.AddArg(v1)
+               v0.AddArg(ptr)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSSLL, config.fe.TypeUInt32())
+               v3 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v3.AddArg(val)
+               v2.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v4.AuxInt = 3
+               v5 := b.NewValue0(v.Line, OpMIPSANDconst, config.fe.TypeUInt32())
+               v5.AuxInt = 3
+               v6 := b.NewValue0(v.Line, OpMIPSXORconst, config.fe.TypeUInt32())
+               v6.AuxInt = 3
+               v6.AddArg(ptr)
+               v5.AddArg(v6)
+               v4.AddArg(v5)
+               v2.AddArg(v4)
+               v.AddArg(v2)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpAtomicStore32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicStore32      ptr val mem)
+       // cond:
+       // result: (LoweredAtomicStore ptr val mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSLoweredAtomicStore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpAtomicStorePtrNoWB(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AtomicStorePtrNoWB ptr val mem)
+       // cond:
+       // result: (LoweredAtomicStore  ptr val mem)
+       for {
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSLoweredAtomicStore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpClosureCall(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ClosureCall [argwid] entry closure mem)
+       // cond:
+       // result: (CALLclosure [argwid] entry closure mem)
+       for {
+               argwid := v.AuxInt
+               entry := v.Args[0]
+               closure := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSCALLclosure)
+               v.AuxInt = argwid
+               v.AddArg(entry)
+               v.AddArg(closure)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCom16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Com16 x)
+       // cond:
+       // result: (NORconst [0] x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNORconst)
+               v.AuxInt = 0
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCom32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Com32 x)
+       // cond:
+       // result: (NORconst [0] x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNORconst)
+               v.AuxInt = 0
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCom8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Com8 x)
+       // cond:
+       // result: (NORconst [0] x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNORconst)
+               v.AuxInt = 0
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpConst16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Const16 [val])
+       // cond:
+       // result: (MOVWconst [val])
+       for {
+               val := v.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = val
+               return true
+       }
+}
+func rewriteValueMIPS_OpConst32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Const32 [val])
+       // cond:
+       // result: (MOVWconst [val])
+       for {
+               val := v.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = val
+               return true
+       }
+}
+func rewriteValueMIPS_OpConst32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Const32F [val])
+       // cond:
+       // result: (MOVFconst [val])
+       for {
+               val := v.AuxInt
+               v.reset(OpMIPSMOVFconst)
+               v.AuxInt = val
+               return true
+       }
+}
+func rewriteValueMIPS_OpConst64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Const64F [val])
+       // cond:
+       // result: (MOVDconst [val])
+       for {
+               val := v.AuxInt
+               v.reset(OpMIPSMOVDconst)
+               v.AuxInt = val
+               return true
+       }
+}
+func rewriteValueMIPS_OpConst8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Const8 [val])
+       // cond:
+       // result: (MOVWconst [val])
+       for {
+               val := v.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = val
+               return true
+       }
+}
+func rewriteValueMIPS_OpConstBool(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ConstBool [b])
+       // cond:
+       // result: (MOVWconst [b])
+       for {
+               b := v.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = b
+               return true
+       }
+}
+func rewriteValueMIPS_OpConstNil(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ConstNil)
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+}
+func rewriteValueMIPS_OpConvert(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Convert x mem)
+       // cond:
+       // result: (MOVWconvert x mem)
+       for {
+               x := v.Args[0]
+               mem := v.Args[1]
+               v.reset(OpMIPSMOVWconvert)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCtz32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Ctz32 <t> x)
+       // cond:
+       // result: (SUB (MOVWconst [32]) (CLZ <t> (SUBconst <t> [1] (AND <t> x (NEG <t> x)))))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               v.reset(OpMIPSSUB)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 32
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCLZ, t)
+               v2 := b.NewValue0(v.Line, OpMIPSSUBconst, t)
+               v2.AuxInt = 1
+               v3 := b.NewValue0(v.Line, OpMIPSAND, t)
+               v3.AddArg(x)
+               v4 := b.NewValue0(v.Line, OpMIPSNEG, t)
+               v4.AddArg(x)
+               v3.AddArg(v4)
+               v2.AddArg(v3)
+               v1.AddArg(v2)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCvt32Fto32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Cvt32Fto32 x)
+       // cond:
+       // result: (TRUNCFW x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSTRUNCFW)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCvt32Fto64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Cvt32Fto64F x)
+       // cond:
+       // result: (MOVFD x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVFD)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCvt32to32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Cvt32to32F x)
+       // cond:
+       // result: (MOVWF x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVWF)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCvt32to64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Cvt32to64F x)
+       // cond:
+       // result: (MOVWD x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVWD)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCvt64Fto32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Cvt64Fto32 x)
+       // cond:
+       // result: (TRUNCDW x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSTRUNCDW)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpCvt64Fto32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Cvt64Fto32F x)
+       // cond:
+       // result: (MOVDF x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVDF)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDeferCall(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (DeferCall [argwid] mem)
+       // cond:
+       // result: (CALLdefer [argwid] mem)
+       for {
+               argwid := v.AuxInt
+               mem := v.Args[0]
+               v.reset(OpMIPSCALLdefer)
+               v.AuxInt = argwid
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div16 x y)
+       // cond:
+       // result: (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSDIV, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv16u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div16u x y)
+       // cond:
+       // result: (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSDIVU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div32 x y)
+       // cond:
+       // result: (Select1 (DIV x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSDIV, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div32F x y)
+       // cond:
+       // result: (DIVF x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSDIVF)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv32u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div32u x y)
+       // cond:
+       // result: (Select1 (DIVU x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSDIVU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div64F x y)
+       // cond:
+       // result: (DIVD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSDIVD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div8 x y)
+       // cond:
+       // result: (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSDIV, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpDiv8u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Div8u x y)
+       // cond:
+       // result: (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSDIVU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEq16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Eq16 x y)
+       // cond:
+       // result: (SGTUconst [1] (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTUconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEq32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Eq32 x y)
+       // cond:
+       // result: (SGTUconst [1] (XOR x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTUconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEq32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Eq32F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPEQF x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPEQF, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEq64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Eq64F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPEQD x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPEQD, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEq8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Eq8 x y)
+       // cond:
+       // result: (SGTUconst [1] (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTUconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEqB(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (EqB x y)
+       // cond:
+       // result: (XORconst [1] (XOR <config.fe.TypeBool()> x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeBool())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpEqPtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (EqPtr x y)
+       // cond:
+       // result: (SGTUconst [1] (XOR x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTUconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq16 x y)
+       // cond:
+       // result: (XORconst [1] (SGT (SignExt16to32 y) (SignExt16to32 x)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v2.AddArg(x)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq16U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq16U x y)
+       // cond:
+       // result: (XORconst [1] (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(x)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq32 x y)
+       // cond:
+       // result: (XORconst [1] (SGT y x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v0.AddArg(y)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq32F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGEF x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGEF, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq32U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq32U x y)
+       // cond:
+       // result: (XORconst [1] (SGTU y x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v0.AddArg(y)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq64F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGED x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGED, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq8 x y)
+       // cond:
+       // result: (XORconst [1] (SGT (SignExt8to32 y) (SignExt8to32 x)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v2.AddArg(x)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGeq8U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Geq8U x y)
+       // cond:
+       // result: (XORconst [1] (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(x)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGetClosurePtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (GetClosurePtr)
+       // cond:
+       // result: (LoweredGetClosurePtr)
+       for {
+               v.reset(OpMIPSLoweredGetClosurePtr)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGoCall(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (GoCall [argwid] mem)
+       // cond:
+       // result: (CALLgo [argwid] mem)
+       for {
+               argwid := v.AuxInt
+               mem := v.Args[0]
+               v.reset(OpMIPSCALLgo)
+               v.AuxInt = argwid
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater16 x y)
+       // cond:
+       // result: (SGT (SignExt16to32 x) (SignExt16to32 y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGT)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(y)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater16U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater16U x y)
+       // cond:
+       // result: (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater32 x y)
+       // cond:
+       // result: (SGT x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGT)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater32F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGTF x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGTF, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater32U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater32U x y)
+       // cond:
+       // result: (SGTU x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater64F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGTD x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGTD, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater8 x y)
+       // cond:
+       // result: (SGT (SignExt8to32 x) (SignExt8to32 y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGT)
+               v0 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(y)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpGreater8U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Greater8U x y)
+       // cond:
+       // result: (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpHmul16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Hmul16 x y)
+       // cond:
+       // result: (SRAconst (MUL <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 16
+               v0 := b.NewValue0(v.Line, OpMIPSMUL, config.fe.TypeInt32())
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpHmul16u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Hmul16u x y)
+       // cond:
+       // result: (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = 16
+               v0 := b.NewValue0(v.Line, OpMIPSMUL, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpHmul32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Hmul32 x y)
+       // cond:
+       // result: (Select0 (MULT x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSMULT, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpHmul32u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Hmul32u x y)
+       // cond:
+       // result: (Select0 (MULTU x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSMULTU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpHmul8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Hmul8 x y)
+       // cond:
+       // result: (SRAconst  (MUL <config.fe.TypeInt32()> (SignExt8to32 x) (SignExt8to32 y)) [8])
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 8
+               v0 := b.NewValue0(v.Line, OpMIPSMUL, config.fe.TypeInt32())
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpHmul8u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Hmul8u x y)
+       // cond:
+       // result: (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = 8
+               v0 := b.NewValue0(v.Line, OpMIPSMUL, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpInterCall(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (InterCall [argwid] entry mem)
+       // cond:
+       // result: (CALLinter [argwid] entry mem)
+       for {
+               argwid := v.AuxInt
+               entry := v.Args[0]
+               mem := v.Args[1]
+               v.reset(OpMIPSCALLinter)
+               v.AuxInt = argwid
+               v.AddArg(entry)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpIsInBounds(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (IsInBounds idx len)
+       // cond:
+       // result: (SGTU len idx)
+       for {
+               idx := v.Args[0]
+               len := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v.AddArg(len)
+               v.AddArg(idx)
+               return true
+       }
+}
+func rewriteValueMIPS_OpIsNonNil(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (IsNonNil ptr)
+       // cond:
+       // result: (SGTU ptr (MOVWconst [0]))
+       for {
+               ptr := v.Args[0]
+               v.reset(OpMIPSSGTU)
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpIsSliceInBounds(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (IsSliceInBounds idx len)
+       // cond:
+       // result: (XORconst [1] (SGTU idx len))
+       for {
+               idx := v.Args[0]
+               len := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v0.AddArg(idx)
+               v0.AddArg(len)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq16 x y)
+       // cond:
+       // result: (XORconst [1] (SGT (SignExt16to32 x) (SignExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq16U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq16U x y)
+       // cond:
+       // result: (XORconst [1] (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq32 x y)
+       // cond:
+       // result: (XORconst [1] (SGT x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq32F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGEF y x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGEF, TypeFlags)
+               v0.AddArg(y)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq32U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq32U x y)
+       // cond:
+       // result: (XORconst [1] (SGTU x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq64F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGED y x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGED, TypeFlags)
+               v0.AddArg(y)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq8 x y)
+       // cond:
+       // result: (XORconst [1] (SGT (SignExt8to32 x) (SignExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLeq8U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Leq8U x y)
+       // cond:
+       // result: (XORconst [1] (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less16 x y)
+       // cond:
+       // result: (SGT (SignExt16to32 y) (SignExt16to32 x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGT)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess16U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less16U x y)
+       // cond:
+       // result: (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less32 x y)
+       // cond:
+       // result: (SGT y x)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGT)
+               v.AddArg(y)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less32F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGTF y x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGTF, TypeFlags)
+               v0.AddArg(y)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess32U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less32U x y)
+       // cond:
+       // result: (SGTU y x)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v.AddArg(y)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less64F x y)
+       // cond:
+       // result: (FPFlagTrue (CMPGTD y x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagTrue)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPGTD, TypeFlags)
+               v0.AddArg(y)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less8 x y)
+       // cond:
+       // result: (SGT (SignExt8to32 y) (SignExt8to32 x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGT)
+               v0 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLess8U(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Less8U x y)
+       // cond:
+       // result: (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLoad(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Load <t> ptr mem)
+       // cond: t.IsBoolean()
+       // result: (MOVBUload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(t.IsBoolean()) {
+                       break
+               }
+               v.reset(OpMIPSMOVBUload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: (is8BitInt(t) && isSigned(t))
+       // result: (MOVBload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is8BitInt(t) && isSigned(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVBload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: (is8BitInt(t) && !isSigned(t))
+       // result: (MOVBUload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is8BitInt(t) && !isSigned(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVBUload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: (is16BitInt(t) && isSigned(t))
+       // result: (MOVHload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is16BitInt(t) && isSigned(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVHload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: (is16BitInt(t) && !isSigned(t))
+       // result: (MOVHUload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is16BitInt(t) && !isSigned(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVHUload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: (is32BitInt(t) || isPtr(t))
+       // result: (MOVWload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is32BitInt(t) || isPtr(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: is32BitFloat(t)
+       // result: (MOVFload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is32BitFloat(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVFload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: is64BitFloat(t)
+       // result: (MOVDload ptr mem)
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is64BitFloat(t)) {
+                       break
+               }
+               v.reset(OpMIPSMOVDload)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpLsh16x16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh16x16 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh16x32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh16x32 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v2.AuxInt = 32
+               v2.AddArg(y)
+               v.AddArg(v2)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh16x64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh16x64 x (Const64 [c]))
+       // cond: uint32(c) < 16
+       // result: (SLLconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 16) {
+                       break
+               }
+               v.reset(OpMIPSSLLconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (Lsh16x64 _ (Const64 [c]))
+       // cond: uint32(c) >= 16
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 16) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpLsh16x8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh16x8 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh32x16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh32x16 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh32x32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh32x32 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v2.AuxInt = 32
+               v2.AddArg(y)
+               v.AddArg(v2)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh32x64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh32x64 x (Const64 [c]))
+       // cond: uint32(c) < 32
+       // result: (SLLconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 32) {
+                       break
+               }
+               v.reset(OpMIPSSLLconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (Lsh32x64 _ (Const64 [c]))
+       // cond: uint32(c) >= 32
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 32) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpLsh32x8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh32x8 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh8x16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh8x16 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh8x32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh8x32 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v2.AuxInt = 32
+               v2.AddArg(y)
+               v.AddArg(v2)
+               return true
+       }
+}
+func rewriteValueMIPS_OpLsh8x64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh8x64 x (Const64 [c]))
+       // cond: uint32(c) < 8
+       // result: (SLLconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 8) {
+                       break
+               }
+               v.reset(OpMIPSSLLconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (Lsh8x64 _ (Const64 [c]))
+       // cond: uint32(c) >= 8
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 8) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpLsh8x8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Lsh8x8 <t> x y)
+       // cond:
+       // result: (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSLL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMIPSADD(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ADD (MOVWconst [c]) x)
+       // cond:
+       // result: (ADDconst [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (ADD x (MOVWconst [c]))
+       // cond:
+       // result: (ADDconst [c] x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (ADD x (NEG y))
+       // cond:
+       // result: (SUB x y)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSNEG {
+                       break
+               }
+               y := v_1.Args[0]
+               v.reset(OpMIPSSUB)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+       // match: (ADD (NEG y) x)
+       // cond:
+       // result: (SUB x y)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSNEG {
+                       break
+               }
+               y := v_0.Args[0]
+               x := v.Args[1]
+               v.reset(OpMIPSSUB)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSADDconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ADDconst [off1] (MOVWaddr [off2] {sym} ptr))
+       // cond:
+       // result: (MOVWaddr [off1+off2] {sym} ptr)
+       for {
+               off1 := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym := v_0.Aux
+               ptr := v_0.Args[0]
+               v.reset(OpMIPSMOVWaddr)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               return true
+       }
+       // match: (ADDconst [0]  x)
+       // cond:
+       // result: x
+       for {
+               if v.AuxInt != 0 {
+                       break
+               }
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (ADDconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [int64(int32(c+d))])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(c + d))
+               return true
+       }
+       // match: (ADDconst [c] (ADDconst [d] x))
+       // cond:
+       // result: (ADDconst [int64(int32(c+d))] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSADDconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = int64(int32(c + d))
+               v.AddArg(x)
+               return true
+       }
+       // match: (ADDconst [c] (SUBconst [d] x))
+       // cond:
+       // result: (ADDconst [int64(int32(c-d))] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSSUBconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = int64(int32(c - d))
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSAND(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (AND (MOVWconst [c]) x)
+       // cond:
+       // result: (ANDconst [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (AND x (MOVWconst [c]))
+       // cond:
+       // result: (ANDconst [c] x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (AND x x)
+       // cond:
+       // result: x
+       for {
+               x := v.Args[0]
+               if x != v.Args[1] {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (AND (SGTUconst [1] x) (SGTUconst [1] y))
+       // cond:
+       // result: (SGTUconst [1] (OR <x.Type> x y))
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSSGTUconst {
+                       break
+               }
+               if v_0.AuxInt != 1 {
+                       break
+               }
+               x := v_0.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSSGTUconst {
+                       break
+               }
+               if v_1.AuxInt != 1 {
+                       break
+               }
+               y := v_1.Args[0]
+               v.reset(OpMIPSSGTUconst)
+               v.AuxInt = 1
+               v0 := b.NewValue0(v.Line, OpMIPSOR, x.Type)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSANDconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ANDconst [0]  _)
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               if v.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (ANDconst [-1] x)
+       // cond:
+       // result: x
+       for {
+               if v.AuxInt != -1 {
+                       break
+               }
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (ANDconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [c&d])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = c & d
+               return true
+       }
+       // match: (ANDconst [c] (ANDconst [d] x))
+       // cond:
+       // result: (ANDconst [c&d] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c & d
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSCMOVZ(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (CMOVZ _ b (MOVWconst [0]))
+       // cond:
+       // result: b
+       for {
+               b := v.Args[1]
+               v_2 := v.Args[2]
+               if v_2.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_2.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = b.Type
+               v.AddArg(b)
+               return true
+       }
+       // match: (CMOVZ a _ (MOVWconst [c]))
+       // cond: c!=0
+       // result: a
+       for {
+               a := v.Args[0]
+               v_2 := v.Args[2]
+               if v_2.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_2.AuxInt
+               if !(c != 0) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = a.Type
+               v.AddArg(a)
+               return true
+       }
+       // match: (CMOVZ a (MOVWconst [0]) c)
+       // cond:
+       // result: (CMOVZzero a c)
+       for {
+               a := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               c := v.Args[2]
+               v.reset(OpMIPSCMOVZzero)
+               v.AddArg(a)
+               v.AddArg(c)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSCMOVZzero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (CMOVZzero _ (MOVWconst [0]))
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (CMOVZzero a (MOVWconst [c]))
+       // cond: c!=0
+       // result: a
+       for {
+               a := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(c != 0) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = a.Type
+               v.AddArg(a)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSLoweredAtomicAdd(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (LoweredAtomicAdd ptr (MOVWconst [c]) mem)
+       // cond: is16Bit(c)
+       // result: (LoweredAtomicAddconst [c] ptr mem)
+       for {
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               mem := v.Args[2]
+               if !(is16Bit(c)) {
+                       break
+               }
+               v.reset(OpMIPSLoweredAtomicAddconst)
+               v.AuxInt = c
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSLoweredAtomicStore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (LoweredAtomicStore ptr (MOVWconst [0]) mem)
+       // cond:
+       // result: (LoweredAtomicStorezero ptr mem)
+       for {
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               mem := v.Args[2]
+               v.reset(OpMIPSLoweredAtomicStorezero)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVBUload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVBUload [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVBUload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVBUload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && !isSigned(x.Type)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVBstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && !isSigned(x.Type)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVBUreg(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVBUreg x:(MOVBUload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVBUreg x:(MOVBUreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem))
+       // cond: x.Uses == 1 && clobber(x)
+       // result: @x.Block (MOVBUload <t> [off] {sym} ptr mem)
+       for {
+               t := v.Type
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBload {
+                       break
+               }
+               off := x.AuxInt
+               sym := x.Aux
+               ptr := x.Args[0]
+               mem := x.Args[1]
+               if !(x.Uses == 1 && clobber(x)) {
+                       break
+               }
+               b = x.Block
+               v0 := b.NewValue0(v.Line, OpMIPSMOVBUload, t)
+               v.reset(OpCopy)
+               v.AddArg(v0)
+               v0.AuxInt = off
+               v0.Aux = sym
+               v0.AddArg(ptr)
+               v0.AddArg(mem)
+               return true
+       }
+       // match: (MOVBUreg (ANDconst [c] x))
+       // cond:
+       // result: (ANDconst [c&0xff] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c & 0xff
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVBUreg (MOVWconst [c]))
+       // cond:
+       // result: (MOVWconst [int64(uint8(c))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(uint8(c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVBload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVBload  [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVBload  [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVBload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVBload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && isSigned(x.Type)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVBstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && isSigned(x.Type)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVBreg(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVBreg x:(MOVBload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVBreg x:(MOVBreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem))
+       // cond: x.Uses == 1 && clobber(x)
+       // result: @x.Block (MOVBload <t> [off] {sym} ptr mem)
+       for {
+               t := v.Type
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUload {
+                       break
+               }
+               off := x.AuxInt
+               sym := x.Aux
+               ptr := x.Args[0]
+               mem := x.Args[1]
+               if !(x.Uses == 1 && clobber(x)) {
+                       break
+               }
+               b = x.Block
+               v0 := b.NewValue0(v.Line, OpMIPSMOVBload, t)
+               v.reset(OpCopy)
+               v.AddArg(v0)
+               v0.AuxInt = off
+               v0.Aux = sym
+               v0.AddArg(ptr)
+               v0.AddArg(mem)
+               return true
+       }
+       // match: (MOVBreg (ANDconst [c] x))
+       // cond: c & 0x80 == 0
+       // result: (ANDconst [c&0x7f] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v_0.Args[0]
+               if !(c&0x80 == 0) {
+                       break
+               }
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c & 0x7f
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVBreg  (MOVWconst [c]))
+       // cond:
+       // result: (MOVWconst [int64(int8(c))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int8(c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVBstore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVBstore [off1+off2] {sym} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off] {sym} ptr (MOVWconst [0]) mem)
+       // cond:
+       // result: (MOVBstorezero [off] {sym} ptr mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstorezero)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
+       // cond:
+       // result: (MOVBstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVBreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem)
+       // cond:
+       // result: (MOVBstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
+       // cond:
+       // result: (MOVBstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVHreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem)
+       // cond:
+       // result: (MOVBstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVHUreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem)
+       // cond:
+       // result: (MOVBstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVBstorezero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVBstorezero [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstorezero)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstorezero)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVDload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVDload  [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVDload  [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVDload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVDload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVDstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVDstore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVDstore [off1+off2] {sym} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVDstore)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVDstore)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVFload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVFload  [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVFload  [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVFload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVFload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVFstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVFstore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVFstore [off1+off2] {sym} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVFstore)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVFstore)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVHUload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVHUload [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVHUload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVHUload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && !isSigned(x.Type)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVHstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && !isSigned(x.Type)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVHUreg(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVHUreg x:(MOVBUload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHUreg x:(MOVHUload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVHUload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHUreg x:(MOVBUreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHUreg x:(MOVHUreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVHUreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem))
+       // cond: x.Uses == 1 && clobber(x)
+       // result: @x.Block (MOVHUload <t> [off] {sym} ptr mem)
+       for {
+               t := v.Type
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVHload {
+                       break
+               }
+               off := x.AuxInt
+               sym := x.Aux
+               ptr := x.Args[0]
+               mem := x.Args[1]
+               if !(x.Uses == 1 && clobber(x)) {
+                       break
+               }
+               b = x.Block
+               v0 := b.NewValue0(v.Line, OpMIPSMOVHUload, t)
+               v.reset(OpCopy)
+               v.AddArg(v0)
+               v0.AuxInt = off
+               v0.Aux = sym
+               v0.AddArg(ptr)
+               v0.AddArg(mem)
+               return true
+       }
+       // match: (MOVHUreg (ANDconst [c] x))
+       // cond:
+       // result: (ANDconst [c&0xffff] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c & 0xffff
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHUreg (MOVWconst [c]))
+       // cond:
+       // result: (MOVWconst [int64(uint16(c))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(uint16(c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVHload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVHload  [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVHload  [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVHload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVHload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && isSigned(x.Type)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVHstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) && isSigned(x.Type)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVHreg(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVHreg x:(MOVBload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg x:(MOVBUload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg x:(MOVHload _ _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVHload {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg x:(MOVBreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg x:(MOVBUreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg x:(MOVHreg _))
+       // cond:
+       // result: (MOVWreg x)
+       for {
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVHreg {
+                       break
+               }
+               v.reset(OpMIPSMOVWreg)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem))
+       // cond: x.Uses == 1 && clobber(x)
+       // result: @x.Block (MOVHload <t> [off] {sym} ptr mem)
+       for {
+               t := v.Type
+               x := v.Args[0]
+               if x.Op != OpMIPSMOVHUload {
+                       break
+               }
+               off := x.AuxInt
+               sym := x.Aux
+               ptr := x.Args[0]
+               mem := x.Args[1]
+               if !(x.Uses == 1 && clobber(x)) {
+                       break
+               }
+               b = x.Block
+               v0 := b.NewValue0(v.Line, OpMIPSMOVHload, t)
+               v.reset(OpCopy)
+               v.AddArg(v0)
+               v0.AuxInt = off
+               v0.Aux = sym
+               v0.AddArg(ptr)
+               v0.AddArg(mem)
+               return true
+       }
+       // match: (MOVHreg (ANDconst [c] x))
+       // cond: c & 0x8000 == 0
+       // result: (ANDconst [c&0x7fff] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v_0.Args[0]
+               if !(c&0x8000 == 0) {
+                       break
+               }
+               v.reset(OpMIPSANDconst)
+               v.AuxInt = c & 0x7fff
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVHreg  (MOVWconst [c]))
+       // cond:
+       // result: (MOVWconst [int64(int16(c))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int16(c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVHstore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVHstore [off1+off2] {sym} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHstore [off] {sym} ptr (MOVWconst [0]) mem)
+       // cond:
+       // result: (MOVHstorezero [off] {sym} ptr mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVHstorezero)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem)
+       // cond:
+       // result: (MOVHstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVHreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem)
+       // cond:
+       // result: (MOVHstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVHUreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem)
+       // cond:
+       // result: (MOVHstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVHstorezero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVHstorezero [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstorezero)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstorezero)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVWload(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVWload  [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVWload  [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVWload)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWload)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
+       // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)
+       // result: x
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWstore {
+                       break
+               }
+               off2 := v_1.AuxInt
+               sym2 := v_1.Aux
+               ptr2 := v_1.Args[0]
+               x := v_1.Args[1]
+               if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVWreg(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVWreg x)
+       // cond: x.Uses == 1
+       // result: (MOVWnop x)
+       for {
+               x := v.Args[0]
+               if !(x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVWnop)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MOVWreg  (MOVWconst [c]))
+       // cond:
+       // result: (MOVWconst [c])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = c
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVWstore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVWstore [off1+off2] {sym} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVWstore [off] {sym} ptr (MOVWconst [0]) mem)
+       // cond:
+       // result: (MOVWstorezero [off] {sym} ptr mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVWstorezero)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem)
+       // cond:
+       // result: (MOVWstore [off] {sym} ptr x mem)
+       for {
+               off := v.AuxInt
+               sym := v.Aux
+               ptr := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWreg {
+                       break
+               }
+               x := v_1.Args[0]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = off
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(x)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMOVWstorezero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem)
+       // cond: (is16Bit(off1+off2) || x.Uses == 1)
+       // result: (MOVWstorezero [off1+off2] {sym} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym := v.Aux
+               x := v.Args[0]
+               if x.Op != OpMIPSADDconst {
+                       break
+               }
+               off2 := x.AuxInt
+               ptr := x.Args[0]
+               mem := v.Args[1]
+               if !(is16Bit(off1+off2) || x.Uses == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstorezero)
+               v.AuxInt = off1 + off2
+               v.Aux = sym
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
+       // cond: canMergeSym(sym1,sym2)
+       // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       for {
+               off1 := v.AuxInt
+               sym1 := v.Aux
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWaddr {
+                       break
+               }
+               off2 := v_0.AuxInt
+               sym2 := v_0.Aux
+               ptr := v_0.Args[0]
+               mem := v.Args[1]
+               if !(canMergeSym(sym1, sym2)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstorezero)
+               v.AuxInt = off1 + off2
+               v.Aux = mergeSym(sym1, sym2)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSMUL(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (MUL (MOVWconst [0]) _ )
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (MUL (MOVWconst [1]) x )
+       // cond:
+       // result: x
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0.AuxInt != 1 {
+                       break
+               }
+               x := v.Args[1]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (MUL (MOVWconst [-1]) x )
+       // cond:
+       // result: (NEG x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0.AuxInt != -1 {
+                       break
+               }
+               x := v.Args[1]
+               v.reset(OpMIPSNEG)
+               v.AddArg(x)
+               return true
+       }
+       // match: (MUL (MOVWconst [c]) x )
+       // cond: isPowerOfTwo(int64(uint32(c)))
+       // result: (SLLconst [log2(int64(uint32(c)))] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               if !(isPowerOfTwo(int64(uint32(c)))) {
+                       break
+               }
+               v.reset(OpMIPSSLLconst)
+               v.AuxInt = log2(int64(uint32(c)))
+               v.AddArg(x)
+               return true
+       }
+       // match: (MUL (MOVWconst [c]) (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [int64(int32(c)*int32(d))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(c) * int32(d))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSNEG(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (NEG (MOVWconst [c]))
+       // cond:
+       // result: (MOVWconst [int64(int32(-c))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(-c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSNOR(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (NOR (MOVWconst [c]) x)
+       // cond:
+       // result: (NORconst [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSNORconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (NOR x (MOVWconst [c]))
+       // cond:
+       // result: (NORconst [c] x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSNORconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSNORconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (NORconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [^(c|d)])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = ^(c | d)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSOR(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (OR  (MOVWconst [c]) x)
+       // cond:
+       // result: (ORconst  [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSORconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (OR  x (MOVWconst [c]))
+       // cond:
+       // result: (ORconst  [c] x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSORconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (OR  x x)
+       // cond:
+       // result: x
+       for {
+               x := v.Args[0]
+               if x != v.Args[1] {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (OR (SGTUzero x) (SGTUzero y))
+       // cond:
+       // result: (SGTUzero (OR <x.Type> x y))
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSSGTUzero {
+                       break
+               }
+               x := v_0.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSSGTUzero {
+                       break
+               }
+               y := v_1.Args[0]
+               v.reset(OpMIPSSGTUzero)
+               v0 := b.NewValue0(v.Line, OpMIPSOR, x.Type)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSORconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ORconst  [0]  x)
+       // cond:
+       // result: x
+       for {
+               if v.AuxInt != 0 {
+                       break
+               }
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (ORconst  [-1] _)
+       // cond:
+       // result: (MOVWconst [-1])
+       for {
+               if v.AuxInt != -1 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = -1
+               return true
+       }
+       // match: (ORconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [c|d])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = c | d
+               return true
+       }
+       // match: (ORconst [c] (ORconst [d] x))
+       // cond:
+       // result: (ORconst [c|d] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSORconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSORconst)
+               v.AuxInt = c | d
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSGT(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SGT  (MOVWconst [c]) x)
+       // cond:
+       // result: (SGTconst  [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSSGTconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (SGT x (MOVWconst [0]))
+       // cond:
+       // result: (SGTzero x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSSGTzero)
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSGTU(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SGTU (MOVWconst [c]) x)
+       // cond:
+       // result: (SGTUconst [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSSGTUconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (SGTU x (MOVWconst [0]))
+       // cond:
+       // result: (SGTUzero x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_1.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSSGTUzero)
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSGTUconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SGTUconst [c] (MOVWconst [d]))
+       // cond: uint32(c)>uint32(d)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(uint32(c) > uint32(d)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTUconst [c] (MOVWconst [d]))
+       // cond: uint32(c)<=uint32(d)
+       // result: (MOVWconst [0])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(uint32(c) <= uint32(d)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SGTUconst [c] (MOVBUreg _))
+       // cond: 0xff < uint32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               if !(0xff < uint32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTUconst [c] (MOVHUreg _))
+       // cond: 0xffff < uint32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVHUreg {
+                       break
+               }
+               if !(0xffff < uint32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTUconst [c] (ANDconst [m] _))
+       // cond: uint32(m) < uint32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               m := v_0.AuxInt
+               if !(uint32(m) < uint32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTUconst [c] (SRLconst _ [d]))
+       // cond: uint32(d) <= 31 && 1<<(32-uint32(d)) <= uint32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSSRLconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(uint32(d) <= 31 && 1<<(32-uint32(d)) <= uint32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSGTUzero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SGTUzero (MOVWconst [d]))
+       // cond: uint32(d) != 0
+       // result: (MOVWconst [1])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(uint32(d) != 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTUzero (MOVWconst [d]))
+       // cond: uint32(d) == 0
+       // result: (MOVWconst [0])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(uint32(d) == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSGTconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SGTconst [c] (MOVWconst [d]))
+       // cond: int32(c) > int32(d)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(int32(c) > int32(d)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTconst [c] (MOVWconst [d]))
+       // cond: int32(c) <= int32(d)
+       // result: (MOVWconst [0])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(int32(c) <= int32(d)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SGTconst [c] (MOVBreg _))
+       // cond: 0x7f < int32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVBreg {
+                       break
+               }
+               if !(0x7f < int32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTconst [c] (MOVBreg _))
+       // cond: int32(c) <= -0x80
+       // result: (MOVWconst [0])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVBreg {
+                       break
+               }
+               if !(int32(c) <= -0x80) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SGTconst [c] (MOVBUreg _))
+       // cond: 0xff < int32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               if !(0xff < int32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTconst [c] (MOVBUreg _))
+       // cond: int32(c) < 0
+       // result: (MOVWconst [0])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVBUreg {
+                       break
+               }
+               if !(int32(c) < 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SGTconst [c] (MOVHreg _))
+       // cond: 0x7fff < int32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVHreg {
+                       break
+               }
+               if !(0x7fff < int32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTconst [c] (MOVHreg _))
+       // cond: int32(c) <= -0x8000
+       // result: (MOVWconst [0])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVHreg {
+                       break
+               }
+               if !(int32(c) <= -0x8000) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SGTconst [c] (MOVHUreg _))
+       // cond: 0xffff < int32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVHUreg {
+                       break
+               }
+               if !(0xffff < int32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTconst [c] (MOVHUreg _))
+       // cond: int32(c) < 0
+       // result: (MOVWconst [0])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVHUreg {
+                       break
+               }
+               if !(int32(c) < 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SGTconst [c] (ANDconst [m] _))
+       // cond: 0 <= int32(m) && int32(m) < int32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSANDconst {
+                       break
+               }
+               m := v_0.AuxInt
+               if !(0 <= int32(m) && int32(m) < int32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTconst [c] (SRLconst _ [d]))
+       // cond: 0 <= int32(c) && uint32(d) <= 31 && 1<<(32-uint32(d)) <= int32(c)
+       // result: (MOVWconst [1])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSSRLconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(0 <= int32(c) && uint32(d) <= 31 && 1<<(32-uint32(d)) <= int32(c)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSGTzero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SGTzero (MOVWconst [d]))
+       // cond: int32(d) > 0
+       // result: (MOVWconst [1])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(int32(d) > 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 1
+               return true
+       }
+       // match: (SGTzero (MOVWconst [d]))
+       // cond: int32(d) <= 0
+       // result: (MOVWconst [0])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               if !(int32(d) <= 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSLL(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SLL _ (MOVWconst [c]))
+       // cond: uint32(c)>=32
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 32) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SLL x (MOVWconst [c]))
+       // cond:
+       // result: (SLLconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSSLLconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSLLconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SLLconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [int64(int32(uint32(d)<<uint32(c)))])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(uint32(d) << uint32(c)))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSRA(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SRA x (MOVWconst [c]))
+       // cond: uint32(c)>=32
+       // result: (SRAconst x [31])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 32) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 31
+               v.AddArg(x)
+               return true
+       }
+       // match: (SRA x (MOVWconst [c]))
+       // cond:
+       // result: (SRAconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSRAconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SRAconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [int64(int32(d)>>uint32(c))])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(d) >> uint32(c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSRL(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SRL _ (MOVWconst [c]))
+       // cond: uint32(c)>=32
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 32) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SRL x (MOVWconst [c]))
+       // cond:
+       // result: (SRLconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSRLconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SRLconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [int64(uint32(d)>>uint32(c))])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(uint32(d) >> uint32(c))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSUB(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SUB x (MOVWconst [c]))
+       // cond:
+       // result: (SUBconst [c] x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSSUBconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (SUB x x)
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               x := v.Args[0]
+               if x != v.Args[1] {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (SUB (MOVWconst [0]) x)
+       // cond:
+       // result: (NEG x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0.AuxInt != 0 {
+                       break
+               }
+               x := v.Args[1]
+               v.reset(OpMIPSNEG)
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSSUBconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SUBconst [0]  x)
+       // cond:
+       // result: x
+       for {
+               if v.AuxInt != 0 {
+                       break
+               }
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (SUBconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [int64(int32(d-c))])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(d - c))
+               return true
+       }
+       // match: (SUBconst [c] (SUBconst [d] x))
+       // cond:
+       // result: (ADDconst [int64(int32(-c-d))] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSSUBconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = int64(int32(-c - d))
+               v.AddArg(x)
+               return true
+       }
+       // match: (SUBconst [c] (ADDconst [d] x))
+       // cond:
+       // result: (ADDconst [int64(int32(-c+d))] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSADDconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = int64(int32(-c + d))
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSXOR(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (XOR (MOVWconst [c]) x)
+       // cond:
+       // result: (XORconst [c] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0.AuxInt
+               x := v.Args[1]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (XOR x (MOVWconst [c]))
+       // cond:
+       // result: (XORconst [c] x)
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_1.AuxInt
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (XOR x x)
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               x := v.Args[0]
+               if x != v.Args[1] {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMIPSXORconst(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (XORconst [0]  x)
+       // cond:
+       // result: x
+       for {
+               if v.AuxInt != 0 {
+                       break
+               }
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (XORconst [-1] x)
+       // cond:
+       // result: (NORconst [0] x)
+       for {
+               if v.AuxInt != -1 {
+                       break
+               }
+               x := v.Args[0]
+               v.reset(OpMIPSNORconst)
+               v.AuxInt = 0
+               v.AddArg(x)
+               return true
+       }
+       // match: (XORconst [c] (MOVWconst [d]))
+       // cond:
+       // result: (MOVWconst [c^d])
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = c ^ d
+               return true
+       }
+       // match: (XORconst [c] (XORconst [d] x))
+       // cond:
+       // result: (XORconst [c^d] x)
+       for {
+               c := v.AuxInt
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSXORconst {
+                       break
+               }
+               d := v_0.AuxInt
+               x := v_0.Args[0]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = c ^ d
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMod16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mod16 x y)
+       // cond:
+       // result: (Select0 (DIV (SignExt16to32 x) (SignExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSDIV, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMod16u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mod16u x y)
+       // cond:
+       // result: (Select0 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSDIVU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMod32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mod32 x y)
+       // cond:
+       // result: (Select0 (DIV x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSDIV, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMod32u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mod32u x y)
+       // cond:
+       // result: (Select0 (DIVU x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSDIVU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMod8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mod8 x y)
+       // cond:
+       // result: (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSDIV, MakeTuple(config.fe.TypeInt32(), config.fe.TypeInt32()))
+               v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMod8u(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mod8u x y)
+       // cond:
+       // result: (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSDIVU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMove(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Move [s] _ _ mem)
+       // cond: SizeAndAlign(s).Size() == 0
+       // result: mem
+       for {
+               s := v.AuxInt
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 0) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = mem.Type
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 1
+       // result: (MOVBstore dst (MOVBUload src mem) mem)
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore dst (MOVHUload src mem) mem)
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVHUload, config.fe.TypeUInt16())
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 2
+       // result: (MOVBstore [1] dst (MOVBUload [1] src mem)           (MOVBstore dst (MOVBUload src mem) mem))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 2) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = 1
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v0.AuxInt = 1
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore dst (MOVWload src mem) mem)
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore [2] dst (MOVHUload [2] src mem)           (MOVHstore dst (MOVHUload src mem) mem))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = 2
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVHUload, config.fe.TypeUInt16())
+               v0.AuxInt = 2
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVHUload, config.fe.TypeUInt16())
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 4
+       // result: (MOVBstore [3] dst (MOVBUload [3] src mem)           (MOVBstore [2] dst (MOVBUload [2] src mem)                      (MOVBstore [1] dst (MOVBUload [1] src mem)                              (MOVBstore dst (MOVBUload src mem) mem))))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 4) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = 3
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v0.AuxInt = 3
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v1.AuxInt = 2
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v2.AuxInt = 2
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v3.AuxInt = 1
+               v3.AddArg(dst)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v4.AuxInt = 1
+               v4.AddArg(src)
+               v4.AddArg(mem)
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v5.AddArg(dst)
+               v6 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v6.AddArg(src)
+               v6.AddArg(mem)
+               v5.AddArg(v6)
+               v5.AddArg(mem)
+               v3.AddArg(v5)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 3
+       // result: (MOVBstore [2] dst (MOVBUload [2] src mem)           (MOVBstore [1] dst (MOVBUload [1] src mem)                      (MOVBstore dst (MOVBUload src mem) mem)))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 3) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = 2
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v0.AuxInt = 2
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v1.AuxInt = 1
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v2.AuxInt = 1
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v3.AddArg(dst)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVBUload, config.fe.TypeUInt8())
+               v4.AddArg(src)
+               v4.AddArg(mem)
+               v3.AddArg(v4)
+               v3.AddArg(mem)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore [4] dst (MOVWload [4] src mem)            (MOVWstore dst (MOVWload src mem) mem))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = 4
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v0.AuxInt = 4
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore [6] dst (MOVHload [6] src mem)            (MOVHstore [4] dst (MOVHload [4] src mem)                       (MOVHstore [2] dst (MOVHload [2] src mem)                               (MOVHstore dst (MOVHload src mem) mem))))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = 6
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v0.AuxInt = 6
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v1.AuxInt = 4
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v2.AuxInt = 4
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v3.AuxInt = 2
+               v3.AddArg(dst)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v4.AuxInt = 2
+               v4.AddArg(src)
+               v4.AddArg(mem)
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v5.AddArg(dst)
+               v6 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v6.AddArg(src)
+               v6.AddArg(mem)
+               v5.AddArg(v6)
+               v5.AddArg(mem)
+               v3.AddArg(v5)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore [4] dst (MOVHload [4] src mem)            (MOVHstore [2] dst (MOVHload [2] src mem)                       (MOVHstore dst (MOVHload src mem) mem)))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = 4
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v0.AuxInt = 4
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v1.AuxInt = 2
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v2.AuxInt = 2
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v3.AddArg(dst)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVHload, config.fe.TypeInt16())
+               v4.AddArg(src)
+               v4.AddArg(mem)
+               v3.AddArg(v4)
+               v3.AddArg(mem)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore [8] dst (MOVWload [8] src mem)            (MOVWstore [4] dst (MOVWload [4] src mem)                       (MOVWstore dst (MOVWload src mem) mem)))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = 8
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v0.AuxInt = 8
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v1.AuxInt = 4
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v2.AuxInt = 4
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v3.AddArg(dst)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v4.AddArg(src)
+               v4.AddArg(mem)
+               v3.AddArg(v4)
+               v3.AddArg(mem)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore [12] dst (MOVWload [12] src mem)          (MOVWstore [8] dst (MOVWload [8] src mem)                       (MOVWstore [4] dst (MOVWload [4] src mem)                               (MOVWstore dst (MOVWload src mem) mem))))
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = 12
+               v.AddArg(dst)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v0.AuxInt = 12
+               v0.AddArg(src)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v1.AuxInt = 8
+               v1.AddArg(dst)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v2.AuxInt = 8
+               v2.AddArg(src)
+               v2.AddArg(mem)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v3.AuxInt = 4
+               v3.AddArg(dst)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v4.AuxInt = 4
+               v4.AddArg(src)
+               v4.AddArg(mem)
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v5.AddArg(dst)
+               v6 := b.NewValue0(v.Line, OpMIPSMOVWload, config.fe.TypeUInt32())
+               v6.AddArg(src)
+               v6.AddArg(mem)
+               v5.AddArg(v6)
+               v5.AddArg(mem)
+               v3.AddArg(v5)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Move [s] dst src mem)
+       // cond: (SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0)
+       // result: (LoweredMove [SizeAndAlign(s).Align()]               dst             src             (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])            mem)
+       for {
+               s := v.AuxInt
+               dst := v.Args[0]
+               src := v.Args[1]
+               mem := v.Args[2]
+               if !(SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) {
+                       break
+               }
+               v.reset(OpMIPSLoweredMove)
+               v.AuxInt = SizeAndAlign(s).Align()
+               v.AddArg(dst)
+               v.AddArg(src)
+               v0 := b.NewValue0(v.Line, OpMIPSADDconst, src.Type)
+               v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+               v0.AddArg(src)
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpMul16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mul16 x y)
+       // cond:
+       // result: (MUL x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSMUL)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMul32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mul32 x y)
+       // cond:
+       // result: (MUL x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSMUL)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMul32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mul32F x y)
+       // cond:
+       // result: (MULF x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSMULF)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMul32uhilo(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mul32uhilo x y)
+       // cond:
+       // result: (MULTU x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSMULTU)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMul64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mul64F x y)
+       // cond:
+       // result: (MULD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSMULD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpMul8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Mul8 x y)
+       // cond:
+       // result: (MUL x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSMUL)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeg16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neg16 x)
+       // cond:
+       // result: (NEG x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEG)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeg32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neg32 x)
+       // cond:
+       // result: (NEG x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEG)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeg32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neg32F x)
+       // cond:
+       // result: (NEGF x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEGF)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeg64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neg64F x)
+       // cond:
+       // result: (NEGD x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEGD)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeg8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neg8 x)
+       // cond:
+       // result: (NEG x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEG)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeq16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neq16 x y)
+       // cond:
+       // result: (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)) (MOVWconst [0]))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = 0
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeq32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neq32 x y)
+       // cond:
+       // result: (SGTU (XOR x y) (MOVWconst [0]))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeq32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neq32F x y)
+       // cond:
+       // result: (FPFlagFalse (CMPEQF x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagFalse)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPEQF, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeq64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neq64F x y)
+       // cond:
+       // result: (FPFlagFalse (CMPEQD x y))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSFPFlagFalse)
+               v0 := b.NewValue0(v.Line, OpMIPSCMPEQD, TypeFlags)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeq8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Neq8 x y)
+       // cond:
+       // result: (SGTU (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)) (MOVWconst [0]))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = 0
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeqB(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (NeqB x y)
+       // cond:
+       // result: (XOR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNeqPtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (NeqPtr x y)
+       // cond:
+       // result: (SGTU (XOR x y) (MOVWconst [0]))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSGTU)
+               v0 := b.NewValue0(v.Line, OpMIPSXOR, config.fe.TypeUInt32())
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNilCheck(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (NilCheck ptr mem)
+       // cond:
+       // result: (LoweredNilCheck ptr mem)
+       for {
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               v.reset(OpMIPSLoweredNilCheck)
+               v.AddArg(ptr)
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpNot(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Not x)
+       // cond:
+       // result: (XORconst [1] x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSXORconst)
+               v.AuxInt = 1
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpOffPtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (OffPtr [off] ptr:(SP))
+       // cond:
+       // result: (MOVWaddr [off] ptr)
+       for {
+               off := v.AuxInt
+               ptr := v.Args[0]
+               if ptr.Op != OpSP {
+                       break
+               }
+               v.reset(OpMIPSMOVWaddr)
+               v.AuxInt = off
+               v.AddArg(ptr)
+               return true
+       }
+       // match: (OffPtr [off] ptr)
+       // cond:
+       // result: (ADDconst [off] ptr)
+       for {
+               off := v.AuxInt
+               ptr := v.Args[0]
+               v.reset(OpMIPSADDconst)
+               v.AuxInt = off
+               v.AddArg(ptr)
+               return true
+       }
+}
+func rewriteValueMIPS_OpOr16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Or16 x y)
+       // cond:
+       // result: (OR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpOr32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Or32 x y)
+       // cond:
+       // result: (OR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpOr8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Or8 x y)
+       // cond:
+       // result: (OR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpOrB(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (OrB x y)
+       // cond:
+       // result: (OR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh16Ux16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16Ux16 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = 0
+               v.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v.AddArg(v4)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh16Ux32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16Ux32 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v3.AddArg(y)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh16Ux64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16Ux64 x (Const64 [c]))
+       // cond: uint32(c) < 16
+       // result: (SRLconst (SLLconst <config.fe.TypeUInt32()> x [16]) [c+16])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 16) {
+                       break
+               }
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = c + 16
+               v0 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v0.AuxInt = 16
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Rsh16Ux64 _ (Const64 [c]))
+       // cond: uint32(c) >= 16
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 16) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpRsh16Ux8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16Ux8 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = 0
+               v.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v.AddArg(v4)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh16x16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16x16 x y)
+       // cond:
+       // result: (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt16to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt16to32 y))))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = -1
+               v1.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v1.AddArg(v4)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh16x32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16x32 x y)
+       // cond:
+       // result: (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> y (MOVWconst [-1]) (SGTUconst [32] y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = -1
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v3.AddArg(y)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh16x64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16x64 x (Const64 [c]))
+       // cond: uint32(c) < 16
+       // result: (SRAconst (SLLconst <config.fe.TypeUInt32()> x [16]) [c+16])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 16) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = c + 16
+               v0 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v0.AuxInt = 16
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Rsh16x64 x (Const64 [c]))
+       // cond: uint32(c) >= 16
+       // result: (SRAconst (SLLconst <config.fe.TypeUInt32()> x [16]) [31])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 16) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 31
+               v0 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v0.AuxInt = 16
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpRsh16x8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh16x8 x y)
+       // cond:
+       // result: (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt8to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt8to32 y))))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = -1
+               v1.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v1.AddArg(v4)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh32Ux16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32Ux16 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh32Ux32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32Ux32 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v2.AuxInt = 32
+               v2.AddArg(y)
+               v.AddArg(v2)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh32Ux64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32Ux64 x (Const64 [c]))
+       // cond: uint32(c) < 32
+       // result: (SRLconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 32) {
+                       break
+               }
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (Rsh32Ux64 _ (Const64 [c]))
+       // cond: uint32(c) >= 32
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 32) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpRsh32Ux8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32Ux8 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh32x16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32x16 x y)
+       // cond:
+       // result: (SRA x ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt16to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt16to32 y))))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v.AddArg(x)
+               v0 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = -1
+               v0.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v0.AddArg(v3)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh32x32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32x32 x y)
+       // cond:
+       // result: (SRA x ( CMOVZ <config.fe.TypeUInt32()> y (MOVWconst [-1]) (SGTUconst [32] y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v.AddArg(x)
+               v0 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v0.AddArg(y)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = -1
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v2.AuxInt = 32
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh32x64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32x64 x (Const64 [c]))
+       // cond: uint32(c) < 32
+       // result: (SRAconst x [c])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 32) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = c
+               v.AddArg(x)
+               return true
+       }
+       // match: (Rsh32x64 x (Const64 [c]))
+       // cond: uint32(c) >= 32
+       // result: (SRAconst x [31])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 32) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 31
+               v.AddArg(x)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpRsh32x8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh32x8 x y)
+       // cond:
+       // result: (SRA x ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt8to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt8to32 y))))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v.AddArg(x)
+               v0 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = -1
+               v0.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v4 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v4.AddArg(y)
+               v3.AddArg(v4)
+               v0.AddArg(v3)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh8Ux16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8Ux16 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = 0
+               v.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v.AddArg(v4)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh8Ux32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8Ux32 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> (ZeroExt8to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v3.AddArg(y)
+               v.AddArg(v3)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh8Ux64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8Ux64 x (Const64 [c]))
+       // cond: uint32(c) < 8
+       // result: (SRLconst (SLLconst <config.fe.TypeUInt32()> x [24]) [c+24])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 8) {
+                       break
+               }
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = c + 24
+               v0 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v0.AuxInt = 24
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Rsh8Ux64 _ (Const64 [c]))
+       // cond: uint32(c) >= 8
+       // result: (MOVWconst [0])
+       for {
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 8) {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpRsh8Ux8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8Ux8 <t> x y)
+       // cond:
+       // result: (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSSRL, t)
+               v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v1.AddArg(x)
+               v0.AddArg(v1)
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v0.AddArg(v2)
+               v.AddArg(v0)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = 0
+               v.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v.AddArg(v4)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh8x16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8x16 x y)
+       // cond:
+       // result: (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt16to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt16to32 y))))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = -1
+               v1.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v1.AddArg(v4)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh8x32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8x32 x y)
+       // cond:
+       // result: (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> y (MOVWconst [-1]) (SGTUconst [32] y)))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v1.AddArg(y)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = -1
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v3.AuxInt = 32
+               v3.AddArg(y)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpRsh8x64(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8x64 x (Const64 [c]))
+       // cond: uint32(c) < 8
+       // result: (SRAconst (SLLconst <config.fe.TypeUInt32()> x [24]) [c+24])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) < 8) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = c + 24
+               v0 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v0.AuxInt = 24
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Rsh8x64 x (Const64 [c]))
+       // cond: uint32(c) >= 8
+       // result: (SRAconst (SLLconst <config.fe.TypeUInt32()> x [24]) [31])
+       for {
+               x := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpConst64 {
+                       break
+               }
+               c := v_1.AuxInt
+               if !(uint32(c) >= 8) {
+                       break
+               }
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 31
+               v0 := b.NewValue0(v.Line, OpMIPSSLLconst, config.fe.TypeUInt32())
+               v0.AuxInt = 24
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpRsh8x8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Rsh8x8 x y)
+       // cond:
+       // result: (SRA (SignExt16to32 x) ( CMOVZ <config.fe.TypeUInt32()> (ZeroExt8to32 y) (MOVWconst [-1]) (SGTUconst [32] (ZeroExt8to32 y))))
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSRA)
+               v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSCMOVZ, config.fe.TypeUInt32())
+               v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v2.AddArg(y)
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v3.AuxInt = -1
+               v1.AddArg(v3)
+               v4 := b.NewValue0(v.Line, OpMIPSSGTUconst, config.fe.TypeBool())
+               v4.AuxInt = 32
+               v5 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
+               v5.AddArg(y)
+               v4.AddArg(v5)
+               v1.AddArg(v4)
+               v.AddArg(v1)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSelect0(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Select0 (Add32carry <t> x y))
+       // cond:
+       // result: (ADD <t.FieldType(0)> x y)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpAdd32carry {
+                       break
+               }
+               t := v_0.Type
+               x := v_0.Args[0]
+               y := v_0.Args[1]
+               v.reset(OpMIPSADD)
+               v.Type = t.FieldType(0)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+       // match: (Select0 (Sub32carry <t> x y))
+       // cond:
+       // result: (SUB <t.FieldType(0)> x y)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpSub32carry {
+                       break
+               }
+               t := v_0.Type
+               x := v_0.Args[0]
+               y := v_0.Args[1]
+               v.reset(OpMIPSSUB)
+               v.Type = t.FieldType(0)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+       // match: (Select0 (MULTU x (MOVWconst [c])))
+       // cond: x.Op != OpMIPSMOVWconst
+       // result: (Select0 (MULTU (MOVWconst [c]) x ))
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               x := v_0.Args[0]
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_1.AuxInt
+               if !(x.Op != OpMIPSMOVWconst) {
+                       break
+               }
+               v.reset(OpSelect0)
+               v0 := b.NewValue0(v.Line, OpMIPSMULTU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = c
+               v0.AddArg(v1)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Select0 (MULTU (MOVWconst [0]) _ ))
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0_0.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (Select0 (MULTU (MOVWconst [1]) _ ))
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0_0.AuxInt != 1 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (Select0 (MULTU (MOVWconst [-1]) x ))
+       // cond:
+       // result: (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0_0.AuxInt != -1 {
+                       break
+               }
+               x := v_0.Args[1]
+               v.reset(OpMIPSCMOVZ)
+               v0 := b.NewValue0(v.Line, OpMIPSADDconst, x.Type)
+               v0.AuxInt = -1
+               v0.AddArg(x)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v.AddArg(v1)
+               v.AddArg(x)
+               return true
+       }
+       // match: (Select0 (MULTU (MOVWconst [c]) x ))
+       // cond: isPowerOfTwo(int64(uint32(c)))
+       // result: (SRLconst [32-log2(int64(uint32(c)))] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               x := v_0.Args[1]
+               if !(isPowerOfTwo(int64(uint32(c)))) {
+                       break
+               }
+               v.reset(OpMIPSSRLconst)
+               v.AuxInt = 32 - log2(int64(uint32(c)))
+               v.AddArg(x)
+               return true
+       }
+       // match: (Select0 (MULTU  (MOVWconst [c]) (MOVWconst [d])))
+       // cond:
+       // result: (MOVWconst [(c*d)>>32])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = (c * d) >> 32
+               return true
+       }
+       // match: (Select0 (DIV  (MOVWconst [c]) (MOVWconst [d])))
+       // cond:
+       // result: (MOVWconst [int64(int32(c)%int32(d))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSDIV {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(c) % int32(d))
+               return true
+       }
+       // match: (Select0 (DIVU (MOVWconst [c]) (MOVWconst [d])))
+       // cond:
+       // result: (MOVWconst [int64(int32(uint32(c)%uint32(d)))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSDIVU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(uint32(c) % uint32(d)))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpSelect1(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Select1 (Add32carry <t> x y))
+       // cond:
+       // result: (SGTU <config.fe.TypeBool()> x (ADD <t.FieldType(0)> x y))
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpAdd32carry {
+                       break
+               }
+               t := v_0.Type
+               x := v_0.Args[0]
+               y := v_0.Args[1]
+               v.reset(OpMIPSSGTU)
+               v.Type = config.fe.TypeBool()
+               v.AddArg(x)
+               v0 := b.NewValue0(v.Line, OpMIPSADD, t.FieldType(0))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Select1 (Sub32carry <t> x y))
+       // cond:
+       // result: (SGTU <config.fe.TypeBool()> (SUB <t.FieldType(0)> x y) x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpSub32carry {
+                       break
+               }
+               t := v_0.Type
+               x := v_0.Args[0]
+               y := v_0.Args[1]
+               v.reset(OpMIPSSGTU)
+               v.Type = config.fe.TypeBool()
+               v0 := b.NewValue0(v.Line, OpMIPSSUB, t.FieldType(0))
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v.AddArg(x)
+               return true
+       }
+       // match: (Select1 (MULTU x (MOVWconst [c])))
+       // cond: x.Op != OpMIPSMOVWconst
+       // result: (Select1 (MULTU (MOVWconst [c]) x ))
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               x := v_0.Args[0]
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_1.AuxInt
+               if !(x.Op != OpMIPSMOVWconst) {
+                       break
+               }
+               v.reset(OpSelect1)
+               v0 := b.NewValue0(v.Line, OpMIPSMULTU, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = c
+               v0.AddArg(v1)
+               v0.AddArg(x)
+               v.AddArg(v0)
+               return true
+       }
+       // match: (Select1 (MULTU (MOVWconst [0]) _ ))
+       // cond:
+       // result: (MOVWconst [0])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0_0.AuxInt != 0 {
+                       break
+               }
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = 0
+               return true
+       }
+       // match: (Select1 (MULTU (MOVWconst [1]) x ))
+       // cond:
+       // result: x
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0_0.AuxInt != 1 {
+                       break
+               }
+               x := v_0.Args[1]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (Select1 (MULTU (MOVWconst [-1]) x ))
+       // cond:
+       // result: (NEG <x.Type> x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               if v_0_0.AuxInt != -1 {
+                       break
+               }
+               x := v_0.Args[1]
+               v.reset(OpMIPSNEG)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+       // match: (Select1 (MULTU (MOVWconst [c]) x ))
+       // cond: isPowerOfTwo(int64(uint32(c)))
+       // result: (SLLconst [log2(int64(uint32(c)))] x)
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               x := v_0.Args[1]
+               if !(isPowerOfTwo(int64(uint32(c)))) {
+                       break
+               }
+               v.reset(OpMIPSSLLconst)
+               v.AuxInt = log2(int64(uint32(c)))
+               v.AddArg(x)
+               return true
+       }
+       // match: (Select1 (MULTU  (MOVWconst [c]) (MOVWconst [d])))
+       // cond:
+       // result: (MOVWconst [int64(int32(uint32(c)*uint32(d)))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSMULTU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(uint32(c) * uint32(d)))
+               return true
+       }
+       // match: (Select1 (DIV  (MOVWconst [c]) (MOVWconst [d])))
+       // cond:
+       // result: (MOVWconst [int64(int32(c)/int32(d))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSDIV {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(c) / int32(d))
+               return true
+       }
+       // match: (Select1 (DIVU (MOVWconst [c]) (MOVWconst [d])))
+       // cond:
+       // result: (MOVWconst [int64(int32(uint32(c)/uint32(d)))])
+       for {
+               v_0 := v.Args[0]
+               if v_0.Op != OpMIPSDIVU {
+                       break
+               }
+               v_0_0 := v_0.Args[0]
+               if v_0_0.Op != OpMIPSMOVWconst {
+                       break
+               }
+               c := v_0_0.AuxInt
+               v_0_1 := v_0.Args[1]
+               if v_0_1.Op != OpMIPSMOVWconst {
+                       break
+               }
+               d := v_0_1.AuxInt
+               v.reset(OpMIPSMOVWconst)
+               v.AuxInt = int64(int32(uint32(c) / uint32(d)))
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpSignExt16to32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SignExt16to32 x)
+       // cond:
+       // result: (MOVHreg x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVHreg)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSignExt8to16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SignExt8to16 x)
+       // cond:
+       // result: (MOVBreg x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVBreg)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSignExt8to32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SignExt8to32 x)
+       // cond:
+       // result: (MOVBreg x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVBreg)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSignmask(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Signmask x)
+       // cond:
+       // result: (SRAconst x [31])
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 31
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSlicemask(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Slicemask x)
+       // cond:
+       // result: (NEG (SGT x (MOVWconst [0])))
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEG)
+               v0 := b.NewValue0(v.Line, OpMIPSSGT, config.fe.TypeBool())
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSqrt(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sqrt x)
+       // cond:
+       // result: (SQRTD x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSSQRTD)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpStaticCall(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (StaticCall [argwid] {target} mem)
+       // cond:
+       // result: (CALLstatic [argwid] {target} mem)
+       for {
+               argwid := v.AuxInt
+               target := v.Aux
+               mem := v.Args[0]
+               v.reset(OpMIPSCALLstatic)
+               v.AuxInt = argwid
+               v.Aux = target
+               v.AddArg(mem)
+               return true
+       }
+}
+func rewriteValueMIPS_OpStore(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Store [1] ptr val mem)
+       // cond:
+       // result: (MOVBstore ptr val mem)
+       for {
+               if v.AuxInt != 1 {
+                       break
+               }
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVBstore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Store [2] ptr val mem)
+       // cond:
+       // result: (MOVHstore ptr val mem)
+       for {
+               if v.AuxInt != 2 {
+                       break
+               }
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               v.reset(OpMIPSMOVHstore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Store [4] ptr val mem)
+       // cond: !is32BitFloat(val.Type)
+       // result: (MOVWstore ptr val mem)
+       for {
+               if v.AuxInt != 4 {
+                       break
+               }
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(!is32BitFloat(val.Type)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Store [8] ptr val mem)
+       // cond: !is64BitFloat(val.Type)
+       // result: (MOVWstore ptr val mem)
+       for {
+               if v.AuxInt != 8 {
+                       break
+               }
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(!is64BitFloat(val.Type)) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Store [4] ptr val mem)
+       // cond: is32BitFloat(val.Type)
+       // result: (MOVFstore ptr val mem)
+       for {
+               if v.AuxInt != 4 {
+                       break
+               }
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is32BitFloat(val.Type)) {
+                       break
+               }
+               v.reset(OpMIPSMOVFstore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Store [8] ptr val mem)
+       // cond: is64BitFloat(val.Type)
+       // result: (MOVDstore ptr val mem)
+       for {
+               if v.AuxInt != 8 {
+                       break
+               }
+               ptr := v.Args[0]
+               val := v.Args[1]
+               mem := v.Args[2]
+               if !(is64BitFloat(val.Type)) {
+                       break
+               }
+               v.reset(OpMIPSMOVDstore)
+               v.AddArg(ptr)
+               v.AddArg(val)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpSub16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sub16 x y)
+       // cond:
+       // result: (SUB x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSUB)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSub32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sub32 x y)
+       // cond:
+       // result: (SUB x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSUB)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSub32F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sub32F x y)
+       // cond:
+       // result: (SUBF x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSUBF)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSub32withcarry(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sub32withcarry <t> x y c)
+       // cond:
+       // result: (SUB (SUB <t> x y) c)
+       for {
+               t := v.Type
+               x := v.Args[0]
+               y := v.Args[1]
+               c := v.Args[2]
+               v.reset(OpMIPSSUB)
+               v0 := b.NewValue0(v.Line, OpMIPSSUB, t)
+               v0.AddArg(x)
+               v0.AddArg(y)
+               v.AddArg(v0)
+               v.AddArg(c)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSub64F(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sub64F x y)
+       // cond:
+       // result: (SUBD x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSUBD)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSub8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Sub8 x y)
+       // cond:
+       // result: (SUB x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSUB)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpSubPtr(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (SubPtr x y)
+       // cond:
+       // result: (SUB x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSSUB)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpTrunc16to8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Trunc16to8 x)
+       // cond:
+       // result: x
+       for {
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpTrunc32to16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Trunc32to16 x)
+       // cond:
+       // result: x
+       for {
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpTrunc32to8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Trunc32to8 x)
+       // cond:
+       // result: x
+       for {
+               x := v.Args[0]
+               v.reset(OpCopy)
+               v.Type = x.Type
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpXor16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Xor16 x y)
+       // cond:
+       // result: (XOR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpXor32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Xor32 x y)
+       // cond:
+       // result: (XOR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpXor8(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Xor8 x y)
+       // cond:
+       // result: (XOR x y)
+       for {
+               x := v.Args[0]
+               y := v.Args[1]
+               v.reset(OpMIPSXOR)
+               v.AddArg(x)
+               v.AddArg(y)
+               return true
+       }
+}
+func rewriteValueMIPS_OpZero(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Zero [s] _ mem)
+       // cond: SizeAndAlign(s).Size() == 0
+       // result: mem
+       for {
+               s := v.AuxInt
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 0) {
+                       break
+               }
+               v.reset(OpCopy)
+               v.Type = mem.Type
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 1
+       // result: (MOVBstore ptr (MOVWconst [0]) mem)
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 1) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore ptr (MOVWconst [0]) mem)
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 2
+       // result: (MOVBstore [1] ptr (MOVWconst [0])           (MOVBstore [0] ptr (MOVWconst [0]) mem))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 2) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = 1
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v1.AuxInt = 0
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore ptr (MOVWconst [0]) mem)
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore [2] ptr (MOVWconst [0])           (MOVHstore [0] ptr (MOVWconst [0]) mem))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = 2
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v1.AuxInt = 0
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 4
+       // result: (MOVBstore [3] ptr (MOVWconst [0])           (MOVBstore [2] ptr (MOVWconst [0])                      (MOVBstore [1] ptr (MOVWconst [0])                              (MOVBstore [0] ptr (MOVWconst [0]) mem))))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 4) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = 3
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v1.AuxInt = 2
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v3.AuxInt = 1
+               v3.AddArg(ptr)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v4.AuxInt = 0
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v5.AuxInt = 0
+               v5.AddArg(ptr)
+               v6 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v6.AuxInt = 0
+               v5.AddArg(v6)
+               v5.AddArg(mem)
+               v3.AddArg(v5)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 3
+       // result: (MOVBstore [2] ptr (MOVWconst [0])           (MOVBstore [1] ptr (MOVWconst [0])                      (MOVBstore [0] ptr (MOVWconst [0]) mem)))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 3) {
+                       break
+               }
+               v.reset(OpMIPSMOVBstore)
+               v.AuxInt = 2
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v1.AuxInt = 1
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVBstore, TypeMem)
+               v3.AuxInt = 0
+               v3.AddArg(ptr)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v4.AuxInt = 0
+               v3.AddArg(v4)
+               v3.AddArg(mem)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0
+       // result: (MOVHstore [4] ptr (MOVWconst [0])           (MOVHstore [2] ptr (MOVWconst [0])                      (MOVHstore [0] ptr (MOVWconst [0]) mem)))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVHstore)
+               v.AuxInt = 4
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v1.AuxInt = 2
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVHstore, TypeMem)
+               v3.AuxInt = 0
+               v3.AddArg(ptr)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v4.AuxInt = 0
+               v3.AddArg(v4)
+               v3.AddArg(mem)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore [4] ptr (MOVWconst [0])                   (MOVWstore [0] ptr (MOVWconst [0]) mem))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = 4
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v1.AuxInt = 0
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore [8] ptr (MOVWconst [0])           (MOVWstore [4] ptr (MOVWconst [0])                      (MOVWstore [0] ptr (MOVWconst [0]) mem)))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = 8
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v1.AuxInt = 4
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v3.AuxInt = 0
+               v3.AddArg(ptr)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v4.AuxInt = 0
+               v3.AddArg(v4)
+               v3.AddArg(mem)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0
+       // result: (MOVWstore [12] ptr (MOVWconst [0])          (MOVWstore [8] ptr (MOVWconst [0])                      (MOVWstore [4] ptr (MOVWconst [0])                              (MOVWstore [0] ptr (MOVWconst [0]) mem))))
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0) {
+                       break
+               }
+               v.reset(OpMIPSMOVWstore)
+               v.AuxInt = 12
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v0.AuxInt = 0
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v1.AuxInt = 8
+               v1.AddArg(ptr)
+               v2 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v2.AuxInt = 0
+               v1.AddArg(v2)
+               v3 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v3.AuxInt = 4
+               v3.AddArg(ptr)
+               v4 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v4.AuxInt = 0
+               v3.AddArg(v4)
+               v5 := b.NewValue0(v.Line, OpMIPSMOVWstore, TypeMem)
+               v5.AuxInt = 0
+               v5.AddArg(ptr)
+               v6 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v6.AuxInt = 0
+               v5.AddArg(v6)
+               v5.AddArg(mem)
+               v3.AddArg(v5)
+               v1.AddArg(v3)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Zero [s] ptr mem)
+       // cond: (SizeAndAlign(s).Size() > 16  || SizeAndAlign(s).Align()%4 != 0)
+       // result: (LoweredZero [SizeAndAlign(s).Align()]               ptr             (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])            mem)
+       for {
+               s := v.AuxInt
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) {
+                       break
+               }
+               v.reset(OpMIPSLoweredZero)
+               v.AuxInt = SizeAndAlign(s).Align()
+               v.AddArg(ptr)
+               v0 := b.NewValue0(v.Line, OpMIPSADDconst, ptr.Type)
+               v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+               v0.AddArg(ptr)
+               v.AddArg(v0)
+               v.AddArg(mem)
+               return true
+       }
+       return false
+}
+func rewriteValueMIPS_OpZeroExt16to32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ZeroExt16to32 x)
+       // cond:
+       // result: (MOVHUreg x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVHUreg)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpZeroExt8to16(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ZeroExt8to16 x)
+       // cond:
+       // result: (MOVBUreg x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVBUreg)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpZeroExt8to32(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (ZeroExt8to32 x)
+       // cond:
+       // result: (MOVBUreg x)
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSMOVBUreg)
+               v.AddArg(x)
+               return true
+       }
+}
+func rewriteValueMIPS_OpZeromask(v *Value, config *Config) bool {
+       b := v.Block
+       _ = b
+       // match: (Zeromask x)
+       // cond:
+       // result: (NEG (SGTU x (MOVWconst [0])))
+       for {
+               x := v.Args[0]
+               v.reset(OpMIPSNEG)
+               v0 := b.NewValue0(v.Line, OpMIPSSGTU, config.fe.TypeBool())
+               v0.AddArg(x)
+               v1 := b.NewValue0(v.Line, OpMIPSMOVWconst, config.fe.TypeUInt32())
+               v1.AuxInt = 0
+               v0.AddArg(v1)
+               v.AddArg(v0)
+               return true
+       }
+}
+func rewriteBlockMIPS(b *Block, config *Config) bool {
+       switch b.Kind {
+       case BlockMIPSEQ:
+               // match: (EQ (FPFlagTrue cmp) yes no)
+               // cond:
+               // result: (FPF cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSFPFlagTrue {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSFPF
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (FPFlagFalse cmp) yes no)
+               // cond:
+               // result: (FPT cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSFPFlagFalse {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSFPT
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (XORconst [1] cmp:(SGT _ _)) yes no)
+               // cond:
+               // result: (NE cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGT {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (XORconst [1] cmp:(SGTU _ _)) yes no)
+               // cond:
+               // result: (NE cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTU {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (XORconst [1] cmp:(SGTconst _)) yes no)
+               // cond:
+               // result: (NE cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTconst {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (XORconst [1] cmp:(SGTUconst _)) yes no)
+               // cond:
+               // result: (NE cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTUconst {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (XORconst [1] cmp:(SGTzero _)) yes no)
+               // cond:
+               // result: (NE cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTzero {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (XORconst [1] cmp:(SGTUzero _)) yes no)
+               // cond:
+               // result: (NE cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTUzero {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (SGTUconst [1] x) yes no)
+               // cond:
+               // result: (NE x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTUconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (SGTUzero x) yes no)
+               // cond:
+               // result: (EQ x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTUzero {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (SGTconst [0] x) yes no)
+               // cond:
+               // result: (GEZ x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTconst {
+                               break
+                       }
+                       if v.AuxInt != 0 {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSGEZ
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ (SGTzero x) yes no)
+               // cond:
+               // result: (LEZ x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTzero {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSLEZ
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ  (MOVWconst [0]) yes no)
+               // cond:
+               // result: (First nil yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       if v.AuxInt != 0 {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (EQ  (MOVWconst [c]) yes no)
+               // cond: c != 0
+               // result: (First nil no yes)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(c != 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       b.swapSuccessors()
+                       _ = no
+                       _ = yes
+                       return true
+               }
+       case BlockMIPSGEZ:
+               // match: (GEZ (MOVWconst [c]) yes no)
+               // cond: int32(c) >= 0
+               // result: (First nil yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) >= 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (GEZ (MOVWconst [c]) yes no)
+               // cond: int32(c) <  0
+               // result: (First nil no yes)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) < 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       b.swapSuccessors()
+                       _ = no
+                       _ = yes
+                       return true
+               }
+       case BlockMIPSGTZ:
+               // match: (GTZ (MOVWconst [c]) yes no)
+               // cond: int32(c) >  0
+               // result: (First nil yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) > 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (GTZ (MOVWconst [c]) yes no)
+               // cond: int32(c) <= 0
+               // result: (First nil no yes)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) <= 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       b.swapSuccessors()
+                       _ = no
+                       _ = yes
+                       return true
+               }
+       case BlockIf:
+               // match: (If cond yes no)
+               // cond:
+               // result: (NE cond yes no)
+               for {
+                       v := b.Control
+                       _ = v
+                       cond := b.Control
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(cond)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+       case BlockMIPSLEZ:
+               // match: (LEZ (MOVWconst [c]) yes no)
+               // cond: int32(c) <= 0
+               // result: (First nil yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) <= 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (LEZ (MOVWconst [c]) yes no)
+               // cond: int32(c) >  0
+               // result: (First nil no yes)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) > 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       b.swapSuccessors()
+                       _ = no
+                       _ = yes
+                       return true
+               }
+       case BlockMIPSLTZ:
+               // match: (LTZ (MOVWconst [c]) yes no)
+               // cond: int32(c) <  0
+               // result: (First nil yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) < 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (LTZ (MOVWconst [c]) yes no)
+               // cond: int32(c) >= 0
+               // result: (First nil no yes)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(int32(c) >= 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       b.swapSuccessors()
+                       _ = no
+                       _ = yes
+                       return true
+               }
+       case BlockMIPSNE:
+               // match: (NE (FPFlagTrue cmp) yes no)
+               // cond:
+               // result: (FPT cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSFPFlagTrue {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSFPT
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (FPFlagFalse cmp) yes no)
+               // cond:
+               // result: (FPF cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSFPFlagFalse {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSFPF
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (XORconst [1] cmp:(SGT _ _)) yes no)
+               // cond:
+               // result: (EQ cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGT {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (XORconst [1] cmp:(SGTU _ _)) yes no)
+               // cond:
+               // result: (EQ cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTU {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (XORconst [1] cmp:(SGTconst _)) yes no)
+               // cond:
+               // result: (EQ cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTconst {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (XORconst [1] cmp:(SGTUconst _)) yes no)
+               // cond:
+               // result: (EQ cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTUconst {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (XORconst [1] cmp:(SGTzero _)) yes no)
+               // cond:
+               // result: (EQ cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTzero {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (XORconst [1] cmp:(SGTUzero _)) yes no)
+               // cond:
+               // result: (EQ cmp yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSXORconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       cmp := v.Args[0]
+                       if cmp.Op != OpMIPSSGTUzero {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(cmp)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (SGTUconst [1] x) yes no)
+               // cond:
+               // result: (EQ x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTUconst {
+                               break
+                       }
+                       if v.AuxInt != 1 {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSEQ
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (SGTUzero x) yes no)
+               // cond:
+               // result: (NE x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTUzero {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSNE
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (SGTconst [0] x) yes no)
+               // cond:
+               // result: (LTZ x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTconst {
+                               break
+                       }
+                       if v.AuxInt != 0 {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSLTZ
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE (SGTzero x) yes no)
+               // cond:
+               // result: (GTZ x yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSSGTzero {
+                               break
+                       }
+                       x := v.Args[0]
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockMIPSGTZ
+                       b.SetControl(x)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+               // match: (NE  (MOVWconst [0]) yes no)
+               // cond:
+               // result: (First nil no yes)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       if v.AuxInt != 0 {
+                               break
+                       }
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       b.swapSuccessors()
+                       _ = no
+                       _ = yes
+                       return true
+               }
+               // match: (NE  (MOVWconst [c]) yes no)
+               // cond: c != 0
+               // result: (First nil yes no)
+               for {
+                       v := b.Control
+                       if v.Op != OpMIPSMOVWconst {
+                               break
+                       }
+                       c := v.AuxInt
+                       yes := b.Succs[0]
+                       no := b.Succs[1]
+                       if !(c != 0) {
+                               break
+                       }
+                       b.Kind = BlockFirst
+                       b.SetControl(nil)
+                       _ = yes
+                       _ = no
+                       return true
+               }
+       }
+       return false
+}

diff --git a/src/cmd/compile/internal/ssa/rewritedec64.go b/src/cmd/compile/internal/ssa/rewritedec64.go
index d718da2258900a01e22189d02a1e3bb1ed455bee..deca0075141dbf4fb264f31eb3caee87b0d4bdda 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewritedec64.go
+++ b/src/cmd/compile/internal/ssa/rewritedec64.go
@@ -199,12 +199,12 @@ func rewriteValuedec64_OpArg(v *Value, config *Config) bool {
        b := v.Block
        _ = b
        // match: (Arg {n} [off])
-       // cond: is64BitInt(v.Type) && v.Type.IsSigned()
+       // cond: is64BitInt(v.Type) && !config.BigEndian && v.Type.IsSigned()
        // result: (Int64Make     (Arg <config.fe.TypeInt32()> {n} [off+4])     (Arg <config.fe.TypeUInt32()> {n} [off]))
        for {
                off := v.AuxInt
                n := v.Aux
-               if !(is64BitInt(v.Type) && v.Type.IsSigned()) {
+               if !(is64BitInt(v.Type) && !config.BigEndian && v.Type.IsSigned()) {
                        break
                }
                v.reset(OpInt64Make)
@@ -219,12 +219,12 @@ func rewriteValuedec64_OpArg(v *Value, config *Config) bool {
                return true
        }
        // match: (Arg {n} [off])
-       // cond: is64BitInt(v.Type) && !v.Type.IsSigned()
+       // cond: is64BitInt(v.Type) && !config.BigEndian && !v.Type.IsSigned()
        // result: (Int64Make     (Arg <config.fe.TypeUInt32()> {n} [off+4])     (Arg <config.fe.TypeUInt32()> {n} [off]))
        for {
                off := v.AuxInt
                n := v.Aux
-               if !(is64BitInt(v.Type) && !v.Type.IsSigned()) {
+               if !(is64BitInt(v.Type) && !config.BigEndian && !v.Type.IsSigned()) {
                        break
                }
                v.reset(OpInt64Make)
@@ -238,6 +238,46 @@ func rewriteValuedec64_OpArg(v *Value, config *Config) bool {
                v.AddArg(v1)
                return true
        }
+       // match: (Arg {n} [off])
+       // cond: is64BitInt(v.Type) && config.BigEndian && v.Type.IsSigned()
+       // result: (Int64Make     (Arg <config.fe.TypeInt32()> {n} [off])     (Arg <config.fe.TypeUInt32()> {n} [off+4]))
+       for {
+               off := v.AuxInt
+               n := v.Aux
+               if !(is64BitInt(v.Type) && config.BigEndian && v.Type.IsSigned()) {
+                       break
+               }
+               v.reset(OpInt64Make)
+               v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeInt32())
+               v0.AuxInt = off
+               v0.Aux = n
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeUInt32())
+               v1.AuxInt = off + 4
+               v1.Aux = n
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Arg {n} [off])
+       // cond: is64BitInt(v.Type) && config.BigEndian && !v.Type.IsSigned()
+       // result: (Int64Make     (Arg <config.fe.TypeUInt32()> {n} [off])     (Arg <config.fe.TypeUInt32()> {n} [off+4]))
+       for {
+               off := v.AuxInt
+               n := v.Aux
+               if !(is64BitInt(v.Type) && config.BigEndian && !v.Type.IsSigned()) {
+                       break
+               }
+               v.reset(OpInt64Make)
+               v0 := b.NewValue0(v.Line, OpArg, config.fe.TypeUInt32())
+               v0.AuxInt = off
+               v0.Aux = n
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpArg, config.fe.TypeUInt32())
+               v1.AuxInt = off + 4
+               v1.Aux = n
+               v.AddArg(v1)
+               return true
+       }
        return false
 }
 func rewriteValuedec64_OpBswap64(v *Value, config *Config) bool {
@@ -744,13 +784,13 @@ func rewriteValuedec64_OpLoad(v *Value, config *Config) bool {
        b := v.Block
        _ = b
        // match: (Load <t> ptr mem)
-       // cond: is64BitInt(t) && t.IsSigned()
+       // cond: is64BitInt(t) && !config.BigEndian && t.IsSigned()
        // result: (Int64Make           (Load <config.fe.TypeInt32()> (OffPtr <config.fe.TypeInt32().PtrTo()> [4] ptr) mem)             (Load <config.fe.TypeUInt32()> ptr mem))
        for {
                t := v.Type
                ptr := v.Args[0]
                mem := v.Args[1]
-               if !(is64BitInt(t) && t.IsSigned()) {
+               if !(is64BitInt(t) && !config.BigEndian && t.IsSigned()) {
                        break
                }
                v.reset(OpInt64Make)
@@ -768,13 +808,13 @@ func rewriteValuedec64_OpLoad(v *Value, config *Config) bool {
                return true
        }
        // match: (Load <t> ptr mem)
-       // cond: is64BitInt(t) && !t.IsSigned()
+       // cond: is64BitInt(t) && !config.BigEndian && !t.IsSigned()
        // result: (Int64Make           (Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem)           (Load <config.fe.TypeUInt32()> ptr mem))
        for {
                t := v.Type
                ptr := v.Args[0]
                mem := v.Args[1]
-               if !(is64BitInt(t) && !t.IsSigned()) {
+               if !(is64BitInt(t) && !config.BigEndian && !t.IsSigned()) {
                        break
                }
                v.reset(OpInt64Make)
@@ -791,6 +831,54 @@ func rewriteValuedec64_OpLoad(v *Value, config *Config) bool {
                v.AddArg(v2)
                return true
        }
+       // match: (Load <t> ptr mem)
+       // cond: is64BitInt(t) && config.BigEndian && t.IsSigned()
+       // result: (Int64Make           (Load <config.fe.TypeInt32()> ptr mem)          (Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is64BitInt(t) && config.BigEndian && t.IsSigned()) {
+                       break
+               }
+               v.reset(OpInt64Make)
+               v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeInt32())
+               v0.AddArg(ptr)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeUInt32())
+               v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeUInt32().PtrTo())
+               v2.AuxInt = 4
+               v2.AddArg(ptr)
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
+       // match: (Load <t> ptr mem)
+       // cond: is64BitInt(t) && config.BigEndian && !t.IsSigned()
+       // result: (Int64Make           (Load <config.fe.TypeUInt32()> ptr mem)                 (Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
+       for {
+               t := v.Type
+               ptr := v.Args[0]
+               mem := v.Args[1]
+               if !(is64BitInt(t) && config.BigEndian && !t.IsSigned()) {
+                       break
+               }
+               v.reset(OpInt64Make)
+               v0 := b.NewValue0(v.Line, OpLoad, config.fe.TypeUInt32())
+               v0.AddArg(ptr)
+               v0.AddArg(mem)
+               v.AddArg(v0)
+               v1 := b.NewValue0(v.Line, OpLoad, config.fe.TypeUInt32())
+               v2 := b.NewValue0(v.Line, OpOffPtr, config.fe.TypeUInt32().PtrTo())
+               v2.AuxInt = 4
+               v2.AddArg(ptr)
+               v1.AddArg(v2)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
        return false
 }
 func rewriteValuedec64_OpLrot64(v *Value, config *Config) bool {
@@ -2387,7 +2475,7 @@ func rewriteValuedec64_OpStore(v *Value, config *Config) bool {
        b := v.Block
        _ = b
        // match: (Store [8] dst (Int64Make hi lo) mem)
-       // cond:
+       // cond: !config.BigEndian
        // result: (Store [4]           (OffPtr <hi.Type.PtrTo()> [4] dst)              hi              (Store [4] dst lo mem))
        for {
                if v.AuxInt != 8 {
@@ -2401,6 +2489,9 @@ func rewriteValuedec64_OpStore(v *Value, config *Config) bool {
                hi := v_1.Args[0]
                lo := v_1.Args[1]
                mem := v.Args[2]
+               if !(!config.BigEndian) {
+                       break
+               }
                v.reset(OpStore)
                v.AuxInt = 4
                v0 := b.NewValue0(v.Line, OpOffPtr, hi.Type.PtrTo())
@@ -2416,6 +2507,39 @@ func rewriteValuedec64_OpStore(v *Value, config *Config) bool {
                v.AddArg(v1)
                return true
        }
+       // match: (Store [8] dst (Int64Make hi lo) mem)
+       // cond: config.BigEndian
+       // result: (Store [4]           (OffPtr <lo.Type.PtrTo()> [4] dst)              lo              (Store [4] dst hi mem))
+       for {
+               if v.AuxInt != 8 {
+                       break
+               }
+               dst := v.Args[0]
+               v_1 := v.Args[1]
+               if v_1.Op != OpInt64Make {
+                       break
+               }
+               hi := v_1.Args[0]
+               lo := v_1.Args[1]
+               mem := v.Args[2]
+               if !(config.BigEndian) {
+                       break
+               }
+               v.reset(OpStore)
+               v.AuxInt = 4
+               v0 := b.NewValue0(v.Line, OpOffPtr, lo.Type.PtrTo())
+               v0.AuxInt = 4
+               v0.AddArg(dst)
+               v.AddArg(v0)
+               v.AddArg(lo)
+               v1 := b.NewValue0(v.Line, OpStore, TypeMem)
+               v1.AuxInt = 4
+               v1.AddArg(dst)
+               v1.AddArg(hi)
+               v1.AddArg(mem)
+               v.AddArg(v1)
+               return true
+       }
        return false
 }
 func rewriteValuedec64_OpSub64(v *Value, config *Config) bool {

diff --git a/src/cmd/compile/internal/ssa/schedule.go b/src/cmd/compile/internal/ssa/schedule.go
index 411c09b971711cec5eacc69de7984e3e05699961..f2a89d82d833429bddc596bcb6a0bbcde982072d 100644 (file)
--- a/src/cmd/compile/internal/ssa/schedule.go
+++ b/src/cmd/compile/internal/ssa/schedule.go
@@ -88,7 +88,7 @@ func schedule(f *Func) {
                        case v.Op == OpAMD64LoweredGetClosurePtr || v.Op == OpPPC64LoweredGetClosurePtr ||
                                v.Op == OpARMLoweredGetClosurePtr || v.Op == OpARM64LoweredGetClosurePtr ||
                                v.Op == Op386LoweredGetClosurePtr || v.Op == OpMIPS64LoweredGetClosurePtr ||
-                               v.Op == OpS390XLoweredGetClosurePtr:
+                               v.Op == OpS390XLoweredGetClosurePtr || v.Op == OpMIPSLoweredGetClosurePtr:
                                // We also score GetLoweredClosurePtr as early as possible to ensure that the
                                // context register is not stomped. GetLoweredClosurePtr should only appear
                                // in the entry block where there are no phi functions, so there is no
@@ -100,7 +100,7 @@ func schedule(f *Func) {
                        case v.Op == OpAMD64LoweredNilCheck || v.Op == OpPPC64LoweredNilCheck ||
                                v.Op == OpARMLoweredNilCheck || v.Op == OpARM64LoweredNilCheck ||
                                v.Op == Op386LoweredNilCheck || v.Op == OpMIPS64LoweredNilCheck ||
-                               v.Op == OpS390XLoweredNilCheck:
+                               v.Op == OpS390XLoweredNilCheck || v.Op == OpMIPSLoweredNilCheck:
                                // Nil checks must come before loads from the same address.
                                score[v.ID] = ScoreNilCheck
                        case v.Op == OpPhi: