cmd/asm: use single-instruction forms for all loong64 sign and zero extensions

8-bit and 16-bit sign extensions and 32-bit zero extensions were realized
with left and right shifts before this change. We now support assembling
EXTWB, EXTWH and BSTRPICKV, so all three can be done with a single insn
respectively.

This patch is a copy of CL 479496.
Co-authored-by: WANG Xuerui <git@xen0n.name>
Change-Id: Iee5741dd9ebb25746f51008f3f6c86704339d615
Reviewed-on: https://go-review.googlesource.com/c/go/+/626195
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
index 459d161748b57dcf8aa1a65323427f2f202515c6..4b16aae5762baadc8f780fd4147e24101e4cf851 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
@@ -21,8 +21,11 @@ lable2:
        MOVW    $65536, R4              // 04020014
        MOVW    $4096, R4               // 24000014
        MOVV    $65536, R4              // 04020014
+       MOVB    R4, R5                  // 855c0000
+       MOVH    R4, R5                  // 85580000
        MOVV    $4096, R4               // 24000014
        MOVW    R4, R5                  // 85001700
+       MOVWU   R4, R5                  // 8500df00
        MOVV    R4, R5                  // 85001500
        MOVBU   R4, R5                  // 85fc4303
        SUB     R4, R5, R6              // a6101100

diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc2.s b/src/cmd/asm/internal/asm/testdata/loong64enc2.s
index 00768365b698e560d586952e68483e1db4db87aa..e497b83627ec8a5b068766252136da99be35f252 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/loong64enc2.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc2.s
@@ -5,8 +5,6 @@
 #include "../../../../../runtime/textflag.h"
 
 TEXT asmtest(SB),DUPOK|NOSPLIT,$0
-       MOVB    R4, R5                  // 85e04000a5e04800
-       MOVWU   R4, R5                  // 85804100a5804500
        MOVW    $74565, R4              // 4402001484148d03
        MOVW    $4097, R4               // 2400001484048003
        MOVV    $74565, R4              // 4402001484148d03
@@ -59,7 +57,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
        XOR     $4096, R4               // 3e00001484f81500
        XOR     $-1, R4, R5             // 1efcbf0285f81500
        XOR     $-1, R4                 // 1efcbf0284f81500
-       MOVH    R4, R5                  // 85c04000a5c04800
 
        // relocation instructions
        MOVW    R4, name(SB)            // 1e00001ac4038029

diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go
index d1200fa59863eb6c255e7df32adc3f7a84f977f8..7d8b18116fef70820462b8b2e62380af94edadf6 100644 (file)
--- a/src/cmd/internal/obj/loong64/asm.go
+++ b/src/cmd/internal/obj/loong64/asm.go
@@ -57,9 +57,9 @@ var optab = []Optab{
 
        {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
        {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
-       {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 8, 0, NOTUSETMP},
-       {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 13, 4, 0, 0},
-       {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 14, 8, 0, NOTUSETMP},
+       {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
+       {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
+       {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
 
        {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
        {ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
@@ -1511,29 +1511,21 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
                }
 
        case 12: // movbs r,r
-               // NOTE: this case does not use REGTMP. If it ever does,
-               // remove the NOTUSETMP flag in optab.
-               v := 16
-               if p.As == AMOVB {
-                       v = 24
-               }
-               o1 = OP_16IRR(c.opirr(ASLL), uint32(v), uint32(p.From.Reg), uint32(p.To.Reg))
-               o2 = OP_16IRR(c.opirr(ASRA), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
-
-       case 13: // movbu r,r
-               if p.As == AMOVBU {
+               switch p.As {
+               case AMOVB:
+                       o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
+               case AMOVH:
+                       o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
+               case AMOVBU:
                        o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
-               } else {
-                       // bstrpick.d (msbd=15, lsbd=0)
-                       o1 = (0x33c0 << 10) | ((uint32(p.From.Reg) & 0x1f) << 5) | (uint32(p.To.Reg) & 0x1F)
+               case AMOVHU:
+                       o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
+               case AMOVWU:
+                       o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
+               default:
+                       c.ctxt.Diag("unexpected encoding\n%v", p)
                }
 
-       case 14: // movwu r,r
-               // NOTE: this case does not use REGTMP. If it ever does,
-               // remove the NOTUSETMP flag in optab.
-               o1 = OP_16IRR(c.opirr(ASLLV), uint32(32)&0x3f, uint32(p.From.Reg), uint32(p.To.Reg))
-               o2 = OP_16IRR(c.opirr(ASRLV), uint32(32)&0x3f, uint32(p.To.Reg), uint32(p.To.Reg))
-
        case 15: // teq $c r,r
                v := c.regoff(&p.From)
                r := int(p.Reg)