cmd: update x/arch to pull in CL 315572

Because x/arch is now lazy, this removes the checksum for rsc.io/pdf
from the go.sum file: the requirements of rsc.io/pdf are known not to
be relevant to any package imported within the cmd packages.

For #36460
Updates #36905

Change-Id: I3abb6a8029cd0c9099b592ccb01ca5606c93edec
Reviewed-on: https://go-review.googlesource.com/c/go/+/316110
Trust: Bryan C. Mills <bcmills@google.com>
Run-TryBot: Bryan C. Mills <bcmills@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Dmitri Shuralyov <dmitshur@golang.org>

diff --git a/src/cmd/go.mod b/src/cmd/go.mod
index 1487025268577517d7390b20b260ce26169dbcdc..96f709081f115f781470fddc35f0ca613fa0980c 100644 (file)
--- a/src/cmd/go.mod
+++ b/src/cmd/go.mod
@@ -5,7 +5,7 @@ go 1.17
 require (
        github.com/google/pprof v0.0.0-20210226084205-cbba55b83ad5
        github.com/ianlancetaylor/demangle v0.0.0-20200824232613-28f6c0f3b639 // indirect
-       golang.org/x/arch v0.0.0-20210308155006-05f8f0431f72
+       golang.org/x/arch v0.0.0-20210502124803-cbf565b21d1e
        golang.org/x/crypto v0.0.0-20210220033148-5ea612d1eb83 // indirect
        golang.org/x/mod v0.4.3-0.20210409134425-858fdbee9c24
        golang.org/x/sys v0.0.0-20210403161142-5e06dd20ab57 // indirect

diff --git a/src/cmd/go.sum b/src/cmd/go.sum
index 0f13c366d019e54f73c1bf5306a02762e0e52800..9c702d0d330bd7c6dbcb241ea3ab064f674ddb44 100644 (file)
--- a/src/cmd/go.sum
+++ b/src/cmd/go.sum
@@ -6,8 +6,8 @@ github.com/google/pprof v0.0.0-20210226084205-cbba55b83ad5/go.mod h1:kpwsk12EmLe
 github.com/ianlancetaylor/demangle v0.0.0-20200824232613-28f6c0f3b639 h1:mV02weKRL81bEnm8A0HT1/CAelMQDBuQIfLw8n+d6xI=
 github.com/ianlancetaylor/demangle v0.0.0-20200824232613-28f6c0f3b639/go.mod h1:aSSvb/t6k1mPoxDqO4vJh6VOCGPwU4O0C2/Eqndh1Sc=
 github.com/yuin/goldmark v1.3.3/go.mod h1:mwnBkeHKe2W/ZEtQ+71ViKU8L12m81fl3OWwC1Zlc8k=
-golang.org/x/arch v0.0.0-20210308155006-05f8f0431f72 h1:CdaLHkic8S6xdhpWgHmtWij2rv2DTGwPuJZjjEDGk2w=
-golang.org/x/arch v0.0.0-20210308155006-05f8f0431f72/go.mod h1:flIaEI6LNU6xOCD5PaJvn9wGP0agmIOqjrtsKGRguv4=
+golang.org/x/arch v0.0.0-20210502124803-cbf565b21d1e h1:pv3V0NlNSh5Q6AX/StwGLBjcLS7UN4m4Gq+V+uSecqM=
+golang.org/x/arch v0.0.0-20210502124803-cbf565b21d1e/go.mod h1:5om86z9Hs0C8fWVUuoMHwpExlXzs5Tkyp9hOrfG7pp8=
 golang.org/x/crypto v0.0.0-20190308221718-c2843e01d9a2/go.mod h1:djNgcEr1/C05ACkg1iLfiJU5Ep61QUkGW8qpdssI0+w=
 golang.org/x/crypto v0.0.0-20191011191535-87dc89f01550/go.mod h1:yigFU9vqHzYiE8UmvKecakEJjdnWj3jj499lnFckfCI=
 golang.org/x/crypto v0.0.0-20210220033148-5ea612d1eb83 h1:/ZScEX8SfEmUGRHs0gxpqteO5nfNW6axyZbBdw9A12g=
@@ -42,4 +42,3 @@ golang.org/x/xerrors v0.0.0-20190717185122-a985d3407aa7/go.mod h1:I/5z698sn9Ka8T
 golang.org/x/xerrors v0.0.0-20191011141410-1b5146add898/go.mod h1:I/5z698sn9Ka8TeJc9MKroUUfqBBauWjQqLJ2OPfmY0=
 golang.org/x/xerrors v0.0.0-20200804184101-5ec99f83aff1 h1:go1bK/D/BFZV2I8cIQd1NKEZ+0owSTG1fDTci4IqFcE=
 golang.org/x/xerrors v0.0.0-20200804184101-5ec99f83aff1/go.mod h1:I/5z698sn9Ka8TeJc9MKroUUfqBBauWjQqLJ2OPfmY0=
-rsc.io/pdf v0.1.1/go.mod h1:n8OzWcQ6Sp37PL01nO98y4iUCRdTGarVfzxY20ICaU4=

diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
index bae42e284ebaaf07022359ad3de6cbb713d0b2d1..3aaf0b2a3030cc33352116b6c94f579c931128db 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
+++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
@@ -126,7 +126,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
                        op = "VMOV"
                }
 
-       case LDR:
+       case LDR, LDUR:
                var rno uint16
                if r, ok := inst.Args[0].(Reg); ok {
                        rno = uint16(r)
@@ -135,12 +135,21 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
                }
                if rno <= uint16(WZR) {
                        op = "MOVWU" + suffix
+               } else if rno >= uint16(B0) && rno <= uint16(B31) {
+                       op = "FMOVB" + suffix
+                       args[0] = fmt.Sprintf("F%d", rno&31)
+               } else if rno >= uint16(H0) && rno <= uint16(H31) {
+                       op = "FMOVH" + suffix
+                       args[0] = fmt.Sprintf("F%d", rno&31)
                } else if rno >= uint16(S0) && rno <= uint16(S31) {
                        op = "FMOVS" + suffix
                        args[0] = fmt.Sprintf("F%d", rno&31)
                } else if rno >= uint16(D0) && rno <= uint16(D31) {
                        op = "FMOVD" + suffix
                        args[0] = fmt.Sprintf("F%d", rno&31)
+               } else if rno >= uint16(Q0) && rno <= uint16(Q31) {
+                       op = "FMOVQ" + suffix
+                       args[0] = fmt.Sprintf("F%d", rno&31)
                } else {
                        op = "MOVD" + suffix
                }
@@ -181,12 +190,21 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
                }
                if rno <= uint16(WZR) {
                        op = "MOVW" + suffix
+               } else if rno >= uint16(B0) && rno <= uint16(B31) {
+                       op = "FMOVB" + suffix
+                       args[0] = fmt.Sprintf("F%d", rno&31)
+               } else if rno >= uint16(H0) && rno <= uint16(H31) {
+                       op = "FMOVH" + suffix
+                       args[0] = fmt.Sprintf("F%d", rno&31)
                } else if rno >= uint16(S0) && rno <= uint16(S31) {
                        op = "FMOVS" + suffix
                        args[0] = fmt.Sprintf("F%d", rno&31)
                } else if rno >= uint16(D0) && rno <= uint16(D31) {
                        op = "FMOVD" + suffix
                        args[0] = fmt.Sprintf("F%d", rno&31)
+               } else if rno >= uint16(Q0) && rno <= uint16(Q31) {
+                       op = "FMOVQ" + suffix
+                       args[0] = fmt.Sprintf("F%d", rno&31)
                } else {
                        op = "MOVD" + suffix
                }
@@ -251,18 +269,31 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
                                op += "W"
                        }
                }
-               fallthrough
+               args[0] = fmt.Sprintf("(%s, %s)", args[0], args[1])
+               args[1] = args[2]
+               return op + " " + args[1] + ", " + args[0]
 
        case STP, LDP:
                args[0] = fmt.Sprintf("(%s, %s)", args[0], args[1])
                args[1] = args[2]
-               if op == "STP" {
-                       op = op + suffix
+
+               rno, ok := inst.Args[0].(Reg)
+               if !ok {
+                       rno = Reg(inst.Args[0].(RegSP))
+               }
+               if rno <= WZR {
+                       op = op + "W"
+               } else if rno >= S0 && rno <= S31 {
+                       op = "F" + op + "S"
+               } else if rno >= D0 && rno <= D31 {
+                       op = "F" + op + "D"
+               } else if rno >= Q0 && rno <= Q31 {
+                       op = "F" + op + "Q"
+               }
+               op = op + suffix
+               if inst.Op.String() == "STP" {
                        return op + " " + args[0] + ", " + args[1]
-               } else if op == "LDP" {
-                       op = op + suffix
-                       return op + " " + args[1] + ", " + args[0]
-               } else if op == "LDAXP" || op == "LDXP" || op == "LDAXPW" || op == "LDXPW" {
+               } else {
                        return op + " " + args[1] + ", " + args[0]
                }
 
@@ -469,6 +500,12 @@ SHA256SU0
 SHA256SU1
 `)
 
+// floating point instrcutions without "F" prefix.
+var fOpsWithoutFPrefix = map[Op]bool{
+       LDP: true,
+       STP: true,
+}
+
 func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
        switch a := arg.(type) {
        case Imm:
@@ -494,20 +531,17 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg
                regenum := uint16(a)
                regno := uint16(a) & 31
 
-               if regenum >= uint16(B0) && regenum <= uint16(D31) {
-                       if strings.HasPrefix(inst.Op.String(), "F") || strings.HasSuffix(inst.Op.String(), "CVTF") {
+               if regenum >= uint16(B0) && regenum <= uint16(Q31) {
+                       if strings.HasPrefix(inst.Op.String(), "F") || strings.HasSuffix(inst.Op.String(), "CVTF") || fOpsWithoutFPrefix[inst.Op] {
                                // FP registers are the same ones as SIMD registers
                                // Print Fn for scalar variant to align with assembler (e.g., FCVT, SCVTF, UCVTF, etc.)
                                return fmt.Sprintf("F%d", regno)
                        } else {
+                               // Print Vn to align with assembler (e.g., SHA256H)
                                return fmt.Sprintf("V%d", regno)
                        }
 
-               } else if regenum >= uint16(Q0) && regenum <= uint16(Q31) {
-                       // Print Vn to align with assembler (e.g., SHA256H)
-                       return fmt.Sprintf("V%d", regno)
                }
-
                if regno == 31 {
                        return "ZR"
                }

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
index 5f04ff40e450a5b9d4e58cd9f344086b4e1e7cd1..59bd3258ef64f091abe5561e7e1e6994774859b3 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go
@@ -12,18 +12,25 @@ import (
 
 const debugDecode = false
 
+const prefixOpcode = 1
+
 // instFormat is a decoding rule for one specific instruction form.
-// a uint32 instruction ins matches the rule if ins&Mask == Value
+// an instruction ins matches the rule if ins&Mask == Value
 // DontCare bits should be zero, but the machine might not reject
 // ones in those bits, they are mainly reserved for future expansion
 // of the instruction set.
 // The Args are stored in the same order as the instruction manual.
+//
+// Prefixed instructions are stored as:
+//   prefix << 32 | suffix,
+// Regular instructions are:
+//   inst << 32
 type instFormat struct {
        Op       Op
-       Mask     uint32
-       Value    uint32
-       DontCare uint32
-       Args     [5]*argField
+       Mask     uint64
+       Value    uint64
+       DontCare uint64
+       Args     [6]*argField
 }
 
 // argField indicate how to decode an argument to an instruction.
@@ -36,7 +43,7 @@ type argField struct {
 }
 
 // Parse parses the Arg out from the given binary instruction i.
-func (a argField) Parse(i uint32) Arg {
+func (a argField) Parse(i [2]uint32) Arg {
        switch a.Type {
        default:
                return nil
@@ -54,6 +61,10 @@ func (a argField) Parse(i uint32) Arg {
                return V0 + Reg(a.BitFields.Parse(i))
        case TypeVecSReg:
                return VS0 + Reg(a.BitFields.Parse(i))
+       case TypeVecSpReg:
+               return VS0 + Reg(a.BitFields.Parse(i))*2
+       case TypeMMAReg:
+               return A0 + Reg(a.BitFields.Parse(i))
        case TypeSpReg:
                return SpReg(a.BitFields.Parse(i))
        case TypeImmSigned:
@@ -81,6 +92,8 @@ const (
        TypeFPReg                // floating point register
        TypeVecReg               // vector register
        TypeVecSReg              // VSX register
+       TypeVecSpReg             // VSX register pair (even only encoding)
+       TypeMMAReg               // MMA register
        TypeSpReg                // special register (depends on Op)
        TypeImmSigned            // signed immediate
        TypeImmUnsigned          // unsigned immediate/flag/mask, this is the catch-all type
@@ -106,6 +119,10 @@ func (t ArgType) String() string {
                return "VecReg"
        case TypeVecSReg:
                return "VecSReg"
+       case TypeVecSpReg:
+               return "VecSpReg"
+       case TypeMMAReg:
+               return "MMAReg"
        case TypeSpReg:
                return "SpReg"
        case TypeImmSigned:
@@ -146,9 +163,22 @@ func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
        if decoderCover == nil {
                decoderCover = make([]bool, len(instFormats))
        }
-       inst.Len = 4 // only 4-byte instructions are supported
-       ui := ord.Uint32(src[:inst.Len])
-       inst.Enc = ui
+       inst.Len = 4
+       ui_extn := [2]uint32{ord.Uint32(src[:inst.Len]), 0}
+       ui := uint64(ui_extn[0]) << 32
+       inst.Enc = ui_extn[0]
+       opcode := inst.Enc >> 26
+       if opcode == prefixOpcode {
+               // This is a prefixed instruction
+               inst.Len = 8
+               if len(src) < 8 {
+                       return inst, errShort
+               }
+               // Merge the suffixed word.
+               ui_extn[1] = ord.Uint32(src[4:inst.Len])
+               ui |= uint64(ui_extn[1])
+               inst.SuffixEnc = ui_extn[1]
+       }
        for i, iform := range instFormats {
                if ui&iform.Mask != iform.Value {
                        continue
@@ -163,7 +193,7 @@ func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
                        if argfield == nil {
                                break
                        }
-                       inst.Args[i] = argfield.Parse(ui)
+                       inst.Args[i] = argfield.Parse(ui_extn)
                }
                inst.Op = iform.Op
                if debugDecode {

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go
index 26a4fdf1a054f07c7e6232140c1c70cfc234c91f..882c91ae1277ebb2c1fd82e911dee4213085863c 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/field.go
@@ -14,6 +14,10 @@ import (
 type BitField struct {
        Offs uint8 // the offset of the left-most bit.
        Bits uint8 // length in bits.
+       // This instruction word holding this field.
+       // It is always 0 for ISA < 3.1 instructions. It is
+       // in decoding order. (0 == prefix, 1 == suffix on ISA 3.1)
+       Word uint8
 }
 
 func (b BitField) String() string {
@@ -28,16 +32,16 @@ func (b BitField) String() string {
 
 // Parse extracts the bitfield b from i, and return it as an unsigned integer.
 // Parse will panic if b is invalid.
-func (b BitField) Parse(i uint32) uint32 {
+func (b BitField) Parse(i [2]uint32) uint32 {
        if b.Bits > 32 || b.Bits == 0 || b.Offs > 31 || b.Offs+b.Bits > 32 {
                panic(fmt.Sprintf("invalid bitfiled %v", b))
        }
-       return (i >> (32 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1)
+       return (i[b.Word] >> (32 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1)
 }
 
 // ParseSigned extracts the bitfield b from i, and return it as a signed integer.
 // ParseSigned will panic if b is invalid.
-func (b BitField) ParseSigned(i uint32) int32 {
+func (b BitField) ParseSigned(i [2]uint32) int32 {
        u := int32(b.Parse(i))
        return u << (32 - b.Bits) >> (32 - b.Bits)
 }
@@ -61,9 +65,9 @@ func (bs *BitFields) Append(b BitField) {
 // as an unsigned integer and the total length of all the bitfields.
 // parse will panic if any bitfield in b is invalid, but it doesn't check if
 // the sequence of bitfields is reasonable.
-func (bs BitFields) parse(i uint32) (u uint32, Bits uint8) {
+func (bs BitFields) parse(i [2]uint32) (u uint64, Bits uint8) {
        for _, b := range bs {
-               u = (u << b.Bits) | b.Parse(i)
+               u = (uint64(u) << b.Bits) | uint64(b.Parse(i))
                Bits += b.Bits
        }
        return u, Bits
@@ -71,14 +75,14 @@ func (bs BitFields) parse(i uint32) (u uint32, Bits uint8) {
 
 // Parse extracts the bitfields from i, concatenate them and return the result
 // as an unsigned integer. Parse will panic if any bitfield in b is invalid.
-func (bs BitFields) Parse(i uint32) uint32 {
+func (bs BitFields) Parse(i [2]uint32) uint64 {
        u, _ := bs.parse(i)
        return u
 }
 
 // Parse extracts the bitfields from i, concatenate them and return the result
 // as a signed integer. Parse will panic if any bitfield in b is invalid.
-func (bs BitFields) ParseSigned(i uint32) int32 {
+func (bs BitFields) ParseSigned(i [2]uint32) int64 {
        u, l := bs.parse(i)
-       return int32(u) << (32 - l) >> (32 - l)
+       return int64(u) << (64 - l) >> (64 - l)
 }

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
index 46317497459b072a77ffd8117fef993e13b2d97f..225ef4fb88d2aecf00b2e41bd03c8e8df5d9920a 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go
@@ -34,6 +34,8 @@ func GNUSyntax(inst Inst, pc uint64) string {
        startArg := 0
        sep := " "
        opName := inst.Op.String()
+       argList := inst.Args[:]
+
        switch opName {
        case "bc", "bcl", "bca", "bcla", "bclr", "bclrl", "bcctr", "bcctrl", "bctar", "bctarl":
                sfx := inst.Op.String()[2:]
@@ -223,23 +225,111 @@ func GNUSyntax(inst Inst, pc uint64) string {
                        buf.WriteString("spr")
                }
 
+       case "mtfsfi", "mtfsfi.":
+               buf.WriteString(opName)
+               l := inst.Args[2].(Imm)
+               if l == 0 {
+                       // L == 0 is an extended mnemonic for the same.
+                       asm := fmt.Sprintf(" %s,%s",
+                               gnuArg(&inst, 0, inst.Args[0], PC),
+                               gnuArg(&inst, 1, inst.Args[1], PC))
+                       buf.WriteString(asm)
+                       startArg = 3
+               }
+
+       case "paste.":
+               buf.WriteString(opName)
+               l := inst.Args[2].(Imm)
+               if l == 1 {
+                       // L == 1 is an extended mnemonic for the same.
+                       asm := fmt.Sprintf(" %s,%s",
+                               gnuArg(&inst, 0, inst.Args[0], PC),
+                               gnuArg(&inst, 1, inst.Args[1], PC))
+                       buf.WriteString(asm)
+                       startArg = 3
+               }
+
+       case "mtfsf", "mtfsf.":
+               buf.WriteString(opName)
+               l := inst.Args[3].(Imm)
+               if l == 0 {
+                       // L == 0 is an extended mnemonic for the same.
+                       asm := fmt.Sprintf(" %s,%s,%s",
+                               gnuArg(&inst, 0, inst.Args[0], PC),
+                               gnuArg(&inst, 1, inst.Args[1], PC),
+                               gnuArg(&inst, 2, inst.Args[2], PC))
+                       buf.WriteString(asm)
+                       startArg = 4
+               }
+
        case "sync":
-               switch arg := inst.Args[0].(type) {
-               case Imm:
-                       switch arg {
-                       case 0:
-                               buf.WriteString("hwsync")
-                       case 1:
-                               buf.WriteString("lwsync")
-                       case 2:
-                               buf.WriteString("ptesync")
-                       }
+               lsc := inst.Args[0].(Imm)<<4 | inst.Args[1].(Imm)
+               switch lsc {
+               case 0x00:
+                       buf.WriteString("hwsync")
+                       startArg = 2
+               case 0x10:
+                       buf.WriteString("lwsync")
+                       startArg = 2
+               default:
+                       buf.WriteString(opName)
+               }
+
+       case "lbarx", "lharx", "lwarx", "ldarx":
+               // If EH == 0, omit printing EH.
+               eh := inst.Args[3].(Imm)
+               if eh == 0 {
+                       argList = inst.Args[:3]
                }
-               startArg = 2
-       default:
                buf.WriteString(inst.Op.String())
+
+       case "paddi":
+               // There are several extended mnemonics.  Notably, "pla" is
+               // the only valid mnemonic for paddi (R=1), In this case, RA must
+               // always be 0.  Otherwise it is invalid.
+               r := inst.Args[3].(Imm)
+               ra := inst.Args[1].(Reg)
+               str := opName
+               if ra == R0 {
+                       name := []string{"pli", "pla"}
+                       str = fmt.Sprintf("%s %s,%s",
+                               name[r&1],
+                               gnuArg(&inst, 0, inst.Args[0], PC),
+                               gnuArg(&inst, 2, inst.Args[2], PC))
+                       startArg = 4
+               } else if r == 0 {
+                       str = fmt.Sprintf("%s %s,%s,%s", opName,
+                               gnuArg(&inst, 0, inst.Args[0], PC),
+                               gnuArg(&inst, 1, inst.Args[1], PC),
+                               gnuArg(&inst, 2, inst.Args[2], PC))
+                       startArg = 4
+               }
+               buf.WriteString(str)
+
+       default:
+               // Prefixed load/stores do not print the displacement register when R==1 (they are PCrel).
+               // This also implies RA should be 0.  Likewise, when R==0, printing of R can be omitted.
+               if strings.HasPrefix(opName, "pl") || strings.HasPrefix(opName, "pst") {
+                       r := inst.Args[3].(Imm)
+                       ra := inst.Args[2].(Reg)
+                       d := inst.Args[1].(Offset)
+                       if r == 1 && ra == R0 {
+                               str := fmt.Sprintf("%s %s,%d", opName, gnuArg(&inst, 0, inst.Args[0], PC), d)
+                               buf.WriteString(str)
+                               startArg = 4
+                       } else if r == 0 {
+                               str := fmt.Sprintf("%s %s,%d(%s)", opName,
+                                       gnuArg(&inst, 0, inst.Args[0], PC),
+                                       d,
+                                       gnuArg(&inst, 2, inst.Args[2], PC))
+                               buf.WriteString(str)
+                               startArg = 4
+                       }
+               } else {
+                       buf.WriteString(opName)
+               }
        }
-       for i, arg := range inst.Args[:] {
+       for i, arg := range argList {
                if arg == nil {
                        break
                }

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go
index 870522a10b3637ab7cd045b8404398a6b5f9bfc7..41e04513ddafb70e404557fa2bdf8cc39622baf1 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go
@@ -10,10 +10,11 @@ import (
 )
 
 type Inst struct {
-       Op   Op     // Opcode mnemonic
-       Enc  uint32 // Raw encoding bits
-       Len  int    // Length of encoding in bytes.
-       Args Args   // Instruction arguments, in Power ISA manual order.
+       Op        Op     // Opcode mnemonic
+       Enc       uint32 // Raw encoding bits (if Len == 8, this is the prefix word)
+       Len       int    // Length of encoding in bytes.
+       SuffixEnc uint32 // Raw encoding bits of second word (if Len == 8)
+       Args      Args   // Instruction arguments, in Power ISA manual order.
 }
 
 func (i Inst) String() string {
@@ -50,9 +51,9 @@ type Arg interface {
 }
 
 // An Args holds the instruction arguments.
-// If an instruction has fewer than 4 arguments,
+// If an instruction has fewer than 6 arguments,
 // the final elements in the array are nil.
-type Args [5]Arg
+type Args [6]Arg
 
 // A Reg is a single register. The zero value means R0, not the absence of a register.
 // It also includes special registers.
@@ -220,6 +221,14 @@ const (
        VS61
        VS62
        VS63
+       A0 // MMA registers.  These are effectively shadow registers of four adjacent VSR's [An*4,An*4+3]
+       A1
+       A2
+       A3
+       A4
+       A5
+       A6
+       A7
 )
 
 func (Reg) IsArg() {}
@@ -233,6 +242,8 @@ func (r Reg) String() string {
                return fmt.Sprintf("v%d", int(r-V0))
        case VS0 <= r && r <= VS63:
                return fmt.Sprintf("vs%d", int(r-VS0))
+       case A0 <= r && r <= A7:
+               return fmt.Sprintf("a%d", int(r-A0))
        default:
                return fmt.Sprintf("Reg(%d)", int(r))
        }
@@ -328,7 +339,7 @@ func (l Label) String() string {
 }
 
 // Imm represents an immediate number.
-type Imm int32
+type Imm int64
 
 func (Imm) IsArg() {}
 func (i Imm) String() string {
@@ -336,7 +347,7 @@ func (i Imm) String() string {
 }
 
 // Offset represents a memory offset immediate.
-type Offset int32
+type Offset int64
 
 func (Offset) IsArg() {}
 func (o Offset) String() string {

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
index 48a4e9790aa3b8563b3b4946228edd434bb20d2d..89b917320a314ce45ac5928600f04a6348fcb38c 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
@@ -76,6 +76,9 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
                }
                args = append(args, args[0])
                return op + " " + strings.Join(args[1:], ",")
+       case PASTECC:
+               // paste. has two input registers, and an L field, unlike other 3 operand instructions.
+               return op + " " + args[0] + "," + args[1] + "," + args[2]
        case SYNC:
                if args[0] == "$1" {
                        return "LWSYNC"
@@ -136,7 +139,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) strin
        case LXVL, LXVLL:
                return op + " " + args[1] + "," + args[2] + "," + args[0]
 
-       case DCBT, DCBTST, DCBZ, DCBST, DCBI, ICBI:
+       case DCBT, DCBTST, DCBZ, DCBST, ICBI:
                if args[0] == "0" || args[0] == "R0" {
                        return op + " (" + args[1] + ")"
                }

diff --git a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
index 971816ddac6ad386a0619f10011bc9f7fe69dd34..d42ab0f29441fdbec1bd85c6bb018ff734123a74 100644 (file)
--- a/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
+++ b/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
@@ -1,797 +1,669 @@
 // DO NOT EDIT
-// generated by: ppc64map -fmt=decoder pp64.csv
+// generated by: ppc64map -fmt=decoder ../pp64.csv
 
 package ppc64asm
 
 const (
        _ Op = iota
-       CNTLZW
-       CNTLZWCC
-       B
-       BA
-       BL
-       BLA
-       BC
-       BCA
-       BCL
-       BCLA
-       BCLR
-       BCLRL
-       BCCTR
-       BCCTRL
+       BRD
+       BRH
+       BRW
+       CFUGED
+       CNTLZDM
+       CNTTZDM
+       DCFFIXQQ
+       DCTFIXQQ
+       LXVKQ
+       LXVP
+       LXVPX
+       LXVRBX
+       LXVRDX
+       LXVRHX
+       LXVRWX
+       MTVSRBM
+       MTVSRBMI
+       MTVSRDM
+       MTVSRHM
+       MTVSRQM
+       MTVSRWM
+       PADDI
+       PDEPD
+       PEXTD
+       PLBZ
+       PLD
+       PLFD
+       PLFS
+       PLHA
+       PLHZ
+       PLQ
+       PLWA
+       PLWZ
+       PLXSD
+       PLXSSP
+       PLXV
+       PLXVP
+       PMXVBF16GER2
+       PMXVBF16GER2NN
+       PMXVBF16GER2NP
+       PMXVBF16GER2PN
+       PMXVBF16GER2PP
+       PMXVF16GER2
+       PMXVF16GER2NN
+       PMXVF16GER2NP
+       PMXVF16GER2PN
+       PMXVF16GER2PP
+       PMXVF32GER
+       PMXVF32GERNN
+       PMXVF32GERNP
+       PMXVF32GERPN
+       PMXVF32GERPP
+       PMXVF64GER
+       PMXVF64GERNN
+       PMXVF64GERNP
+       PMXVF64GERPN
+       PMXVF64GERPP
+       PMXVI16GER2
+       PMXVI16GER2PP
+       PMXVI16GER2S
+       PMXVI16GER2SPP
+       PMXVI4GER8
+       PMXVI4GER8PP
+       PMXVI8GER4
+       PMXVI8GER4PP
+       PMXVI8GER4SPP
+       PNOP
+       PSTB
+       PSTD
+       PSTFD
+       PSTFS
+       PSTH
+       PSTQ
+       PSTW
+       PSTXSD
+       PSTXSSP
+       PSTXV
+       PSTXVP
+       SETBC
+       SETBCR
+       SETNBC
+       SETNBCR
+       STXVP
+       STXVPX
+       STXVRBX
+       STXVRDX
+       STXVRHX
+       STXVRWX
+       VCFUGED
+       VCLRLB
+       VCLRRB
+       VCLZDM
+       VCMPEQUQ
+       VCMPEQUQCC
+       VCMPGTSQ
+       VCMPGTSQCC
+       VCMPGTUQ
+       VCMPGTUQCC
+       VCMPSQ
+       VCMPUQ
+       VCNTMBB
+       VCNTMBD
+       VCNTMBH
+       VCNTMBW
+       VCTZDM
+       VDIVESD
+       VDIVESQ
+       VDIVESW
+       VDIVEUD
+       VDIVEUQ
+       VDIVEUW
+       VDIVSD
+       VDIVSQ
+       VDIVSW
+       VDIVUD
+       VDIVUQ
+       VDIVUW
+       VEXPANDBM
+       VEXPANDDM
+       VEXPANDHM
+       VEXPANDQM
+       VEXPANDWM
+       VEXTDDVLX
+       VEXTDDVRX
+       VEXTDUBVLX
+       VEXTDUBVRX
+       VEXTDUHVLX
+       VEXTDUHVRX
+       VEXTDUWVLX
+       VEXTDUWVRX
+       VEXTRACTBM
+       VEXTRACTDM
+       VEXTRACTHM
+       VEXTRACTQM
+       VEXTRACTWM
+       VEXTSD2Q
+       VGNB
+       VINSBLX
+       VINSBRX
+       VINSBVLX
+       VINSBVRX
+       VINSD
+       VINSDLX
+       VINSDRX
+       VINSHLX
+       VINSHRX
+       VINSHVLX
+       VINSHVRX
+       VINSW
+       VINSWLX
+       VINSWRX
+       VINSWVLX
+       VINSWVRX
+       VMODSD
+       VMODSQ
+       VMODSW
+       VMODUD
+       VMODUQ
+       VMODUW
+       VMSUMCUD
+       VMULESD
+       VMULEUD
+       VMULHSD
+       VMULHSW
+       VMULHUD
+       VMULHUW
+       VMULLD
+       VMULOSD
+       VMULOUD
+       VPDEPD
+       VPEXTD
+       VRLQ
+       VRLQMI
+       VRLQNM
+       VSLDBI
+       VSLQ
+       VSRAQ
+       VSRDBI
+       VSRQ
+       VSTRIBL
+       VSTRIBLCC
+       VSTRIBR
+       VSTRIBRCC
+       VSTRIHL
+       VSTRIHLCC
+       VSTRIHR
+       VSTRIHRCC
+       XSCMPEQQP
+       XSCMPGEQP
+       XSCMPGTQP
+       XSCVQPSQZ
+       XSCVQPUQZ
+       XSCVSQQP
+       XSCVUQQP
+       XSMAXCQP
+       XSMINCQP
+       XVBF16GER2
+       XVBF16GER2NN
+       XVBF16GER2NP
+       XVBF16GER2PN
+       XVBF16GER2PP
+       XVCVBF16SPN
+       XVCVSPBF16
+       XVF16GER2
+       XVF16GER2NN
+       XVF16GER2NP
+       XVF16GER2PN
+       XVF16GER2PP
+       XVF32GER
+       XVF32GERNN
+       XVF32GERNP
+       XVF32GERPN
+       XVF32GERPP
+       XVF64GER
+       XVF64GERNN
+       XVF64GERNP
+       XVF64GERPN
+       XVF64GERPP
+       XVI16GER2
+       XVI16GER2PP
+       XVI16GER2S
+       XVI16GER2SPP
+       XVI4GER8
+       XVI4GER8PP
+       XVI8GER4
+       XVI8GER4PP
+       XVI8GER4SPP
+       XVTLSBB
+       XXBLENDVB
+       XXBLENDVD
+       XXBLENDVH
+       XXBLENDVW
+       XXEVAL
+       XXGENPCVBM
+       XXGENPCVDM
+       XXGENPCVHM
+       XXGENPCVWM
+       XXMFACC
+       XXMTACC
+       XXPERMX
+       XXSETACCZ
+       XXSPLTI32DX
+       XXSPLTIDP
+       XXSPLTIW
+       MSGCLRU
+       MSGSNDU
+       URFID
+       ADDEX
+       MFFSCDRN
+       MFFSCDRNI
+       MFFSCE
+       MFFSCRN
+       MFFSCRNI
+       MFFSL
+       SLBIAG
+       VMSUMUDM
+       ADDPCIS
+       BCDCFNCC
+       BCDCFSQCC
+       BCDCFZCC
+       BCDCPSGNCC
+       BCDCTNCC
+       BCDCTSQCC
+       BCDCTZCC
+       BCDSCC
+       BCDSETSGNCC
+       BCDSRCC
+       BCDTRUNCCC
+       BCDUSCC
+       BCDUTRUNCCC
+       CMPEQB
+       CMPRB
+       CNTTZD
+       CNTTZDCC
+       CNTTZW
+       CNTTZWCC
+       COPY
+       CPABORT
+       DARN
+       DTSTSFI
+       DTSTSFIQ
+       EXTSWSLI
+       EXTSWSLICC
+       LDAT
+       LWAT
+       LXSD
+       LXSIBZX
+       LXSIHZX
+       LXSSP
+       LXV
+       LXVB16X
+       LXVH8X
+       LXVL
+       LXVLL
+       LXVWSX
+       LXVX
+       MADDHD
+       MADDHDU
+       MADDLD
+       MCRXRX
+       MFVSRLD
+       MODSD
+       MODSW
+       MODUD
+       MODUW
+       MSGSYNC
+       MTVSRDD
+       MTVSRWS
+       PASTECC
+       SETB
+       SLBIEG
+       SLBSYNC
+       STDAT
+       STOP
+       STWAT
+       STXSD
+       STXSIBX
+       STXSIHX
+       STXSSP
+       STXV
+       STXVB16X
+       STXVH8X
+       STXVL
+       STXVLL
+       STXVX
+       VABSDUB
+       VABSDUH
+       VABSDUW
+       VBPERMD
+       VCLZLSBB
+       VCMPNEB
+       VCMPNEBCC
+       VCMPNEH
+       VCMPNEHCC
+       VCMPNEW
+       VCMPNEWCC
+       VCMPNEZB
+       VCMPNEZBCC
+       VCMPNEZH
+       VCMPNEZHCC
+       VCMPNEZW
+       VCMPNEZWCC
+       VCTZB
+       VCTZD
+       VCTZH
+       VCTZLSBB
+       VCTZW
+       VEXTRACTD
+       VEXTRACTUB
+       VEXTRACTUH
+       VEXTRACTUW
+       VEXTSB2D
+       VEXTSB2W
+       VEXTSH2D
+       VEXTSH2W
+       VEXTSW2D
+       VEXTUBLX
+       VEXTUBRX
+       VEXTUHLX
+       VEXTUHRX
+       VEXTUWLX
+       VEXTUWRX
+       VINSERTB
+       VINSERTD
+       VINSERTH
+       VINSERTW
+       VMUL10CUQ
+       VMUL10ECUQ
+       VMUL10EUQ
+       VMUL10UQ
+       VNEGD
+       VNEGW
+       VPERMR
+       VPRTYBD
+       VPRTYBQ
+       VPRTYBW
+       VRLDMI
+       VRLDNM
+       VRLWMI
+       VRLWNM
+       VSLV
+       VSRV
+       WAIT
+       XSABSQP
+       XSADDQP
+       XSADDQPO
+       XSCMPEQDP
+       XSCMPEXPDP
+       XSCMPEXPQP
+       XSCMPGEDP
+       XSCMPGTDP
+       XSCMPOQP
+       XSCMPUQP
+       XSCPSGNQP
+       XSCVDPHP
+       XSCVDPQP
+       XSCVHPDP
+       XSCVQPDP
+       XSCVQPDPO
+       XSCVQPSDZ
+       XSCVQPSWZ
+       XSCVQPUDZ
+       XSCVQPUWZ
+       XSCVSDQP
+       XSCVUDQP
+       XSDIVQP
+       XSDIVQPO
+       XSIEXPDP
+       XSIEXPQP
+       XSMADDQP
+       XSMADDQPO
+       XSMAXCDP
+       XSMAXJDP
+       XSMINCDP
+       XSMINJDP
+       XSMSUBQP
+       XSMSUBQPO
+       XSMULQP
+       XSMULQPO
+       XSNABSQP
+       XSNEGQP
+       XSNMADDQP
+       XSNMADDQPO
+       XSNMSUBQP
+       XSNMSUBQPO
+       XSRQPI
+       XSRQPIX
+       XSRQPXP
+       XSSQRTQP
+       XSSQRTQPO
+       XSSUBQP
+       XSSUBQPO
+       XSTSTDCDP
+       XSTSTDCQP
+       XSTSTDCSP
+       XSXEXPDP
+       XSXEXPQP
+       XSXSIGDP
+       XSXSIGQP
+       XVCVHPSP
+       XVCVSPHP
+       XVIEXPDP
+       XVIEXPSP
+       XVTSTDCDP
+       XVTSTDCSP
+       XVXEXPDP
+       XVXEXPSP
+       XVXSIGDP
+       XVXSIGSP
+       XXBRD
+       XXBRH
+       XXBRQ
+       XXBRW
+       XXEXTRACTUW
+       XXINSERTW
+       XXPERM
+       XXPERMR
+       XXSPLTIB
+       BCDADDCC
+       BCDSUBCC
        BCTAR
        BCTARL
-       CRAND
-       CROR
-       CRNAND
-       CRXOR
-       CRNOR
-       CRANDC
-       MCRF
-       CREQV
-       CRORC
-       SC
        CLRBHRB
+       FMRGEW
+       FMRGOW
+       ICBT
+       LQARX
+       LXSIWAX
+       LXSIWZX
+       LXSSPX
        MFBHRBE
-       LBZ
-       LBZU
-       LBZX
-       LBZUX
-       LHZ
-       LHZU
-       LHZX
-       LHZUX
-       LHA
-       LHAU
-       LHAX
-       LHAUX
-       LWZ
-       LWZU
-       LWZX
-       LWZUX
-       LWA
-       LWAX
-       LWAUX
-       LD
-       LDU
-       LDX
-       LDUX
-       STB
-       STBU
-       STBX
-       STBUX
-       STH
-       STHU
-       STHX
-       STHUX
-       STW
-       STWU
-       STWX
-       STWUX
-       STD
-       STDU
-       STDX
-       STDUX
-       LQ
-       STQ
-       LHBRX
-       LWBRX
-       STHBRX
-       STWBRX
-       LDBRX
-       STDBRX
-       LMW
-       STMW
-       LSWI
-       LSWX
-       STSWI
-       STSWX
-       LI
-       ADDI
-       LIS
-       ADDIS
-       ADD
-       ADDCC
-       ADDO
-       ADDOCC
-       ADDIC
-       SUBF
-       SUBFCC
-       SUBFO
-       SUBFOCC
-       ADDICCC
-       SUBFIC
-       ADDC
-       ADDCCC
-       ADDCO
-       ADDCOCC
-       SUBFC
-       SUBFCCC
-       SUBFCO
-       SUBFCOCC
-       ADDE
-       ADDECC
-       ADDEO
-       ADDEOCC
-       ADDME
-       ADDMECC
-       ADDMEO
-       ADDMEOCC
-       SUBFE
-       SUBFECC
-       SUBFEO
-       SUBFEOCC
-       SUBFME
-       SUBFMECC
-       SUBFMEO
-       SUBFMEOCC
-       ADDZE
-       ADDZECC
-       ADDZEO
-       ADDZEOCC
-       SUBFZE
-       SUBFZECC
-       SUBFZEO
-       SUBFZEOCC
-       NEG
-       NEGCC
-       NEGO
-       NEGOCC
-       MULLI
-       MULLW
-       MULLWCC
-       MULLWO
-       MULLWOCC
-       MULHW
-       MULHWCC
-       MULHWU
-       MULHWUCC
-       DIVW
-       DIVWCC
-       DIVWO
-       DIVWOCC
-       DIVWU
-       DIVWUCC
-       DIVWUO
-       DIVWUOCC
-       DIVWE
-       DIVWECC
-       DIVWEO
-       DIVWEOCC
-       DIVWEU
-       DIVWEUCC
-       DIVWEUO
-       DIVWEUOCC
-       MULLD
-       MULLDCC
-       MULLDO
-       MULLDOCC
-       MULHDU
-       MULHDUCC
-       MULHD
-       MULHDCC
-       DIVD
-       DIVDCC
-       DIVDO
-       DIVDOCC
-       DIVDU
-       DIVDUCC
-       DIVDUO
-       DIVDUOCC
-       DIVDE
-       DIVDECC
-       DIVDEO
-       DIVDEOCC
-       DIVDEU
-       DIVDEUCC
-       DIVDEUO
-       DIVDEUOCC
-       MODSD
-       MODUD
-       MODSW
-       MODUW
-       CMPWI
-       CMPDI
-       CMPW
-       CMPD
-       CMPLWI
-       CMPLDI
-       CMPLW
-       CMPLD
-       TWI
-       TW
-       TDI
-       ISEL
-       TD
-       ANDICC
-       ANDISCC
-       ORI
-       ORIS
-       XORI
-       XORIS
-       AND
-       ANDCC
-       XOR
-       XORCC
-       NAND
-       NANDCC
-       OR
-       ORCC
-       NOR
-       NORCC
-       ANDC
-       ANDCCC
-       EXTSB
-       EXTSBCC
-       EQV
-       EQVCC
-       ORC
-       ORCCC
-       EXTSH
-       EXTSHCC
-       CMPB
-       POPCNTB
-       POPCNTW
-       PRTYD
-       PRTYW
-       EXTSW
-       EXTSWCC
-       CNTLZD
-       CNTLZDCC
-       POPCNTD
-       BPERMD
-       RLWINM
-       RLWINMCC
-       RLWNM
-       RLWNMCC
-       RLWIMI
-       RLWIMICC
-       RLDICL
-       RLDICLCC
-       RLDICR
-       RLDICRCC
-       RLDIC
-       RLDICCC
-       RLDCL
-       RLDCLCC
-       RLDCR
-       RLDCRCC
-       RLDIMI
-       RLDIMICC
-       SLW
-       SLWCC
-       SRW
-       SRWCC
-       SRAWI
-       SRAWICC
-       SRAW
-       SRAWCC
-       SLD
-       SLDCC
-       SRD
-       SRDCC
-       SRADI
-       SRADICC
-       SRAD
-       SRADCC
-       CDTBCD
-       CBCDTD
-       ADDG6S
-       MTSPR
-       MFSPR
-       MTCRF
-       MFCR
-       MTSLE
        MFVSRD
        MFVSRWZ
+       MSGCLR
+       MSGCLRP
+       MSGSND
+       MSGSNDP
        MTVSRD
        MTVSRWA
        MTVSRWZ
-       MTOCRF
-       MFOCRF
-       MCRXR
-       MTDCRUX
-       MFDCRUX
-       LFS
-       LFSU
-       LFSX
-       LFSUX
-       LFD
-       LFDU
-       LFDX
-       LFDUX
-       LFIWAX
+       RFEBB
+       STQCXCC
+       STXSIWX
+       STXSSPX
+       VADDCUQ
+       VADDECUQ
+       VADDEUQM
+       VADDUDM
+       VADDUQM
+       VBPERMQ
+       VCIPHER
+       VCIPHERLAST
+       VCLZB
+       VCLZD
+       VCLZH
+       VCLZW
+       VCMPEQUD
+       VCMPEQUDCC
+       VCMPGTSD
+       VCMPGTSDCC
+       VCMPGTUD
+       VCMPGTUDCC
+       VEQV
+       VGBBD
+       VMAXSD
+       VMAXUD
+       VMINSD
+       VMINUD
+       VMRGEW
+       VMRGOW
+       VMULESW
+       VMULEUW
+       VMULOSW
+       VMULOUW
+       VMULUWM
+       VNAND
+       VNCIPHER
+       VNCIPHERLAST
+       VORC
+       VPERMXOR
+       VPKSDSS
+       VPKSDUS
+       VPKUDUM
+       VPKUDUS
+       VPMSUMB
+       VPMSUMD
+       VPMSUMH
+       VPMSUMW
+       VPOPCNTB
+       VPOPCNTD
+       VPOPCNTH
+       VPOPCNTW
+       VRLD
+       VSBOX
+       VSHASIGMAD
+       VSHASIGMAW
+       VSLD
+       VSRAD
+       VSRD
+       VSUBCUQ
+       VSUBECUQ
+       VSUBEUQM
+       VSUBUDM
+       VSUBUQM
+       VUPKHSW
+       VUPKLSW
+       XSADDSP
+       XSCVDPSPN
+       XSCVSPDPN
+       XSCVSXDSP
+       XSCVUXDSP
+       XSDIVSP
+       XSMADDASP
+       XSMADDMSP
+       XSMSUBASP
+       XSMSUBMSP
+       XSMULSP
+       XSNMADDASP
+       XSNMADDMSP
+       XSNMSUBASP
+       XSNMSUBMSP
+       XSRESP
+       XSRSP
+       XSRSQRTESP
+       XSSQRTSP
+       XSSUBSP
+       XXLEQV
+       XXLNAND
+       XXLORC
+       ADDG6S
+       BPERMD
+       CBCDTD
+       CDTBCD
+       DCFFIX
+       DCFFIXCC
+       DIVDE
+       DIVDECC
+       DIVDEO
+       DIVDEOCC
+       DIVDEU
+       DIVDEUCC
+       DIVDEUO
+       DIVDEUOCC
+       DIVWE
+       DIVWECC
+       DIVWEO
+       DIVWEOCC
+       DIVWEU
+       DIVWEUCC
+       DIVWEUO
+       DIVWEUOCC
+       FCFIDS
+       FCFIDSCC
+       FCFIDU
+       FCFIDUCC
+       FCFIDUS
+       FCFIDUSCC
+       FCTIDU
+       FCTIDUCC
+       FCTIDUZ
+       FCTIDUZCC
+       FCTIWU
+       FCTIWUCC
+       FCTIWUZ
+       FCTIWUZCC
+       FTDIV
+       FTSQRT
+       LBARX
+       LDBRX
        LFIWZX
-       STFS
-       STFSU
-       STFSX
-       STFSUX
-       STFD
-       STFDU
-       STFDX
-       STFDUX
-       STFIWX
-       LFDP
-       LFDPX
-       STFDP
-       STFDPX
-       FMR
-       FMRCC
-       FABS
-       FABSCC
-       FNABS
-       FNABSCC
-       FNEG
-       FNEGCC
-       FCPSGN
-       FCPSGNCC
-       FMRGEW
-       FMRGOW
-       FADD
-       FADDCC
-       FADDS
-       FADDSCC
-       FSUB
-       FSUBCC
-       FSUBS
-       FSUBSCC
-       FMUL
-       FMULCC
-       FMULS
-       FMULSCC
-       FDIV
-       FDIVCC
-       FDIVS
-       FDIVSCC
-       FSQRT
-       FSQRTCC
-       FSQRTS
-       FSQRTSCC
-       FRE
-       FRECC
-       FRES
-       FRESCC
-       FRSQRTE
-       FRSQRTECC
-       FRSQRTES
-       FRSQRTESCC
-       FTDIV
-       FTSQRT
-       FMADD
-       FMADDCC
-       FMADDS
-       FMADDSCC
-       FMSUB
-       FMSUBCC
-       FMSUBS
-       FMSUBSCC
-       FNMADD
-       FNMADDCC
-       FNMADDS
-       FNMADDSCC
-       FNMSUB
-       FNMSUBCC
-       FNMSUBS
-       FNMSUBSCC
-       FRSP
-       FRSPCC
-       FCTID
-       FCTIDCC
-       FCTIDZ
-       FCTIDZCC
-       FCTIDU
-       FCTIDUCC
-       FCTIDUZ
-       FCTIDUZCC
-       FCTIW
-       FCTIWCC
-       FCTIWZ
-       FCTIWZCC
-       FCTIWU
-       FCTIWUCC
-       FCTIWUZ
-       FCTIWUZCC
-       FCFID
-       FCFIDCC
-       FCFIDU
-       FCFIDUCC
-       FCFIDS
-       FCFIDSCC
-       FCFIDUS
-       FCFIDUSCC
-       FRIN
-       FRINCC
-       FRIZ
-       FRIZCC
-       FRIP
-       FRIPCC
-       FRIM
-       FRIMCC
-       FCMPU
-       FCMPO
-       FSEL
-       FSELCC
-       MFFS
-       MFFSCC
-       MCRFS
-       MTFSFI
-       MTFSFICC
-       MTFSF
-       MTFSFCC
-       MTFSB0
-       MTFSB0CC
-       MTFSB1
-       MTFSB1CC
-       LVEBX
-       LVEHX
-       LVEWX
-       LVX
-       LVXL
-       STVEBX
-       STVEHX
-       STVEWX
-       STVX
-       STVXL
-       LVSL
-       LVSR
-       VPKPX
-       VPKSDSS
-       VPKSDUS
-       VPKSHSS
-       VPKSHUS
-       VPKSWSS
-       VPKSWUS
-       VPKUDUM
-       VPKUDUS
-       VPKUHUM
-       VPKUHUS
-       VPKUWUM
-       VPKUWUS
-       VUPKHPX
-       VUPKLPX
-       VUPKHSB
-       VUPKHSH
-       VUPKHSW
-       VUPKLSB
-       VUPKLSH
-       VUPKLSW
-       VMRGHB
-       VMRGHH
-       VMRGLB
-       VMRGLH
-       VMRGHW
-       VMRGLW
-       VMRGEW
-       VMRGOW
-       VSPLTB
-       VSPLTH
-       VSPLTW
-       VSPLTISB
-       VSPLTISH
-       VSPLTISW
-       VPERM
-       VPERMR
-       VSEL
-       VSL
-       VSLDOI
-       VSLO
-       VSR
-       VSRO
-       VADDCUW
-       VADDSBS
-       VADDSHS
-       VADDSWS
-       VADDUBM
-       VADDUDM
-       VADDUHM
-       VADDUWM
-       VADDUBS
-       VADDUHS
-       VADDUWS
-       VADDUQM
-       VADDEUQM
-       VADDCUQ
-       VADDECUQ
-       VSUBCUW
-       VSUBSBS
-       VSUBSHS
-       VSUBSWS
-       VSUBUBM
-       VSUBUDM
-       VSUBUHM
-       VSUBUWM
-       VSUBUBS
-       VSUBUHS
-       VSUBUWS
-       VSUBUQM
-       VSUBEUQM
-       VSUBCUQ
-       VSUBECUQ
-       VMULESB
-       VMULEUB
-       VMULOSB
-       VMULOUB
-       VMULESH
-       VMULEUH
-       VMULOSH
-       VMULOUH
-       VMULESW
-       VMULEUW
-       VMULOSW
-       VMULOUW
-       VMULUWM
-       VMHADDSHS
-       VMHRADDSHS
-       VMLADDUHM
-       VMSUMUBM
-       VMSUMMBM
-       VMSUMSHM
-       VMSUMSHS
-       VMSUMUHM
-       VMSUMUHS
-       VMSUMUDM
-       VSUMSWS
-       VSUM2SWS
-       VSUM4SBS
-       VSUM4SHS
-       VSUM4UBS
-       VAVGSB
-       VAVGSH
-       VAVGSW
-       VAVGUB
-       VAVGUW
-       VAVGUH
-       VMAXSB
-       VMAXSD
-       VMAXUB
-       VMAXUD
-       VMAXSH
-       VMAXSW
-       VMAXUH
-       VMAXUW
-       VMINSB
-       VMINSD
-       VMINUB
-       VMINUD
-       VMINSH
-       VMINSW
-       VMINUH
-       VMINUW
-       VCMPEQUB
-       VCMPEQUBCC
-       VCMPEQUH
-       VCMPEQUHCC
-       VCMPEQUW
-       VCMPEQUWCC
-       VCMPEQUD
-       VCMPEQUDCC
-       VCMPNEB
-       VCMPNEBCC
-       VCMPNEZB
-       VCMPNEZBCC
-       VCMPNEH
-       VCMPNEHCC
-       VCMPNEZH
-       VCMPNEZHCC
-       VCMPNEW
-       VCMPNEWCC
-       VCMPNEZW
-       VCMPNEZWCC
-       VCMPGTSB
-       VCMPGTSBCC
-       VCMPGTSD
-       VCMPGTSDCC
-       VCMPGTSH
-       VCMPGTSHCC
-       VCMPGTSW
-       VCMPGTSWCC
-       VCMPGTUB
-       VCMPGTUBCC
-       VCMPGTUD
-       VCMPGTUDCC
-       VCMPGTUH
-       VCMPGTUHCC
-       VCMPGTUW
-       VCMPGTUWCC
-       VAND
-       VANDC
-       VEQV
-       VNAND
-       VORC
-       VNOR
-       VOR
-       VXOR
-       VRLB
-       VRLH
-       VRLW
-       VRLD
-       VSLB
-       VSLH
-       VSLW
-       VSLD
-       VSRB
-       VSRH
-       VSRW
-       VSRD
-       VSRAB
-       VSRAH
-       VSRAW
-       VSRAD
-       VADDFP
-       VSUBFP
-       VMADDFP
-       VNMSUBFP
-       VMAXFP
-       VMINFP
-       VCTSXS
-       VCTUXS
-       VCFSX
-       VCFUX
-       VRFIM
-       VRFIN
-       VRFIP
-       VRFIZ
-       VCMPBFP
-       VCMPBFPCC
-       VCMPEQFP
-       VCMPEQFPCC
-       VCMPGEFP
-       VCMPGEFPCC
-       VCMPGTFP
-       VCMPGTFPCC
-       VEXPTEFP
-       VLOGEFP
-       VREFP
-       VRSQRTEFP
-       VCIPHER
-       VCIPHERLAST
-       VNCIPHER
-       VNCIPHERLAST
-       VSBOX
-       VSHASIGMAD
-       VSHASIGMAW
-       VPMSUMB
-       VPMSUMD
-       VPMSUMH
-       VPMSUMW
-       VPERMXOR
-       VGBBD
-       VCLZB
-       VCLZH
-       VCLZW
-       VCLZD
-       VPOPCNTB
-       VPOPCNTD
-       VPOPCNTH
-       VPOPCNTW
-       VBPERMQ
-       VBPERMD
-       BCDADDCC
-       BCDSUBCC
-       MTVSCR
-       MFVSCR
-       DADD
-       DADDCC
-       DSUB
-       DSUBCC
-       DMUL
-       DMULCC
-       DDIV
-       DDIVCC
-       DCMPU
-       DCMPO
-       DTSTDC
-       DTSTDG
-       DTSTEX
-       DTSTSF
-       DQUAI
-       DQUAICC
-       DQUA
-       DQUACC
-       DRRND
-       DRRNDCC
-       DRINTX
-       DRINTXCC
-       DRINTN
-       DRINTNCC
-       DCTDP
-       DCTDPCC
-       DCTQPQ
-       DCTQPQCC
-       DRSP
-       DRSPCC
-       DRDPQ
-       DRDPQCC
-       DCFFIX
-       DCFFIXCC
-       DCFFIXQ
-       DCFFIXQCC
-       DCTFIX
-       DCTFIXCC
-       DDEDPD
-       DDEDPDCC
-       DENBCD
-       DENBCDCC
-       DXEX
-       DXEXCC
-       DIEX
-       DIEXCC
-       DSCLI
-       DSCLICC
-       DSCRI
-       DSCRICC
+       LHARX
        LXSDX
-       LXSIWAX
-       LXSIWZX
-       LXSSPX
        LXVD2X
        LXVDSX
        LXVW4X
-       LXVH8X
-       LXVB16X
-       LXV
-       LXVL
-       LXVLL
-       LXVX
+       POPCNTD
+       POPCNTW
+       STBCXCC
+       STDBRX
+       STHCXCC
        STXSDX
-       STXSIWX
-       STXSSPX
        STXVD2X
        STXVW4X
-       STXVH8X
-       STXVB16X
-       STXV
-       STXVL
-       STXVLL
-       STXVX
        XSABSDP
        XSADDDP
-       XSADDSP
        XSCMPODP
        XSCMPUDP
        XSCPSGNDP
        XSCVDPSP
-       XSCVDPSPN
        XSCVDPSXDS
        XSCVDPSXWS
        XSCVDPUXDS
        XSCVDPUXWS
        XSCVSPDP
-       XSCVSPDPN
        XSCVSXDDP
-       XSCVSXDSP
        XSCVUXDDP
-       XSCVUXDSP
        XSDIVDP
-       XSDIVSP
        XSMADDADP
-       XSMADDASP
+       XSMADDMDP
        XSMAXDP
        XSMINDP
        XSMSUBADP
-       XSMSUBASP
+       XSMSUBMDP
        XSMULDP
-       XSMULSP
        XSNABSDP
        XSNEGDP
        XSNMADDADP
-       XSNMADDASP
+       XSNMADDMDP
        XSNMSUBADP
-       XSNMSUBASP
+       XSNMSUBMDP
        XSRDPI
        XSRDPIC
        XSRDPIM
        XSRDPIP
        XSRDPIZ
        XSREDP
-       XSRESP
-       XSRSP
        XSRSQRTEDP
-       XSRSQRTESP
        XSSQRTDP
-       XSSQRTSP
        XSSUBDP
-       XSSUBSP
        XSTDIVDP
        XSTSQRTDP
        XVABSDP
@@ -834,12 +706,16 @@ const (
        XVDIVSP
        XVMADDADP
        XVMADDASP
+       XVMADDMDP
+       XVMADDMSP
        XVMAXDP
        XVMAXSP
        XVMINDP
        XVMINSP
        XVMSUBADP
        XVMSUBASP
+       XVMSUBMDP
+       XVMSUBMSP
        XVMULDP
        XVMULSP
        XVNABSDP
@@ -848,8 +724,12 @@ const (
        XVNEGSP
        XVNMADDADP
        XVNMADDASP
+       XVNMADDMDP
+       XVNMADDMSP
        XVNMSUBADP
        XVNMSUBASP
+       XVNMSUBMDP
+       XVNMSUBMSP
        XVRDPI
        XVRDPIC
        XVRDPIM
@@ -874,4763 +754,5019 @@ const (
        XVTSQRTSP
        XXLAND
        XXLANDC
-       XXLEQV
-       XXLNAND
-       XXLORC
        XXLNOR
        XXLOR
        XXLXOR
        XXMRGHW
        XXMRGLW
        XXPERMDI
-       XXPERM
        XXSEL
        XXSLDWI
        XXSPLTW
-       XXBRD
-       XXBRW
-       XXBRH
-       BRINC
-       EVABS
-       EVADDIW
-       EVADDSMIAAW
-       EVADDSSIAAW
-       EVADDUMIAAW
-       EVADDUSIAAW
-       EVADDW
-       EVAND
-       EVCMPEQ
-       EVANDC
-       EVCMPGTS
-       EVCMPGTU
-       EVCMPLTU
-       EVCMPLTS
-       EVCNTLSW
-       EVCNTLZW
-       EVDIVWS
-       EVDIVWU
-       EVEQV
-       EVEXTSB
-       EVEXTSH
-       EVLDD
-       EVLDH
-       EVLDDX
-       EVLDHX
-       EVLDW
-       EVLHHESPLAT
-       EVLDWX
-       EVLHHESPLATX
-       EVLHHOSSPLAT
-       EVLHHOUSPLAT
-       EVLHHOSSPLATX
-       EVLHHOUSPLATX
-       EVLWHE
-       EVLWHOS
-       EVLWHEX
-       EVLWHOSX
-       EVLWHOU
-       EVLWHSPLAT
-       EVLWHOUX
-       EVLWHSPLATX
-       EVLWWSPLAT
-       EVMERGEHI
-       EVLWWSPLATX
-       EVMERGELO
-       EVMERGEHILO
-       EVMHEGSMFAA
-       EVMERGELOHI
-       EVMHEGSMFAN
-       EVMHEGSMIAA
-       EVMHEGUMIAA
-       EVMHEGSMIAN
-       EVMHEGUMIAN
-       EVMHESMF
-       EVMHESMFAAW
-       EVMHESMFA
-       EVMHESMFANW
-       EVMHESMI
-       EVMHESMIAAW
-       EVMHESMIA
-       EVMHESMIANW
-       EVMHESSF
-       EVMHESSFA
-       EVMHESSFAAW
-       EVMHESSFANW
-       EVMHESSIAAW
-       EVMHESSIANW
-       EVMHEUMI
-       EVMHEUMIAAW
-       EVMHEUMIA
-       EVMHEUMIANW
-       EVMHEUSIAAW
-       EVMHEUSIANW
-       EVMHOGSMFAA
-       EVMHOGSMIAA
-       EVMHOGSMFAN
-       EVMHOGSMIAN
-       EVMHOGUMIAA
-       EVMHOSMF
-       EVMHOGUMIAN
-       EVMHOSMFA
-       EVMHOSMFAAW
-       EVMHOSMI
-       EVMHOSMFANW
-       EVMHOSMIA
-       EVMHOSMIAAW
-       EVMHOSMIANW
-       EVMHOSSF
-       EVMHOSSFA
-       EVMHOSSFAAW
-       EVMHOSSFANW
-       EVMHOSSIAAW
-       EVMHOUMI
-       EVMHOSSIANW
-       EVMHOUMIA
-       EVMHOUMIAAW
-       EVMHOUSIAAW
-       EVMHOUMIANW
-       EVMHOUSIANW
-       EVMRA
-       EVMWHSMF
-       EVMWHSMI
-       EVMWHSMFA
-       EVMWHSMIA
-       EVMWHSSF
-       EVMWHUMI
-       EVMWHSSFA
-       EVMWHUMIA
-       EVMWLSMIAAW
-       EVMWLSSIAAW
-       EVMWLSMIANW
-       EVMWLSSIANW
-       EVMWLUMI
-       EVMWLUMIAAW
-       EVMWLUMIA
-       EVMWLUMIANW
-       EVMWLUSIAAW
-       EVMWSMF
-       EVMWLUSIANW
-       EVMWSMFA
-       EVMWSMFAA
-       EVMWSMI
-       EVMWSMIAA
-       EVMWSMFAN
-       EVMWSMIA
-       EVMWSMIAN
-       EVMWSSF
-       EVMWSSFA
-       EVMWSSFAA
-       EVMWUMI
-       EVMWSSFAN
-       EVMWUMIA
-       EVMWUMIAA
-       EVNAND
-       EVMWUMIAN
-       EVNEG
-       EVNOR
-       EVORC
-       EVOR
-       EVRLW
-       EVRLWI
-       EVSEL
-       EVRNDW
-       EVSLW
-       EVSPLATFI
-       EVSRWIS
-       EVSLWI
-       EVSPLATI
-       EVSRWIU
-       EVSRWS
-       EVSTDD
-       EVSRWU
-       EVSTDDX
-       EVSTDH
-       EVSTDW
-       EVSTDHX
-       EVSTDWX
-       EVSTWHE
-       EVSTWHO
-       EVSTWWE
-       EVSTWHEX
-       EVSTWHOX
-       EVSTWWEX
-       EVSTWWO
-       EVSUBFSMIAAW
-       EVSTWWOX
-       EVSUBFSSIAAW
-       EVSUBFUMIAAW
-       EVSUBFUSIAAW
-       EVSUBFW
-       EVSUBIFW
-       EVXOR
-       EVFSABS
-       EVFSNABS
-       EVFSNEG
-       EVFSADD
-       EVFSMUL
-       EVFSSUB
-       EVFSDIV
-       EVFSCMPGT
-       EVFSCMPLT
-       EVFSCMPEQ
-       EVFSTSTGT
-       EVFSTSTLT
-       EVFSTSTEQ
-       EVFSCFSI
-       EVFSCFSF
-       EVFSCFUI
-       EVFSCFUF
-       EVFSCTSI
-       EVFSCTUI
-       EVFSCTSIZ
-       EVFSCTUIZ
-       EVFSCTSF
-       EVFSCTUF
-       EFSABS
-       EFSNEG
-       EFSNABS
-       EFSADD
-       EFSMUL
-       EFSSUB
-       EFSDIV
-       EFSCMPGT
-       EFSCMPLT
-       EFSCMPEQ
-       EFSTSTGT
-       EFSTSTLT
-       EFSTSTEQ
-       EFSCFSI
-       EFSCFSF
-       EFSCTSI
-       EFSCFUI
-       EFSCFUF
-       EFSCTUI
-       EFSCTSIZ
-       EFSCTSF
-       EFSCTUIZ
-       EFSCTUF
-       EFDABS
-       EFDNEG
-       EFDNABS
-       EFDADD
-       EFDMUL
-       EFDSUB
-       EFDDIV
-       EFDCMPGT
-       EFDCMPEQ
-       EFDCMPLT
-       EFDTSTGT
-       EFDTSTLT
-       EFDCFSI
-       EFDTSTEQ
-       EFDCFUI
-       EFDCFSID
-       EFDCFSF
-       EFDCFUF
-       EFDCFUID
-       EFDCTSI
-       EFDCTUI
-       EFDCTSIDZ
-       EFDCTUIDZ
-       EFDCTSIZ
-       EFDCTSF
-       EFDCTUF
-       EFDCTUIZ
-       EFDCFS
-       EFSCFD
-       DLMZB
-       DLMZBCC
-       MACCHW
-       MACCHWCC
-       MACCHWO
-       MACCHWOCC
-       MACCHWS
-       MACCHWSCC
-       MACCHWSO
-       MACCHWSOCC
-       MACCHWU
-       MACCHWUCC
-       MACCHWUO
-       MACCHWUOCC
-       MACCHWSU
-       MACCHWSUCC
-       MACCHWSUO
-       MACCHWSUOCC
-       MACHHW
-       MACHHWCC
-       MACHHWO
-       MACHHWOCC
-       MACHHWS
-       MACHHWSCC
-       MACHHWSO
-       MACHHWSOCC
-       MACHHWU
-       MACHHWUCC
-       MACHHWUO
-       MACHHWUOCC
-       MACHHWSU
-       MACHHWSUCC
-       MACHHWSUO
-       MACHHWSUOCC
-       MACLHW
-       MACLHWCC
-       MACLHWO
-       MACLHWOCC
-       MACLHWS
-       MACLHWSCC
-       MACLHWSO
-       MACLHWSOCC
-       MACLHWU
-       MACLHWUCC
-       MACLHWUO
-       MACLHWUOCC
-       MULCHW
-       MULCHWCC
-       MACLHWSU
-       MACLHWSUCC
-       MACLHWSUO
-       MACLHWSUOCC
-       MULCHWU
-       MULCHWUCC
-       MULHHW
-       MULHHWCC
-       MULLHW
-       MULLHWCC
-       MULHHWU
-       MULHHWUCC
-       MULLHWU
-       MULLHWUCC
-       NMACCHW
-       NMACCHWCC
-       NMACCHWO
-       NMACCHWOCC
-       NMACCHWS
-       NMACCHWSCC
-       NMACCHWSO
-       NMACCHWSOCC
-       NMACHHW
-       NMACHHWCC
-       NMACHHWO
-       NMACHHWOCC
-       NMACHHWS
-       NMACHHWSCC
-       NMACHHWSO
-       NMACHHWSOCC
-       NMACLHW
-       NMACLHWCC
-       NMACLHWO
-       NMACLHWOCC
-       NMACLHWS
-       NMACLHWSCC
-       NMACLHWSO
-       NMACLHWSOCC
-       ICBI
-       ICBT
-       DCBA
+       CMPB
+       DADD
+       DADDCC
+       DADDQ
+       DADDQCC
+       DCFFIXQ
+       DCFFIXQCC
+       DCMPO
+       DCMPOQ
+       DCMPU
+       DCMPUQ
+       DCTDP
+       DCTDPCC
+       DCTFIX
+       DCTFIXCC
+       DCTFIXQ
+       DCTFIXQCC
+       DCTQPQ
+       DCTQPQCC
+       DDEDPD
+       DDEDPDCC
+       DDEDPDQ
+       DDEDPDQCC
+       DDIV
+       DDIVCC
+       DDIVQ
+       DDIVQCC
+       DENBCD
+       DENBCDCC
+       DENBCDQ
+       DENBCDQCC
+       DIEX
+       DIEXCC
+       DIEXQCC
+       DIEXQ
+       DMUL
+       DMULCC
+       DMULQ
+       DMULQCC
+       DQUA
+       DQUACC
+       DQUAI
+       DQUAICC
+       DQUAIQ
+       DQUAIQCC
+       DQUAQ
+       DQUAQCC
+       DRDPQ
+       DRDPQCC
+       DRINTN
+       DRINTNCC
+       DRINTNQ
+       DRINTNQCC
+       DRINTX
+       DRINTXCC
+       DRINTXQ
+       DRINTXQCC
+       DRRND
+       DRRNDCC
+       DRRNDQ
+       DRRNDQCC
+       DRSP
+       DRSPCC
+       DSCLI
+       DSCLICC
+       DSCLIQ
+       DSCLIQCC
+       DSCRI
+       DSCRICC
+       DSCRIQ
+       DSCRIQCC
+       DSUB
+       DSUBCC
+       DSUBQ
+       DSUBQCC
+       DTSTDC
+       DTSTDCQ
+       DTSTDG
+       DTSTDGQ
+       DTSTEX
+       DTSTEXQ
+       DTSTSF
+       DTSTSFQ
+       DXEX
+       DXEXCC
+       DXEXQ
+       DXEXQCC
+       FCPSGN
+       FCPSGNCC
+       LBZCIX
+       LDCIX
+       LFDP
+       LFDPX
+       LFIWAX
+       LHZCIX
+       LWZCIX
+       PRTYD
+       PRTYW
+       SLBFEECC
+       STBCIX
+       STDCIX
+       STFDP
+       STFDPX
+       STHCIX
+       STWCIX
+       ISEL
+       LVEBX
+       LVEHX
+       LVEWX
+       LVSL
+       LVSR
+       LVX
+       LVXL
+       MFVSCR
+       MTVSCR
+       STVEBX
+       STVEHX
+       STVEWX
+       STVX
+       STVXL
+       TLBIEL
+       VADDCUW
+       VADDFP
+       VADDSBS
+       VADDSHS
+       VADDSWS
+       VADDUBM
+       VADDUBS
+       VADDUHM
+       VADDUHS
+       VADDUWM
+       VADDUWS
+       VAND
+       VANDC
+       VAVGSB
+       VAVGSH
+       VAVGSW
+       VAVGUB
+       VAVGUH
+       VAVGUW
+       VCFSX
+       VCFUX
+       VCMPBFP
+       VCMPBFPCC
+       VCMPEQFP
+       VCMPEQFPCC
+       VCMPEQUB
+       VCMPEQUBCC
+       VCMPEQUH
+       VCMPEQUHCC
+       VCMPEQUW
+       VCMPEQUWCC
+       VCMPGEFP
+       VCMPGEFPCC
+       VCMPGTFP
+       VCMPGTFPCC
+       VCMPGTSB
+       VCMPGTSBCC
+       VCMPGTSH
+       VCMPGTSHCC
+       VCMPGTSW
+       VCMPGTSWCC
+       VCMPGTUB
+       VCMPGTUBCC
+       VCMPGTUH
+       VCMPGTUHCC
+       VCMPGTUW
+       VCMPGTUWCC
+       VCTSXS
+       VCTUXS
+       VEXPTEFP
+       VLOGEFP
+       VMADDFP
+       VMAXFP
+       VMAXSB
+       VMAXSH
+       VMAXSW
+       VMAXUB
+       VMAXUH
+       VMAXUW
+       VMHADDSHS
+       VMHRADDSHS
+       VMINFP
+       VMINSB
+       VMINSH
+       VMINSW
+       VMINUB
+       VMINUH
+       VMINUW
+       VMLADDUHM
+       VMRGHB
+       VMRGHH
+       VMRGHW
+       VMRGLB
+       VMRGLH
+       VMRGLW
+       VMSUMMBM
+       VMSUMSHM
+       VMSUMSHS
+       VMSUMUBM
+       VMSUMUHM
+       VMSUMUHS
+       VMULESB
+       VMULESH
+       VMULEUB
+       VMULEUH
+       VMULOSB
+       VMULOSH
+       VMULOUB
+       VMULOUH
+       VNMSUBFP
+       VNOR
+       VOR
+       VPERM
+       VPKPX
+       VPKSHSS
+       VPKSHUS
+       VPKSWSS
+       VPKSWUS
+       VPKUHUM
+       VPKUHUS
+       VPKUWUM
+       VPKUWUS
+       VREFP
+       VRFIM
+       VRFIN
+       VRFIP
+       VRFIZ
+       VRLB
+       VRLH
+       VRLW
+       VRSQRTEFP
+       VSEL
+       VSL
+       VSLB
+       VSLDOI
+       VSLH
+       VSLO
+       VSLW
+       VSPLTB
+       VSPLTH
+       VSPLTISB
+       VSPLTISH
+       VSPLTISW
+       VSPLTW
+       VSR
+       VSRAB
+       VSRAH
+       VSRAW
+       VSRB
+       VSRH
+       VSRO
+       VSRW
+       VSUBCUW
+       VSUBFP
+       VSUBSBS
+       VSUBSHS
+       VSUBSWS
+       VSUBUBM
+       VSUBUBS
+       VSUBUHM
+       VSUBUHS
+       VSUBUWM
+       VSUBUWS
+       VSUM2SWS
+       VSUM4SBS
+       VSUM4SHS
+       VSUM4UBS
+       VSUMSWS
+       VUPKHPX
+       VUPKHSB
+       VUPKHSH
+       VUPKLPX
+       VUPKLSB
+       VUPKLSH
+       VXOR
+       FRE
+       FRECC
+       FRIM
+       FRIMCC
+       FRIN
+       FRINCC
+       FRIP
+       FRIPCC
+       FRIZ
+       FRIZCC
+       FRSQRTES
+       FRSQRTESCC
+       HRFID
+       POPCNTB
+       MFOCRF
+       MTOCRF
+       SLBMFEE
+       SLBMFEV
+       SLBMTE
+       RFSCV
+       SCV
+       LQ
+       STQ
+       CNTLZD
+       CNTLZDCC
+       DCBF
+       DCBST
        DCBT
        DCBTST
+       DIVD
+       DIVDCC
+       DIVDO
+       DIVDOCC
+       DIVDU
+       DIVDUCC
+       DIVDUO
+       DIVDUOCC
+       DIVW
+       DIVWCC
+       DIVWO
+       DIVWOCC
+       DIVWU
+       DIVWUCC
+       DIVWUO
+       DIVWUOCC
+       EIEIO
+       EXTSB
+       EXTSBCC
+       EXTSW
+       EXTSWCC
+       FADDS
+       FADDSCC
+       FCFID
+       FCFIDCC
+       FCTID
+       FCTIDCC
+       FCTIDZ
+       FCTIDZCC
+       FDIVS
+       FDIVSCC
+       FMADDS
+       FMADDSCC
+       FMSUBS
+       FMSUBSCC
+       FMULS
+       FMULSCC
+       FNMADDS
+       FNMADDSCC
+       FNMSUBS
+       FNMSUBSCC
+       FRES
+       FRESCC
+       FRSQRTE
+       FRSQRTECC
+       FSEL
+       FSELCC
+       FSQRTS
+       FSQRTSCC
+       FSUBS
+       FSUBSCC
+       ICBI
+       LD
+       LDARX
+       LDU
+       LDUX
+       LDX
+       LWA
+       LWARX
+       LWAUX
+       LWAX
+       MFTB
+       MTMSRD
+       MULHD
+       MULHDCC
+       MULHDU
+       MULHDUCC
+       MULHW
+       MULHWCC
+       MULHWU
+       MULHWUCC
+       MULLD
+       MULLDCC
+       MULLDO
+       MULLDOCC
+       RFID
+       RLDCL
+       RLDCLCC
+       RLDCR
+       RLDCRCC
+       RLDIC
+       RLDICCC
+       RLDICL
+       RLDICLCC
+       RLDICR
+       RLDICRCC
+       RLDIMI
+       RLDIMICC
+       SC
+       SLBIA
+       SLBIE
+       SLD
+       SLDCC
+       SRAD
+       SRADCC
+       SRADI
+       SRADICC
+       SRD
+       SRDCC
+       STD
+       STDCXCC
+       STDU
+       STDUX
+       STDX
+       STFIWX
+       STWCXCC
+       SUBF
+       SUBFCC
+       SUBFO
+       SUBFOCC
+       TD
+       TDI
+       TLBSYNC
+       FCTIW
+       FCTIWCC
+       FCTIWZ
+       FCTIWZCC
+       FSQRT
+       FSQRTCC
+       ADD
+       ADDCC
+       ADDO
+       ADDOCC
+       ADDC
+       ADDCCC
+       ADDCO
+       ADDCOCC
+       ADDE
+       ADDECC
+       ADDEO
+       ADDEOCC
+       LI
+       ADDI
+       ADDIC
+       ADDICCC
+       LIS
+       ADDIS
+       ADDME
+       ADDMECC
+       ADDMEO
+       ADDMEOCC
+       ADDZE
+       ADDZECC
+       ADDZEO
+       ADDZEOCC
+       AND
+       ANDCC
+       ANDC
+       ANDCCC
+       ANDICC
+       ANDISCC
+       B
+       BA
+       BL
+       BLA
+       BC
+       BCA
+       BCL
+       BCLA
+       BCCTR
+       BCCTRL
+       BCLR
+       BCLRL
+       CMPW
+       CMPD
+       CMP
+       CMPWI
+       CMPDI
+       CMPI
+       CMPLW
+       CMPLD
+       CMPL
+       CMPLWI
+       CMPLDI
+       CMPLI
+       CNTLZW
+       CNTLZWCC
+       CRAND
+       CRANDC
+       CREQV
+       CRNAND
+       CRNOR
+       CROR
+       CRORC
+       CRXOR
        DCBZ
-       DCBST
-       DCBF
+       EQV
+       EQVCC
+       EXTSH
+       EXTSHCC
+       FABS
+       FABSCC
+       FADD
+       FADDCC
+       FCMPO
+       FCMPU
+       FDIV
+       FDIVCC
+       FMADD
+       FMADDCC
+       FMR
+       FMRCC
+       FMSUB
+       FMSUBCC
+       FMUL
+       FMULCC
+       FNABS
+       FNABSCC
+       FNEG
+       FNEGCC
+       FNMADD
+       FNMADDCC
+       FNMSUB
+       FNMSUBCC
+       FRSP
+       FRSPCC
+       FSUB
+       FSUBCC
        ISYNC
-       LBARX
-       LHARX
-       LWARX
-       STBCXCC
-       STHCXCC
-       STWCXCC
-       LDARX
-       STDCXCC
-       LQARX
-       STQCXCC
-       SYNC
-       EIEIO
-       MBAR
-       WAIT
-       TBEGINCC
-       TENDCC
-       TABORTCC
-       TABORTWCCC
-       TABORTWCICC
-       TABORTDCCC
-       TABORTDCICC
-       TSRCC
-       TCHECK
-       MFTB
-       RFEBB
-       LBDX
-       LHDX
-       LWDX
-       LDDX
-       LFDDX
-       STBDX
-       STHDX
-       STWDX
-       STDDX
-       STFDDX
-       DSN
-       ECIWX
-       ECOWX
-       RFID
-       HRFID
-       DOZE
-       NAP
-       SLEEP
-       RVWINKLE
-       LBZCIX
-       LWZCIX
-       LHZCIX
-       LDCIX
-       STBCIX
-       STWCIX
-       STHCIX
-       STDCIX
-       TRECLAIMCC
-       TRECHKPTCC
-       MTMSR
-       MTMSRD
+       LBZ
+       LBZU
+       LBZUX
+       LBZX
+       LFD
+       LFDU
+       LFDUX
+       LFDX
+       LFS
+       LFSU
+       LFSUX
+       LFSX
+       LHA
+       LHAU
+       LHAUX
+       LHAX
+       LHBRX
+       LHZ
+       LHZU
+       LHZUX
+       LHZX
+       LMW
+       LSWI
+       LSWX
+       LWBRX
+       LWZ
+       LWZU
+       LWZUX
+       LWZX
+       MCRF
+       MCRFS
+       MFCR
+       MFFS
+       MFFSCC
        MFMSR
-       SLBIE
-       SLBIA
-       SLBMTE
-       SLBMFEV
-       SLBMFEE
-       SLBFEECC
-       MTSR
-       MTSRIN
-       MFSR
-       MFSRIN
+       MFSPR
+       MTCRF
+       MTFSB0
+       MTFSB0CC
+       MTFSB1
+       MTFSB1CC
+       MTFSF
+       MTFSFCC
+       MTFSFI
+       MTFSFICC
+       MTMSR
+       MTSPR
+       MULLI
+       MULLW
+       MULLWCC
+       MULLWO
+       MULLWOCC
+       NAND
+       NANDCC
+       NEG
+       NEGCC
+       NEGO
+       NEGOCC
+       NOR
+       NORCC
+       OR
+       ORCC
+       ORC
+       ORCCC
+       NOP
+       ORI
+       ORIS
+       RLWIMI
+       RLWIMICC
+       RLWINM
+       RLWINMCC
+       RLWNM
+       RLWNMCC
+       SLW
+       SLWCC
+       SRAW
+       SRAWCC
+       SRAWI
+       SRAWICC
+       SRW
+       SRWCC
+       STB
+       STBU
+       STBUX
+       STBX
+       STFD
+       STFDU
+       STFDUX
+       STFDX
+       STFS
+       STFSU
+       STFSUX
+       STFSX
+       STH
+       STHBRX
+       STHU
+       STHUX
+       STHX
+       STMW
+       STSWI
+       STSWX
+       STW
+       STWBRX
+       STWU
+       STWUX
+       STWX
+       SUBFC
+       SUBFCCC
+       SUBFCO
+       SUBFCOCC
+       SUBFE
+       SUBFECC
+       SUBFEO
+       SUBFEOCC
+       SUBFIC
+       SUBFME
+       SUBFMECC
+       SUBFMEO
+       SUBFMEOCC
+       SUBFZE
+       SUBFZECC
+       SUBFZEO
+       SUBFZEOCC
+       SYNC
        TLBIE
-       TLBIEL
-       TLBIA
-       TLBSYNC
-       MSGSND
-       MSGCLR
-       MSGSNDP
-       MSGCLRP
-       MTTMR
-       RFI
-       RFCI
-       RFDI
-       RFMCI
-       RFGI
-       EHPRIV
-       MTDCR
-       MTDCRX
-       MFDCR
-       MFDCRX
-       WRTEE
-       WRTEEI
-       LBEPX
-       LHEPX
-       LWEPX
-       LDEPX
-       STBEPX
-       STHEPX
-       STWEPX
-       STDEPX
-       DCBSTEP
-       DCBTEP
-       DCBFEP
-       DCBTSTEP
-       ICBIEP
-       DCBZEP
-       LFDEPX
-       STFDEPX
-       EVLDDEPX
-       EVSTDDEPX
-       LVEPX
-       LVEPXL
-       STVEPX
-       STVEPXL
-       DCBI
-       DCBLQCC
-       ICBLQCC
-       DCBTLS
-       DCBTSTLS
-       ICBTLS
-       ICBLC
-       DCBLC
-       TLBIVAX
-       TLBILX
-       TLBSX
-       TLBSRXCC
-       TLBRE
-       TLBWE
-       DNH
-       DCI
-       ICI
-       DCREAD
-       ICREAD
-       MFPMR
-       MTPMR
-       ADDEX
-       DARN
-       MADDHD
-       MADDHDU
-       MADDLD
-       CMPRB
-       CMPEQB
-       EXTSWSLI
-       EXTSWSLICC
-       MFVSRLD
-       MTVSRDD
-       MTVSRWS
-       MCRXRX
-       COPY
-       PASTECC
+       TW
+       TWI
+       XOR
+       XORCC
+       XORI
+       XORIS
 )
 
 var opstr = [...]string{
-       CNTLZW:        "cntlzw",
-       CNTLZWCC:      "cntlzw.",
-       B:             "b",
-       BA:            "ba",
-       BL:            "bl",
-       BLA:           "bla",
-       BC:            "bc",
-       BCA:           "bca",
-       BCL:           "bcl",
-       BCLA:          "bcla",
-       BCLR:          "bclr",
-       BCLRL:         "bclrl",
-       BCCTR:         "bcctr",
-       BCCTRL:        "bcctrl",
-       BCTAR:         "bctar",
-       BCTARL:        "bctarl",
-       CRAND:         "crand",
-       CROR:          "cror",
-       CRNAND:        "crnand",
-       CRXOR:         "crxor",
-       CRNOR:         "crnor",
-       CRANDC:        "crandc",
-       MCRF:          "mcrf",
-       CREQV:         "creqv",
-       CRORC:         "crorc",
-       SC:            "sc",
-       CLRBHRB:       "clrbhrb",
-       MFBHRBE:       "mfbhrbe",
-       LBZ:           "lbz",
-       LBZU:          "lbzu",
-       LBZX:          "lbzx",
-       LBZUX:         "lbzux",
-       LHZ:           "lhz",
-       LHZU:          "lhzu",
-       LHZX:          "lhzx",
-       LHZUX:         "lhzux",
-       LHA:           "lha",
-       LHAU:          "lhau",
-       LHAX:          "lhax",
-       LHAUX:         "lhaux",
-       LWZ:           "lwz",
-       LWZU:          "lwzu",
-       LWZX:          "lwzx",
-       LWZUX:         "lwzux",
-       LWA:           "lwa",
-       LWAX:          "lwax",
-       LWAUX:         "lwaux",
-       LD:            "ld",
-       LDU:           "ldu",
-       LDX:           "ldx",
-       LDUX:          "ldux",
-       STB:           "stb",
-       STBU:          "stbu",
-       STBX:          "stbx",
-       STBUX:         "stbux",
-       STH:           "sth",
-       STHU:          "sthu",
-       STHX:          "sthx",
-       STHUX:         "sthux",
-       STW:           "stw",
-       STWU:          "stwu",
-       STWX:          "stwx",
-       STWUX:         "stwux",
-       STD:           "std",
-       STDU:          "stdu",
-       STDX:          "stdx",
-       STDUX:         "stdux",
-       LQ:            "lq",
-       STQ:           "stq",
-       LHBRX:         "lhbrx",
-       LWBRX:         "lwbrx",
-       STHBRX:        "sthbrx",
-       STWBRX:        "stwbrx",
-       LDBRX:         "ldbrx",
-       STDBRX:        "stdbrx",
-       LMW:           "lmw",
-       STMW:          "stmw",
-       LSWI:          "lswi",
-       LSWX:          "lswx",
-       STSWI:         "stswi",
-       STSWX:         "stswx",
-       LI:            "li",
-       ADDI:          "addi",
-       LIS:           "lis",
-       ADDIS:         "addis",
-       ADD:           "add",
-       ADDCC:         "add.",
-       ADDO:          "addo",
-       ADDOCC:        "addo.",
-       ADDIC:         "addic",
-       SUBF:          "subf",
-       SUBFCC:        "subf.",
-       SUBFO:         "subfo",
-       SUBFOCC:       "subfo.",
-       ADDICCC:       "addic.",
-       SUBFIC:        "subfic",
-       ADDC:          "addc",
-       ADDCCC:        "addc.",
-       ADDCO:         "addco",
-       ADDCOCC:       "addco.",
-       SUBFC:         "subfc",
-       SUBFCCC:       "subfc.",
-       SUBFCO:        "subfco",
-       SUBFCOCC:      "subfco.",
-       ADDE:          "adde",
-       ADDECC:        "adde.",
-       ADDEO:         "addeo",
-       ADDEOCC:       "addeo.",
-       ADDME:         "addme",
-       ADDMECC:       "addme.",
-       ADDMEO:        "addmeo",
-       ADDMEOCC:      "addmeo.",
-       SUBFE:         "subfe",
-       SUBFECC:       "subfe.",
-       SUBFEO:        "subfeo",
-       SUBFEOCC:      "subfeo.",
-       SUBFME:        "subfme",
-       SUBFMECC:      "subfme.",
-       SUBFMEO:       "subfmeo",
-       SUBFMEOCC:     "subfmeo.",
-       ADDZE:         "addze",
-       ADDZECC:       "addze.",
-       ADDZEO:        "addzeo",
-       ADDZEOCC:      "addzeo.",
-       SUBFZE:        "subfze",
-       SUBFZECC:      "subfze.",
-       SUBFZEO:       "subfzeo",
-       SUBFZEOCC:     "subfzeo.",
-       NEG:           "neg",
-       NEGCC:         "neg.",
-       NEGO:          "nego",
-       NEGOCC:        "nego.",
-       MULLI:         "mulli",
-       MULLW:         "mullw",
-       MULLWCC:       "mullw.",
-       MULLWO:        "mullwo",
-       MULLWOCC:      "mullwo.",
-       MULHW:         "mulhw",
-       MULHWCC:       "mulhw.",
-       MULHWU:        "mulhwu",
-       MULHWUCC:      "mulhwu.",
-       DIVW:          "divw",
-       DIVWCC:        "divw.",
-       DIVWO:         "divwo",
-       DIVWOCC:       "divwo.",
-       DIVWU:         "divwu",
-       DIVWUCC:       "divwu.",
-       DIVWUO:        "divwuo",
-       DIVWUOCC:      "divwuo.",
-       DIVWE:         "divwe",
-       DIVWECC:       "divwe.",
-       DIVWEO:        "divweo",
-       DIVWEOCC:      "divweo.",
-       DIVWEU:        "divweu",
-       DIVWEUCC:      "divweu.",
-       DIVWEUO:       "divweuo",
-       DIVWEUOCC:     "divweuo.",
-       MULLD:         "mulld",
-       MULLDCC:       "mulld.",
-       MULLDO:        "mulldo",
-       MULLDOCC:      "mulldo.",
-       MULHDU:        "mulhdu",
-       MULHDUCC:      "mulhdu.",
-       MULHD:         "mulhd",
-       MULHDCC:       "mulhd.",
-       DIVD:          "divd",
-       DIVDCC:        "divd.",
-       DIVDO:         "divdo",
-       DIVDOCC:       "divdo.",
-       DIVDU:         "divdu",
-       DIVDUCC:       "divdu.",
-       DIVDUO:        "divduo",
-       DIVDUOCC:      "divduo.",
-       DIVDE:         "divde",
-       DIVDECC:       "divde.",
-       DIVDEO:        "divdeo",
-       DIVDEOCC:      "divdeo.",
-       DIVDEU:        "divdeu",
-       DIVDEUCC:      "divdeu.",
-       DIVDEUO:       "divdeuo",
-       DIVDEUOCC:     "divdeuo.",
-       MODSD:         "modsd",
-       MODUD:         "modud",
-       MODSW:         "modsw",
-       MODUW:         "moduw",
-       CMPWI:         "cmpwi",
-       CMPDI:         "cmpdi",
-       CMPW:          "cmpw",
-       CMPD:          "cmpd",
-       CMPLWI:        "cmplwi",
-       CMPLDI:        "cmpldi",
-       CMPLW:         "cmplw",
-       CMPLD:         "cmpld",
-       TWI:           "twi",
-       TW:            "tw",
-       TDI:           "tdi",
-       ISEL:          "isel",
-       TD:            "td",
-       ANDICC:        "andi.",
-       ANDISCC:       "andis.",
-       ORI:           "ori",
-       ORIS:          "oris",
-       XORI:          "xori",
-       XORIS:         "xoris",
-       AND:           "and",
-       ANDCC:         "and.",
-       XOR:           "xor",
-       XORCC:         "xor.",
-       NAND:          "nand",
-       NANDCC:        "nand.",
-       OR:            "or",
-       ORCC:          "or.",
-       NOR:           "nor",
-       NORCC:         "nor.",
-       ANDC:          "andc",
-       ANDCCC:        "andc.",
-       EXTSB:         "extsb",
-       EXTSBCC:       "extsb.",
-       EQV:           "eqv",
-       EQVCC:         "eqv.",
-       ORC:           "orc",
-       ORCCC:         "orc.",
-       EXTSH:         "extsh",
-       EXTSHCC:       "extsh.",
-       CMPB:          "cmpb",
-       POPCNTB:       "popcntb",
-       POPCNTW:       "popcntw",
-       PRTYD:         "prtyd",
-       PRTYW:         "prtyw",
-       EXTSW:         "extsw",
-       EXTSWCC:       "extsw.",
-       CNTLZD:        "cntlzd",
-       CNTLZDCC:      "cntlzd.",
-       POPCNTD:       "popcntd",
-       BPERMD:        "bpermd",
-       RLWINM:        "rlwinm",
-       RLWINMCC:      "rlwinm.",
-       RLWNM:         "rlwnm",
-       RLWNMCC:       "rlwnm.",
-       RLWIMI:        "rlwimi",
-       RLWIMICC:      "rlwimi.",
-       RLDICL:        "rldicl",
-       RLDICLCC:      "rldicl.",
-       RLDICR:        "rldicr",
-       RLDICRCC:      "rldicr.",
-       RLDIC:         "rldic",
-       RLDICCC:       "rldic.",
-       RLDCL:         "rldcl",
-       RLDCLCC:       "rldcl.",
-       RLDCR:         "rldcr",
-       RLDCRCC:       "rldcr.",
-       RLDIMI:        "rldimi",
-       RLDIMICC:      "rldimi.",
-       SLW:           "slw",
-       SLWCC:         "slw.",
-       SRW:           "srw",
-       SRWCC:         "srw.",
-       SRAWI:         "srawi",
-       SRAWICC:       "srawi.",
-       SRAW:          "sraw",
-       SRAWCC:        "sraw.",
-       SLD:           "sld",
-       SLDCC:         "sld.",
-       SRD:           "srd",
-       SRDCC:         "srd.",
-       SRADI:         "sradi",
-       SRADICC:       "sradi.",
-       SRAD:          "srad",
-       SRADCC:        "srad.",
-       CDTBCD:        "cdtbcd",
-       CBCDTD:        "cbcdtd",
-       ADDG6S:        "addg6s",
-       MTSPR:         "mtspr",
-       MFSPR:         "mfspr",
-       MTCRF:         "mtcrf",
-       MFCR:          "mfcr",
-       MTSLE:         "mtsle",
-       MFVSRD:        "mfvsrd",
-       MFVSRWZ:       "mfvsrwz",
-       MTVSRD:        "mtvsrd",
-       MTVSRWA:       "mtvsrwa",
-       MTVSRWZ:       "mtvsrwz",
-       MTOCRF:        "mtocrf",
-       MFOCRF:        "mfocrf",
-       MCRXR:         "mcrxr",
-       MTDCRUX:       "mtdcrux",
-       MFDCRUX:       "mfdcrux",
-       LFS:           "lfs",
-       LFSU:          "lfsu",
-       LFSX:          "lfsx",
-       LFSUX:         "lfsux",
-       LFD:           "lfd",
-       LFDU:          "lfdu",
-       LFDX:          "lfdx",
-       LFDUX:         "lfdux",
-       LFIWAX:        "lfiwax",
-       LFIWZX:        "lfiwzx",
-       STFS:          "stfs",
-       STFSU:         "stfsu",
-       STFSX:         "stfsx",
-       STFSUX:        "stfsux",
-       STFD:          "stfd",
-       STFDU:         "stfdu",
-       STFDX:         "stfdx",
-       STFDUX:        "stfdux",
-       STFIWX:        "stfiwx",
-       LFDP:          "lfdp",
-       LFDPX:         "lfdpx",
-       STFDP:         "stfdp",
-       STFDPX:        "stfdpx",
-       FMR:           "fmr",
-       FMRCC:         "fmr.",
-       FABS:          "fabs",
-       FABSCC:        "fabs.",
-       FNABS:         "fnabs",
-       FNABSCC:       "fnabs.",
-       FNEG:          "fneg",
-       FNEGCC:        "fneg.",
-       FCPSGN:        "fcpsgn",
-       FCPSGNCC:      "fcpsgn.",
-       FMRGEW:        "fmrgew",
-       FMRGOW:        "fmrgow",
-       FADD:          "fadd",
-       FADDCC:        "fadd.",
-       FADDS:         "fadds",
-       FADDSCC:       "fadds.",
-       FSUB:          "fsub",
-       FSUBCC:        "fsub.",
-       FSUBS:         "fsubs",
-       FSUBSCC:       "fsubs.",
-       FMUL:          "fmul",
-       FMULCC:        "fmul.",
-       FMULS:         "fmuls",
-       FMULSCC:       "fmuls.",
-       FDIV:          "fdiv",
-       FDIVCC:        "fdiv.",
-       FDIVS:         "fdivs",
-       FDIVSCC:       "fdivs.",
-       FSQRT:         "fsqrt",
-       FSQRTCC:       "fsqrt.",
-       FSQRTS:        "fsqrts",
-       FSQRTSCC:      "fsqrts.",
-       FRE:           "fre",
-       FRECC:         "fre.",
-       FRES:          "fres",
-       FRESCC:        "fres.",
-       FRSQRTE:       "frsqrte",
-       FRSQRTECC:     "frsqrte.",
-       FRSQRTES:      "frsqrtes",
-       FRSQRTESCC:    "frsqrtes.",
-       FTDIV:         "ftdiv",
-       FTSQRT:        "ftsqrt",
-       FMADD:         "fmadd",
-       FMADDCC:       "fmadd.",
-       FMADDS:        "fmadds",
-       FMADDSCC:      "fmadds.",
-       FMSUB:         "fmsub",
-       FMSUBCC:       "fmsub.",
-       FMSUBS:        "fmsubs",
-       FMSUBSCC:      "fmsubs.",
-       FNMADD:        "fnmadd",
-       FNMADDCC:      "fnmadd.",
-       FNMADDS:       "fnmadds",
-       FNMADDSCC:     "fnmadds.",
-       FNMSUB:        "fnmsub",
-       FNMSUBCC:      "fnmsub.",
-       FNMSUBS:       "fnmsubs",
-       FNMSUBSCC:     "fnmsubs.",
-       FRSP:          "frsp",
-       FRSPCC:        "frsp.",
-       FCTID:         "fctid",
-       FCTIDCC:       "fctid.",
-       FCTIDZ:        "fctidz",
-       FCTIDZCC:      "fctidz.",
-       FCTIDU:        "fctidu",
-       FCTIDUCC:      "fctidu.",
-       FCTIDUZ:       "fctiduz",
-       FCTIDUZCC:     "fctiduz.",
-       FCTIW:         "fctiw",
-       FCTIWCC:       "fctiw.",
-       FCTIWZ:        "fctiwz",
-       FCTIWZCC:      "fctiwz.",
-       FCTIWU:        "fctiwu",
-       FCTIWUCC:      "fctiwu.",
-       FCTIWUZ:       "fctiwuz",
-       FCTIWUZCC:     "fctiwuz.",
-       FCFID:         "fcfid",
-       FCFIDCC:       "fcfid.",
-       FCFIDU:        "fcfidu",
-       FCFIDUCC:      "fcfidu.",
-       FCFIDS:        "fcfids",
-       FCFIDSCC:      "fcfids.",
-       FCFIDUS:       "fcfidus",
-       FCFIDUSCC:     "fcfidus.",
-       FRIN:          "frin",
-       FRINCC:        "frin.",
-       FRIZ:          "friz",
-       FRIZCC:        "friz.",
-       FRIP:          "frip",
-       FRIPCC:        "frip.",
-       FRIM:          "frim",
-       FRIMCC:        "frim.",
-       FCMPU:         "fcmpu",
-       FCMPO:         "fcmpo",
-       FSEL:          "fsel",
-       FSELCC:        "fsel.",
-       MFFS:          "mffs",
-       MFFSCC:        "mffs.",
-       MCRFS:         "mcrfs",
-       MTFSFI:        "mtfsfi",
-       MTFSFICC:      "mtfsfi.",
-       MTFSF:         "mtfsf",
-       MTFSFCC:       "mtfsf.",
-       MTFSB0:        "mtfsb0",
-       MTFSB0CC:      "mtfsb0.",
-       MTFSB1:        "mtfsb1",
-       MTFSB1CC:      "mtfsb1.",
-       LVEBX:         "lvebx",
-       LVEHX:         "lvehx",
-       LVEWX:         "lvewx",
-       LVX:           "lvx",
-       LVXL:          "lvxl",
-       STVEBX:        "stvebx",
-       STVEHX:        "stvehx",
-       STVEWX:        "stvewx",
-       STVX:          "stvx",
-       STVXL:         "stvxl",
-       LVSL:          "lvsl",
-       LVSR:          "lvsr",
-       VPKPX:         "vpkpx",
-       VPKSDSS:       "vpksdss",
-       VPKSDUS:       "vpksdus",
-       VPKSHSS:       "vpkshss",
-       VPKSHUS:       "vpkshus",
-       VPKSWSS:       "vpkswss",
-       VPKSWUS:       "vpkswus",
-       VPKUDUM:       "vpkudum",
-       VPKUDUS:       "vpkudus",
-       VPKUHUM:       "vpkuhum",
-       VPKUHUS:       "vpkuhus",
-       VPKUWUM:       "vpkuwum",
-       VPKUWUS:       "vpkuwus",
-       VUPKHPX:       "vupkhpx",
-       VUPKLPX:       "vupklpx",
-       VUPKHSB:       "vupkhsb",
-       VUPKHSH:       "vupkhsh",
-       VUPKHSW:       "vupkhsw",
-       VUPKLSB:       "vupklsb",
-       VUPKLSH:       "vupklsh",
-       VUPKLSW:       "vupklsw",
-       VMRGHB:        "vmrghb",
-       VMRGHH:        "vmrghh",
-       VMRGLB:        "vmrglb",
-       VMRGLH:        "vmrglh",
-       VMRGHW:        "vmrghw",
-       VMRGLW:        "vmrglw",
-       VMRGEW:        "vmrgew",
-       VMRGOW:        "vmrgow",
-       VSPLTB:        "vspltb",
-       VSPLTH:        "vsplth",
-       VSPLTW:        "vspltw",
-       VSPLTISB:      "vspltisb",
-       VSPLTISH:      "vspltish",
-       VSPLTISW:      "vspltisw",
-       VPERM:         "vperm",
-       VPERMR:        "vpermr",
-       VSEL:          "vsel",
-       VSL:           "vsl",
-       VSLDOI:        "vsldoi",
-       VSLO:          "vslo",
-       VSR:           "vsr",
-       VSRO:          "vsro",
-       VADDCUW:       "vaddcuw",
-       VADDSBS:       "vaddsbs",
-       VADDSHS:       "vaddshs",
-       VADDSWS:       "vaddsws",
-       VADDUBM:       "vaddubm",
-       VADDUDM:       "vaddudm",
-       VADDUHM:       "vadduhm",
-       VADDUWM:       "vadduwm",
-       VADDUBS:       "vaddubs",
-       VADDUHS:       "vadduhs",
-       VADDUWS:       "vadduws",
-       VADDUQM:       "vadduqm",
-       VADDEUQM:      "vaddeuqm",
-       VADDCUQ:       "vaddcuq",
-       VADDECUQ:      "vaddecuq",
-       VSUBCUW:       "vsubcuw",
-       VSUBSBS:       "vsubsbs",
-       VSUBSHS:       "vsubshs",
-       VSUBSWS:       "vsubsws",
-       VSUBUBM:       "vsububm",
-       VSUBUDM:       "vsubudm",
-       VSUBUHM:       "vsubuhm",
-       VSUBUWM:       "vsubuwm",
-       VSUBUBS:       "vsububs",
-       VSUBUHS:       "vsubuhs",
-       VSUBUWS:       "vsubuws",
-       VSUBUQM:       "vsubuqm",
-       VSUBEUQM:      "vsubeuqm",
-       VSUBCUQ:       "vsubcuq",
-       VSUBECUQ:      "vsubecuq",
-       VMULESB:       "vmulesb",
-       VMULEUB:       "vmuleub",
-       VMULOSB:       "vmulosb",
-       VMULOUB:       "vmuloub",
-       VMULESH:       "vmulesh",
-       VMULEUH:       "vmuleuh",
-       VMULOSH:       "vmulosh",
-       VMULOUH:       "vmulouh",
-       VMULESW:       "vmulesw",
-       VMULEUW:       "vmuleuw",
-       VMULOSW:       "vmulosw",
-       VMULOUW:       "vmulouw",
-       VMULUWM:       "vmuluwm",
-       VMHADDSHS:     "vmhaddshs",
-       VMHRADDSHS:    "vmhraddshs",
-       VMLADDUHM:     "vmladduhm",
-       VMSUMUBM:      "vmsumubm",
-       VMSUMMBM:      "vmsummbm",
-       VMSUMSHM:      "vmsumshm",
-       VMSUMSHS:      "vmsumshs",
-       VMSUMUHM:      "vmsumuhm",
-       VMSUMUHS:      "vmsumuhs",
-       VMSUMUDM:      "vmsumudm",
-       VSUMSWS:       "vsumsws",
-       VSUM2SWS:      "vsum2sws",
-       VSUM4SBS:      "vsum4sbs",
-       VSUM4SHS:      "vsum4shs",
-       VSUM4UBS:      "vsum4ubs",
-       VAVGSB:        "vavgsb",
-       VAVGSH:        "vavgsh",
-       VAVGSW:        "vavgsw",
-       VAVGUB:        "vavgub",
-       VAVGUW:        "vavguw",
-       VAVGUH:        "vavguh",
-       VMAXSB:        "vmaxsb",
-       VMAXSD:        "vmaxsd",
-       VMAXUB:        "vmaxub",
-       VMAXUD:        "vmaxud",
-       VMAXSH:        "vmaxsh",
-       VMAXSW:        "vmaxsw",
-       VMAXUH:        "vmaxuh",
-       VMAXUW:        "vmaxuw",
-       VMINSB:        "vminsb",
-       VMINSD:        "vminsd",
-       VMINUB:        "vminub",
-       VMINUD:        "vminud",
-       VMINSH:        "vminsh",
-       VMINSW:        "vminsw",
-       VMINUH:        "vminuh",
-       VMINUW:        "vminuw",
-       VCMPEQUB:      "vcmpequb",
-       VCMPEQUBCC:    "vcmpequb.",
-       VCMPEQUH:      "vcmpequh",
-       VCMPEQUHCC:    "vcmpequh.",
-       VCMPEQUW:      "vcmpequw",
-       VCMPEQUWCC:    "vcmpequw.",
-       VCMPEQUD:      "vcmpequd",
-       VCMPEQUDCC:    "vcmpequd.",
-       VCMPNEB:       "vcmpneb",
-       VCMPNEBCC:     "vcmpneb.",
-       VCMPNEZB:      "vcmpnezb",
-       VCMPNEZBCC:    "vcmpnezb.",
-       VCMPNEH:       "vcmpneh",
-       VCMPNEHCC:     "vcmpneh.",
-       VCMPNEZH:      "vcmpnezh",
-       VCMPNEZHCC:    "vcmpnezh.",
-       VCMPNEW:       "vcmpnew",
-       VCMPNEWCC:     "vcmpnew.",
-       VCMPNEZW:      "vcmpnezw",
-       VCMPNEZWCC:    "vcmpnezw.",
-       VCMPGTSB:      "vcmpgtsb",
-       VCMPGTSBCC:    "vcmpgtsb.",
-       VCMPGTSD:      "vcmpgtsd",
-       VCMPGTSDCC:    "vcmpgtsd.",
-       VCMPGTSH:      "vcmpgtsh",
-       VCMPGTSHCC:    "vcmpgtsh.",
-       VCMPGTSW:      "vcmpgtsw",
-       VCMPGTSWCC:    "vcmpgtsw.",
-       VCMPGTUB:      "vcmpgtub",
-       VCMPGTUBCC:    "vcmpgtub.",
-       VCMPGTUD:      "vcmpgtud",
-       VCMPGTUDCC:    "vcmpgtud.",
-       VCMPGTUH:      "vcmpgtuh",
-       VCMPGTUHCC:    "vcmpgtuh.",
-       VCMPGTUW:      "vcmpgtuw",
-       VCMPGTUWCC:    "vcmpgtuw.",
-       VAND:          "vand",
-       VANDC:         "vandc",
-       VEQV:          "veqv",
-       VNAND:         "vnand",
-       VORC:          "vorc",
-       VNOR:          "vnor",
-       VOR:           "vor",
-       VXOR:          "vxor",
-       VRLB:          "vrlb",
-       VRLH:          "vrlh",
-       VRLW:          "vrlw",
-       VRLD:          "vrld",
-       VSLB:          "vslb",
-       VSLH:          "vslh",
-       VSLW:          "vslw",
-       VSLD:          "vsld",
-       VSRB:          "vsrb",
-       VSRH:          "vsrh",
-       VSRW:          "vsrw",
-       VSRD:          "vsrd",
-       VSRAB:         "vsrab",
-       VSRAH:         "vsrah",
-       VSRAW:         "vsraw",
-       VSRAD:         "vsrad",
-       VADDFP:        "vaddfp",
-       VSUBFP:        "vsubfp",
-       VMADDFP:       "vmaddfp",
-       VNMSUBFP:      "vnmsubfp",
-       VMAXFP:        "vmaxfp",
-       VMINFP:        "vminfp",
-       VCTSXS:        "vctsxs",
-       VCTUXS:        "vctuxs",
-       VCFSX:         "vcfsx",
-       VCFUX:         "vcfux",
-       VRFIM:         "vrfim",
-       VRFIN:         "vrfin",
-       VRFIP:         "vrfip",
-       VRFIZ:         "vrfiz",
-       VCMPBFP:       "vcmpbfp",
-       VCMPBFPCC:     "vcmpbfp.",
-       VCMPEQFP:      "vcmpeqfp",
-       VCMPEQFPCC:    "vcmpeqfp.",
-       VCMPGEFP:      "vcmpgefp",
-       VCMPGEFPCC:    "vcmpgefp.",
-       VCMPGTFP:      "vcmpgtfp",
-       VCMPGTFPCC:    "vcmpgtfp.",
-       VEXPTEFP:      "vexptefp",
-       VLOGEFP:       "vlogefp",
-       VREFP:         "vrefp",
-       VRSQRTEFP:     "vrsqrtefp",
-       VCIPHER:       "vcipher",
-       VCIPHERLAST:   "vcipherlast",
-       VNCIPHER:      "vncipher",
-       VNCIPHERLAST:  "vncipherlast",
-       VSBOX:         "vsbox",
-       VSHASIGMAD:    "vshasigmad",
-       VSHASIGMAW:    "vshasigmaw",
-       VPMSUMB:       "vpmsumb",
-       VPMSUMD:       "vpmsumd",
-       VPMSUMH:       "vpmsumh",
-       VPMSUMW:       "vpmsumw",
-       VPERMXOR:      "vpermxor",
-       VGBBD:         "vgbbd",
-       VCLZB:         "vclzb",
-       VCLZH:         "vclzh",
-       VCLZW:         "vclzw",
-       VCLZD:         "vclzd",
-       VPOPCNTB:      "vpopcntb",
-       VPOPCNTD:      "vpopcntd",
-       VPOPCNTH:      "vpopcnth",
-       VPOPCNTW:      "vpopcntw",
-       VBPERMQ:       "vbpermq",
-       VBPERMD:       "vbpermd",
-       BCDADDCC:      "bcdadd.",
-       BCDSUBCC:      "bcdsub.",
-       MTVSCR:        "mtvscr",
-       MFVSCR:        "mfvscr",
-       DADD:          "dadd",
-       DADDCC:        "dadd.",
-       DSUB:          "dsub",
-       DSUBCC:        "dsub.",
-       DMUL:          "dmul",
-       DMULCC:        "dmul.",
-       DDIV:          "ddiv",
-       DDIVCC:        "ddiv.",
-       DCMPU:         "dcmpu",
-       DCMPO:         "dcmpo",
-       DTSTDC:        "dtstdc",
-       DTSTDG:        "dtstdg",
-       DTSTEX:        "dtstex",
-       DTSTSF:        "dtstsf",
-       DQUAI:         "dquai",
-       DQUAICC:       "dquai.",
-       DQUA:          "dqua",
-       DQUACC:        "dqua.",
-       DRRND:         "drrnd",
-       DRRNDCC:       "drrnd.",
-       DRINTX:        "drintx",
-       DRINTXCC:      "drintx.",
-       DRINTN:        "drintn",
-       DRINTNCC:      "drintn.",
-       DCTDP:         "dctdp",
-       DCTDPCC:       "dctdp.",
-       DCTQPQ:        "dctqpq",
-       DCTQPQCC:      "dctqpq.",
-       DRSP:          "drsp",
-       DRSPCC:        "drsp.",
-       DRDPQ:         "drdpq",
-       DRDPQCC:       "drdpq.",
-       DCFFIX:        "dcffix",
-       DCFFIXCC:      "dcffix.",
-       DCFFIXQ:       "dcffixq",
-       DCFFIXQCC:     "dcffixq.",
-       DCTFIX:        "dctfix",
-       DCTFIXCC:      "dctfix.",
-       DDEDPD:        "ddedpd",
-       DDEDPDCC:      "ddedpd.",
-       DENBCD:        "denbcd",
-       DENBCDCC:      "denbcd.",
-       DXEX:          "dxex",
-       DXEXCC:        "dxex.",
-       DIEX:          "diex",
-       DIEXCC:        "diex.",
-       DSCLI:         "dscli",
-       DSCLICC:       "dscli.",
-       DSCRI:         "dscri",
-       DSCRICC:       "dscri.",
-       LXSDX:         "lxsdx",
-       LXSIWAX:       "lxsiwax",
-       LXSIWZX:       "lxsiwzx",
-       LXSSPX:        "lxsspx",
-       LXVD2X:        "lxvd2x",
-       LXVDSX:        "lxvdsx",
-       LXVW4X:        "lxvw4x",
-       LXVH8X:        "lxvh8x",
-       LXVB16X:       "lxvb16x",
-       LXV:           "lxv",
-       LXVL:          "lxvl",
-       LXVLL:         "lxvll",
-       LXVX:          "lxvx",
-       STXSDX:        "stxsdx",
-       STXSIWX:       "stxsiwx",
-       STXSSPX:       "stxsspx",
-       STXVD2X:       "stxvd2x",
-       STXVW4X:       "stxvw4x",
-       STXVH8X:       "stxvh8x",
-       STXVB16X:      "stxvb16x",
-       STXV:          "stxv",
-       STXVL:         "stxvl",
-       STXVLL:        "stxvll",
-       STXVX:         "stxvx",
-       XSABSDP:       "xsabsdp",
-       XSADDDP:       "xsadddp",
-       XSADDSP:       "xsaddsp",
-       XSCMPODP:      "xscmpodp",
-       XSCMPUDP:      "xscmpudp",
-       XSCPSGNDP:     "xscpsgndp",
-       XSCVDPSP:      "xscvdpsp",
-       XSCVDPSPN:     "xscvdpspn",
-       XSCVDPSXDS:    "xscvdpsxds",
-       XSCVDPSXWS:    "xscvdpsxws",
-       XSCVDPUXDS:    "xscvdpuxds",
-       XSCVDPUXWS:    "xscvdpuxws",
-       XSCVSPDP:      "xscvspdp",
-       XSCVSPDPN:     "xscvspdpn",
-       XSCVSXDDP:     "xscvsxddp",
-       XSCVSXDSP:     "xscvsxdsp",
-       XSCVUXDDP:     "xscvuxddp",
-       XSCVUXDSP:     "xscvuxdsp",
-       XSDIVDP:       "xsdivdp",
-       XSDIVSP:       "xsdivsp",
-       XSMADDADP:     "xsmaddadp",
-       XSMADDASP:     "xsmaddasp",
-       XSMAXDP:       "xsmaxdp",
-       XSMINDP:       "xsmindp",
-       XSMSUBADP:     "xsmsubadp",
-       XSMSUBASP:     "xsmsubasp",
-       XSMULDP:       "xsmuldp",
-       XSMULSP:       "xsmulsp",
-       XSNABSDP:      "xsnabsdp",
-       XSNEGDP:       "xsnegdp",
-       XSNMADDADP:    "xsnmaddadp",
-       XSNMADDASP:    "xsnmaddasp",
-       XSNMSUBADP:    "xsnmsubadp",
-       XSNMSUBASP:    "xsnmsubasp",
-       XSRDPI:        "xsrdpi",
-       XSRDPIC:       "xsrdpic",
-       XSRDPIM:       "xsrdpim",
-       XSRDPIP:       "xsrdpip",
-       XSRDPIZ:       "xsrdpiz",
-       XSREDP:        "xsredp",
-       XSRESP:        "xsresp",
-       XSRSP:         "xsrsp",
-       XSRSQRTEDP:    "xsrsqrtedp",
-       XSRSQRTESP:    "xsrsqrtesp",
-       XSSQRTDP:      "xssqrtdp",
-       XSSQRTSP:      "xssqrtsp",
-       XSSUBDP:       "xssubdp",
-       XSSUBSP:       "xssubsp",
-       XSTDIVDP:      "xstdivdp",
-       XSTSQRTDP:     "xstsqrtdp",
-       XVABSDP:       "xvabsdp",
-       XVABSSP:       "xvabssp",
-       XVADDDP:       "xvadddp",
-       XVADDSP:       "xvaddsp",
-       XVCMPEQDP:     "xvcmpeqdp",
-       XVCMPEQDPCC:   "xvcmpeqdp.",
-       XVCMPEQSP:     "xvcmpeqsp",
-       XVCMPEQSPCC:   "xvcmpeqsp.",
-       XVCMPGEDP:     "xvcmpgedp",
-       XVCMPGEDPCC:   "xvcmpgedp.",
-       XVCMPGESP:     "xvcmpgesp",
-       XVCMPGESPCC:   "xvcmpgesp.",
-       XVCMPGTDP:     "xvcmpgtdp",
-       XVCMPGTDPCC:   "xvcmpgtdp.",
-       XVCMPGTSP:     "xvcmpgtsp",
-       XVCMPGTSPCC:   "xvcmpgtsp.",
-       XVCPSGNDP:     "xvcpsgndp",
-       XVCPSGNSP:     "xvcpsgnsp",
-       XVCVDPSP:      "xvcvdpsp",
-       XVCVDPSXDS:    "xvcvdpsxds",
-       XVCVDPSXWS:    "xvcvdpsxws",
-       XVCVDPUXDS:    "xvcvdpuxds",
-       XVCVDPUXWS:    "xvcvdpuxws",
-       XVCVSPDP:      "xvcvspdp",
-       XVCVSPSXDS:    "xvcvspsxds",
-       XVCVSPSXWS:    "xvcvspsxws",
-       XVCVSPUXDS:    "xvcvspuxds",
-       XVCVSPUXWS:    "xvcvspuxws",
-       XVCVSXDDP:     "xvcvsxddp",
-       XVCVSXDSP:     "xvcvsxdsp",
-       XVCVSXWDP:     "xvcvsxwdp",
-       XVCVSXWSP:     "xvcvsxwsp",
-       XVCVUXDDP:     "xvcvuxddp",
-       XVCVUXDSP:     "xvcvuxdsp",
-       XVCVUXWDP:     "xvcvuxwdp",
-       XVCVUXWSP:     "xvcvuxwsp",
-       XVDIVDP:       "xvdivdp",
-       XVDIVSP:       "xvdivsp",
-       XVMADDADP:     "xvmaddadp",
-       XVMADDASP:     "xvmaddasp",
-       XVMAXDP:       "xvmaxdp",
-       XVMAXSP:       "xvmaxsp",
-       XVMINDP:       "xvmindp",
-       XVMINSP:       "xvminsp",
-       XVMSUBADP:     "xvmsubadp",
-       XVMSUBASP:     "xvmsubasp",
-       XVMULDP:       "xvmuldp",
-       XVMULSP:       "xvmulsp",
-       XVNABSDP:      "xvnabsdp",
-       XVNABSSP:      "xvnabssp",
-       XVNEGDP:       "xvnegdp",
-       XVNEGSP:       "xvnegsp",
-       XVNMADDADP:    "xvnmaddadp",
-       XVNMADDASP:    "xvnmaddasp",
-       XVNMSUBADP:    "xvnmsubadp",
-       XVNMSUBASP:    "xvnmsubasp",
-       XVRDPI:        "xvrdpi",
-       XVRDPIC:       "xvrdpic",
-       XVRDPIM:       "xvrdpim",
-       XVRDPIP:       "xvrdpip",
-       XVRDPIZ:       "xvrdpiz",
-       XVREDP:        "xvredp",
-       XVRESP:        "xvresp",
-       XVRSPI:        "xvrspi",
-       XVRSPIC:       "xvrspic",
-       XVRSPIM:       "xvrspim",
-       XVRSPIP:       "xvrspip",
-       XVRSPIZ:       "xvrspiz",
-       XVRSQRTEDP:    "xvrsqrtedp",
-       XVRSQRTESP:    "xvrsqrtesp",
-       XVSQRTDP:      "xvsqrtdp",
-       XVSQRTSP:      "xvsqrtsp",
-       XVSUBDP:       "xvsubdp",
-       XVSUBSP:       "xvsubsp",
-       XVTDIVDP:      "xvtdivdp",
-       XVTDIVSP:      "xvtdivsp",
-       XVTSQRTDP:     "xvtsqrtdp",
-       XVTSQRTSP:     "xvtsqrtsp",
-       XXLAND:        "xxland",
-       XXLANDC:       "xxlandc",
-       XXLEQV:        "xxleqv",
-       XXLNAND:       "xxlnand",
-       XXLORC:        "xxlorc",
-       XXLNOR:        "xxlnor",
-       XXLOR:         "xxlor",
-       XXLXOR:        "xxlxor",
-       XXMRGHW:       "xxmrghw",
-       XXMRGLW:       "xxmrglw",
-       XXPERMDI:      "xxpermdi",
-       XXPERM:        "xxperm",
-       XXSEL:         "xxsel",
-       XXSLDWI:       "xxsldwi",
-       XXSPLTW:       "xxspltw",
-       XXBRD:         "xxbrd",
-       XXBRW:         "xxbrw",
-       XXBRH:         "xxbrh",
-       BRINC:         "brinc",
-       EVABS:         "evabs",
-       EVADDIW:       "evaddiw",
-       EVADDSMIAAW:   "evaddsmiaaw",
-       EVADDSSIAAW:   "evaddssiaaw",
-       EVADDUMIAAW:   "evaddumiaaw",
-       EVADDUSIAAW:   "evaddusiaaw",
-       EVADDW:        "evaddw",
-       EVAND:         "evand",
-       EVCMPEQ:       "evcmpeq",
-       EVANDC:        "evandc",
-       EVCMPGTS:      "evcmpgts",
-       EVCMPGTU:      "evcmpgtu",
-       EVCMPLTU:      "evcmpltu",
-       EVCMPLTS:      "evcmplts",
-       EVCNTLSW:      "evcntlsw",
-       EVCNTLZW:      "evcntlzw",
-       EVDIVWS:       "evdivws",
-       EVDIVWU:       "evdivwu",
-       EVEQV:         "eveqv",
-       EVEXTSB:       "evextsb",
-       EVEXTSH:       "evextsh",
-       EVLDD:         "evldd",
-       EVLDH:         "evldh",
-       EVLDDX:        "evlddx",
-       EVLDHX:        "evldhx",
-       EVLDW:         "evldw",
-       EVLHHESPLAT:   "evlhhesplat",
-       EVLDWX:        "evldwx",
-       EVLHHESPLATX:  "evlhhesplatx",
-       EVLHHOSSPLAT:  "evlhhossplat",
-       EVLHHOUSPLAT:  "evlhhousplat",
-       EVLHHOSSPLATX: "evlhhossplatx",
-       EVLHHOUSPLATX: "evlhhousplatx",
-       EVLWHE:        "evlwhe",
-       EVLWHOS:       "evlwhos",
-       EVLWHEX:       "evlwhex",
-       EVLWHOSX:      "evlwhosx",
-       EVLWHOU:       "evlwhou",
-       EVLWHSPLAT:    "evlwhsplat",
-       EVLWHOUX:      "evlwhoux",
-       EVLWHSPLATX:   "evlwhsplatx",
-       EVLWWSPLAT:    "evlwwsplat",
-       EVMERGEHI:     "evmergehi",
-       EVLWWSPLATX:   "evlwwsplatx",
-       EVMERGELO:     "evmergelo",
-       EVMERGEHILO:   "evmergehilo",
-       EVMHEGSMFAA:   "evmhegsmfaa",
-       EVMERGELOHI:   "evmergelohi",
-       EVMHEGSMFAN:   "evmhegsmfan",
-       EVMHEGSMIAA:   "evmhegsmiaa",
-       EVMHEGUMIAA:   "evmhegumiaa",
-       EVMHEGSMIAN:   "evmhegsmian",
-       EVMHEGUMIAN:   "evmhegumian",
-       EVMHESMF:      "evmhesmf",
-       EVMHESMFAAW:   "evmhesmfaaw",
-       EVMHESMFA:     "evmhesmfa",
-       EVMHESMFANW:   "evmhesmfanw",
-       EVMHESMI:      "evmhesmi",
-       EVMHESMIAAW:   "evmhesmiaaw",
-       EVMHESMIA:     "evmhesmia",
-       EVMHESMIANW:   "evmhesmianw",
-       EVMHESSF:      "evmhessf",
-       EVMHESSFA:     "evmhessfa",
-       EVMHESSFAAW:   "evmhessfaaw",
-       EVMHESSFANW:   "evmhessfanw",
-       EVMHESSIAAW:   "evmhessiaaw",
-       EVMHESSIANW:   "evmhessianw",
-       EVMHEUMI:      "evmheumi",
-       EVMHEUMIAAW:   "evmheumiaaw",
-       EVMHEUMIA:     "evmheumia",
-       EVMHEUMIANW:   "evmheumianw",
-       EVMHEUSIAAW:   "evmheusiaaw",
-       EVMHEUSIANW:   "evmheusianw",
-       EVMHOGSMFAA:   "evmhogsmfaa",
-       EVMHOGSMIAA:   "evmhogsmiaa",
-       EVMHOGSMFAN:   "evmhogsmfan",
-       EVMHOGSMIAN:   "evmhogsmian",
-       EVMHOGUMIAA:   "evmhogumiaa",
-       EVMHOSMF:      "evmhosmf",
-       EVMHOGUMIAN:   "evmhogumian",
-       EVMHOSMFA:     "evmhosmfa",
-       EVMHOSMFAAW:   "evmhosmfaaw",
-       EVMHOSMI:      "evmhosmi",
-       EVMHOSMFANW:   "evmhosmfanw",
-       EVMHOSMIA:     "evmhosmia",
-       EVMHOSMIAAW:   "evmhosmiaaw",
-       EVMHOSMIANW:   "evmhosmianw",
-       EVMHOSSF:      "evmhossf",
-       EVMHOSSFA:     "evmhossfa",
-       EVMHOSSFAAW:   "evmhossfaaw",
-       EVMHOSSFANW:   "evmhossfanw",
-       EVMHOSSIAAW:   "evmhossiaaw",
-       EVMHOUMI:      "evmhoumi",
-       EVMHOSSIANW:   "evmhossianw",
-       EVMHOUMIA:     "evmhoumia",
-       EVMHOUMIAAW:   "evmhoumiaaw",
-       EVMHOUSIAAW:   "evmhousiaaw",
-       EVMHOUMIANW:   "evmhoumianw",
-       EVMHOUSIANW:   "evmhousianw",
-       EVMRA:         "evmra",
-       EVMWHSMF:      "evmwhsmf",
-       EVMWHSMI:      "evmwhsmi",
-       EVMWHSMFA:     "evmwhsmfa",
-       EVMWHSMIA:     "evmwhsmia",
-       EVMWHSSF:      "evmwhssf",
-       EVMWHUMI:      "evmwhumi",
-       EVMWHSSFA:     "evmwhssfa",
-       EVMWHUMIA:     "evmwhumia",
-       EVMWLSMIAAW:   "evmwlsmiaaw",
-       EVMWLSSIAAW:   "evmwlssiaaw",
-       EVMWLSMIANW:   "evmwlsmianw",
-       EVMWLSSIANW:   "evmwlssianw",
-       EVMWLUMI:      "evmwlumi",
-       EVMWLUMIAAW:   "evmwlumiaaw",
-       EVMWLUMIA:     "evmwlumia",
-       EVMWLUMIANW:   "evmwlumianw",
-       EVMWLUSIAAW:   "evmwlusiaaw",
-       EVMWSMF:       "evmwsmf",
-       EVMWLUSIANW:   "evmwlusianw",
-       EVMWSMFA:      "evmwsmfa",
-       EVMWSMFAA:     "evmwsmfaa",
-       EVMWSMI:       "evmwsmi",
-       EVMWSMIAA:     "evmwsmiaa",
-       EVMWSMFAN:     "evmwsmfan",
-       EVMWSMIA:      "evmwsmia",
-       EVMWSMIAN:     "evmwsmian",
-       EVMWSSF:       "evmwssf",
-       EVMWSSFA:      "evmwssfa",
-       EVMWSSFAA:     "evmwssfaa",
-       EVMWUMI:       "evmwumi",
-       EVMWSSFAN:     "evmwssfan",
-       EVMWUMIA:      "evmwumia",
-       EVMWUMIAA:     "evmwumiaa",
-       EVNAND:        "evnand",
-       EVMWUMIAN:     "evmwumian",
-       EVNEG:         "evneg",
-       EVNOR:         "evnor",
-       EVORC:         "evorc",
-       EVOR:          "evor",
-       EVRLW:         "evrlw",
-       EVRLWI:        "evrlwi",
-       EVSEL:         "evsel",
-       EVRNDW:        "evrndw",
-       EVSLW:         "evslw",
-       EVSPLATFI:     "evsplatfi",
-       EVSRWIS:       "evsrwis",
-       EVSLWI:        "evslwi",
-       EVSPLATI:      "evsplati",
-       EVSRWIU:       "evsrwiu",
-       EVSRWS:        "evsrws",
-       EVSTDD:        "evstdd",
-       EVSRWU:        "evsrwu",
-       EVSTDDX:       "evstddx",
-       EVSTDH:        "evstdh",
-       EVSTDW:        "evstdw",
-       EVSTDHX:       "evstdhx",
-       EVSTDWX:       "evstdwx",
-       EVSTWHE:       "evstwhe",
-       EVSTWHO:       "evstwho",
-       EVSTWWE:       "evstwwe",
-       EVSTWHEX:      "evstwhex",
-       EVSTWHOX:      "evstwhox",
-       EVSTWWEX:      "evstwwex",
-       EVSTWWO:       "evstwwo",
-       EVSUBFSMIAAW:  "evsubfsmiaaw",
-       EVSTWWOX:      "evstwwox",
-       EVSUBFSSIAAW:  "evsubfssiaaw",
-       EVSUBFUMIAAW:  "evsubfumiaaw",
-       EVSUBFUSIAAW:  "evsubfusiaaw",
-       EVSUBFW:       "evsubfw",
-       EVSUBIFW:      "evsubifw",
-       EVXOR:         "evxor",
-       EVFSABS:       "evfsabs",
-       EVFSNABS:      "evfsnabs",
-       EVFSNEG:       "evfsneg",
-       EVFSADD:       "evfsadd",
-       EVFSMUL:       "evfsmul",
-       EVFSSUB:       "evfssub",
-       EVFSDIV:       "evfsdiv",
-       EVFSCMPGT:     "evfscmpgt",
-       EVFSCMPLT:     "evfscmplt",
-       EVFSCMPEQ:     "evfscmpeq",
-       EVFSTSTGT:     "evfststgt",
-       EVFSTSTLT:     "evfststlt",
-       EVFSTSTEQ:     "evfststeq",
-       EVFSCFSI:      "evfscfsi",
-       EVFSCFSF:      "evfscfsf",
-       EVFSCFUI:      "evfscfui",
-       EVFSCFUF:      "evfscfuf",
-       EVFSCTSI:      "evfsctsi",
-       EVFSCTUI:      "evfsctui",
-       EVFSCTSIZ:     "evfsctsiz",
-       EVFSCTUIZ:     "evfsctuiz",
-       EVFSCTSF:      "evfsctsf",
-       EVFSCTUF:      "evfsctuf",
-       EFSABS:        "efsabs",
-       EFSNEG:        "efsneg",
-       EFSNABS:       "efsnabs",
-       EFSADD:        "efsadd",
-       EFSMUL:        "efsmul",
-       EFSSUB:        "efssub",
-       EFSDIV:        "efsdiv",
-       EFSCMPGT:      "efscmpgt",
-       EFSCMPLT:      "efscmplt",
-       EFSCMPEQ:      "efscmpeq",
-       EFSTSTGT:      "efststgt",
-       EFSTSTLT:      "efststlt",
-       EFSTSTEQ:      "efststeq",
-       EFSCFSI:       "efscfsi",
-       EFSCFSF:       "efscfsf",
-       EFSCTSI:       "efsctsi",
-       EFSCFUI:       "efscfui",
-       EFSCFUF:       "efscfuf",
-       EFSCTUI:       "efsctui",
-       EFSCTSIZ:      "efsctsiz",
-       EFSCTSF:       "efsctsf",
-       EFSCTUIZ:      "efsctuiz",
-       EFSCTUF:       "efsctuf",
-       EFDABS:        "efdabs",
-       EFDNEG:        "efdneg",
-       EFDNABS:       "efdnabs",
-       EFDADD:        "efdadd",
-       EFDMUL:        "efdmul",
-       EFDSUB:        "efdsub",
-       EFDDIV:        "efddiv",
-       EFDCMPGT:      "efdcmpgt",
-       EFDCMPEQ:      "efdcmpeq",
-       EFDCMPLT:      "efdcmplt",
-       EFDTSTGT:      "efdtstgt",
-       EFDTSTLT:      "efdtstlt",
-       EFDCFSI:       "efdcfsi",
-       EFDTSTEQ:      "efdtsteq",
-       EFDCFUI:       "efdcfui",
-       EFDCFSID:      "efdcfsid",
-       EFDCFSF:       "efdcfsf",
-       EFDCFUF:       "efdcfuf",
-       EFDCFUID:      "efdcfuid",
-       EFDCTSI:       "efdctsi",
-       EFDCTUI:       "efdctui",
-       EFDCTSIDZ:     "efdctsidz",
-       EFDCTUIDZ:     "efdctuidz",
-       EFDCTSIZ:      "efdctsiz",
-       EFDCTSF:       "efdctsf",
-       EFDCTUF:       "efdctuf",
-       EFDCTUIZ:      "efdctuiz",
-       EFDCFS:        "efdcfs",
-       EFSCFD:        "efscfd",
-       DLMZB:         "dlmzb",
-       DLMZBCC:       "dlmzb.",
-       MACCHW:        "macchw",
-       MACCHWCC:      "macchw.",
-       MACCHWO:       "macchwo",
-       MACCHWOCC:     "macchwo.",
-       MACCHWS:       "macchws",
-       MACCHWSCC:     "macchws.",
-       MACCHWSO:      "macchwso",
-       MACCHWSOCC:    "macchwso.",
-       MACCHWU:       "macchwu",
-       MACCHWUCC:     "macchwu.",
-       MACCHWUO:      "macchwuo",
-       MACCHWUOCC:    "macchwuo.",
-       MACCHWSU:      "macchwsu",
-       MACCHWSUCC:    "macchwsu.",
-       MACCHWSUO:     "macchwsuo",
-       MACCHWSUOCC:   "macchwsuo.",
-       MACHHW:        "machhw",
-       MACHHWCC:      "machhw.",
-       MACHHWO:       "machhwo",
-       MACHHWOCC:     "machhwo.",
-       MACHHWS:       "machhws",
-       MACHHWSCC:     "machhws.",
-       MACHHWSO:      "machhwso",
-       MACHHWSOCC:    "machhwso.",
-       MACHHWU:       "machhwu",
-       MACHHWUCC:     "machhwu.",
-       MACHHWUO:      "machhwuo",
-       MACHHWUOCC:    "machhwuo.",
-       MACHHWSU:      "machhwsu",
-       MACHHWSUCC:    "machhwsu.",
-       MACHHWSUO:     "machhwsuo",
-       MACHHWSUOCC:   "machhwsuo.",
-       MACLHW:        "maclhw",
-       MACLHWCC:      "maclhw.",
-       MACLHWO:       "maclhwo",
-       MACLHWOCC:     "maclhwo.",
-       MACLHWS:       "maclhws",
-       MACLHWSCC:     "maclhws.",
-       MACLHWSO:      "maclhwso",
-       MACLHWSOCC:    "maclhwso.",
-       MACLHWU:       "maclhwu",
-       MACLHWUCC:     "maclhwu.",
-       MACLHWUO:      "maclhwuo",
-       MACLHWUOCC:    "maclhwuo.",
-       MULCHW:        "mulchw",
-       MULCHWCC:      "mulchw.",
-       MACLHWSU:      "maclhwsu",
-       MACLHWSUCC:    "maclhwsu.",
-       MACLHWSUO:     "maclhwsuo",
-       MACLHWSUOCC:   "maclhwsuo.",
-       MULCHWU:       "mulchwu",
-       MULCHWUCC:     "mulchwu.",
-       MULHHW:        "mulhhw",
-       MULHHWCC:      "mulhhw.",
-       MULLHW:        "mullhw",
-       MULLHWCC:      "mullhw.",
-       MULHHWU:       "mulhhwu",
-       MULHHWUCC:     "mulhhwu.",
-       MULLHWU:       "mullhwu",
-       MULLHWUCC:     "mullhwu.",
-       NMACCHW:       "nmacchw",
-       NMACCHWCC:     "nmacchw.",
-       NMACCHWO:      "nmacchwo",
-       NMACCHWOCC:    "nmacchwo.",
-       NMACCHWS:      "nmacchws",
-       NMACCHWSCC:    "nmacchws.",
-       NMACCHWSO:     "nmacchwso",
-       NMACCHWSOCC:   "nmacchwso.",
-       NMACHHW:       "nmachhw",
-       NMACHHWCC:     "nmachhw.",
-       NMACHHWO:      "nmachhwo",
-       NMACHHWOCC:    "nmachhwo.",
-       NMACHHWS:      "nmachhws",
-       NMACHHWSCC:    "nmachhws.",
-       NMACHHWSO:     "nmachhwso",
-       NMACHHWSOCC:   "nmachhwso.",
-       NMACLHW:       "nmaclhw",
-       NMACLHWCC:     "nmaclhw.",
-       NMACLHWO:      "nmaclhwo",
-       NMACLHWOCC:    "nmaclhwo.",
-       NMACLHWS:      "nmaclhws",
-       NMACLHWSCC:    "nmaclhws.",
-       NMACLHWSO:     "nmaclhwso",
-       NMACLHWSOCC:   "nmaclhwso.",
-       ICBI:          "icbi",
-       ICBT:          "icbt",
-       DCBA:          "dcba",
-       DCBT:          "dcbt",
-       DCBTST:        "dcbtst",
-       DCBZ:          "dcbz",
-       DCBST:         "dcbst",
-       DCBF:          "dcbf",
-       ISYNC:         "isync",
-       LBARX:         "lbarx",
-       LHARX:         "lharx",
-       LWARX:         "lwarx",
-       STBCXCC:       "stbcx.",
-       STHCXCC:       "sthcx.",
-       STWCXCC:       "stwcx.",
-       LDARX:         "ldarx",
-       STDCXCC:       "stdcx.",
-       LQARX:         "lqarx",
-       STQCXCC:       "stqcx.",
-       SYNC:          "sync",
-       EIEIO:         "eieio",
-       MBAR:          "mbar",
-       WAIT:          "wait",
-       TBEGINCC:      "tbegin.",
-       TENDCC:        "tend.",
-       TABORTCC:      "tabort.",
-       TABORTWCCC:    "tabortwc.",
-       TABORTWCICC:   "tabortwci.",
-       TABORTDCCC:    "tabortdc.",
-       TABORTDCICC:   "tabortdci.",
-       TSRCC:         "tsr.",
-       TCHECK:        "tcheck",
-       MFTB:          "mftb",
-       RFEBB:         "rfebb",
-       LBDX:          "lbdx",
-       LHDX:          "lhdx",
-       LWDX:          "lwdx",
-       LDDX:          "lddx",
-       LFDDX:         "lfddx",
-       STBDX:         "stbdx",
-       STHDX:         "sthdx",
-       STWDX:         "stwdx",
-       STDDX:         "stddx",
-       STFDDX:        "stfddx",
-       DSN:           "dsn",
-       ECIWX:         "eciwx",
-       ECOWX:         "ecowx",
-       RFID:          "rfid",
-       HRFID:         "hrfid",
-       DOZE:          "doze",
-       NAP:           "nap",
-       SLEEP:         "sleep",
-       RVWINKLE:      "rvwinkle",
-       LBZCIX:        "lbzcix",
-       LWZCIX:        "lwzcix",
-       LHZCIX:        "lhzcix",
-       LDCIX:         "ldcix",
-       STBCIX:        "stbcix",
-       STWCIX:        "stwcix",
-       STHCIX:        "sthcix",
-       STDCIX:        "stdcix",
-       TRECLAIMCC:    "treclaim.",
-       TRECHKPTCC:    "trechkpt.",
-       MTMSR:         "mtmsr",
-       MTMSRD:        "mtmsrd",
-       MFMSR:         "mfmsr",
-       SLBIE:         "slbie",
-       SLBIA:         "slbia",
-       SLBMTE:        "slbmte",
-       SLBMFEV:       "slbmfev",
-       SLBMFEE:       "slbmfee",
-       SLBFEECC:      "slbfee.",
-       MTSR:          "mtsr",
-       MTSRIN:        "mtsrin",
-       MFSR:          "mfsr",
-       MFSRIN:        "mfsrin",
-       TLBIE:         "tlbie",
-       TLBIEL:        "tlbiel",
-       TLBIA:         "tlbia",
-       TLBSYNC:       "tlbsync",
-       MSGSND:        "msgsnd",
-       MSGCLR:        "msgclr",
-       MSGSNDP:       "msgsndp",
-       MSGCLRP:       "msgclrp",
-       MTTMR:         "mttmr",
-       RFI:           "rfi",
-       RFCI:          "rfci",
-       RFDI:          "rfdi",
-       RFMCI:         "rfmci",
-       RFGI:          "rfgi",
-       EHPRIV:        "ehpriv",
-       MTDCR:         "mtdcr",
-       MTDCRX:        "mtdcrx",
-       MFDCR:         "mfdcr",
-       MFDCRX:        "mfdcrx",
-       WRTEE:         "wrtee",
-       WRTEEI:        "wrteei",
-       LBEPX:         "lbepx",
-       LHEPX:         "lhepx",
-       LWEPX:         "lwepx",
-       LDEPX:         "ldepx",
-       STBEPX:        "stbepx",
-       STHEPX:        "sthepx",
-       STWEPX:        "stwepx",
-       STDEPX:        "stdepx",
-       DCBSTEP:       "dcbstep",
-       DCBTEP:        "dcbtep",
-       DCBFEP:        "dcbfep",
-       DCBTSTEP:      "dcbtstep",
-       ICBIEP:        "icbiep",
-       DCBZEP:        "dcbzep",
-       LFDEPX:        "lfdepx",
-       STFDEPX:       "stfdepx",
-       EVLDDEPX:      "evlddepx",
-       EVSTDDEPX:     "evstddepx",
-       LVEPX:         "lvepx",
-       LVEPXL:        "lvepxl",
-       STVEPX:        "stvepx",
-       STVEPXL:       "stvepxl",
-       DCBI:          "dcbi",
-       DCBLQCC:       "dcblq.",
-       ICBLQCC:       "icblq.",
-       DCBTLS:        "dcbtls",
-       DCBTSTLS:      "dcbtstls",
-       ICBTLS:        "icbtls",
-       ICBLC:         "icblc",
-       DCBLC:         "dcblc",
-       TLBIVAX:       "tlbivax",
-       TLBILX:        "tlbilx",
-       TLBSX:         "tlbsx",
-       TLBSRXCC:      "tlbsrx.",
-       TLBRE:         "tlbre",
-       TLBWE:         "tlbwe",
-       DNH:           "dnh",
-       DCI:           "dci",
-       ICI:           "ici",
-       DCREAD:        "dcread",
-       ICREAD:        "icread",
-       MFPMR:         "mfpmr",
-       MTPMR:         "mtpmr",
-       ADDEX:         "addex",
-       DARN:          "darn",
-       MADDHD:        "maddhd",
-       MADDHDU:       "maddhdu",
-       MADDLD:        "maddld",
-       CMPRB:         "cmprb",
-       CMPEQB:        "cmpeqb",
-       EXTSWSLI:      "extswsli",
-       EXTSWSLICC:    "extswsli.",
-       MFVSRLD:       "mfvsrld",
-       MTVSRDD:       "mtvsrdd",
-       MTVSRWS:       "mtvsrws",
-       MCRXRX:        "mcrxrx",
-       COPY:          "copy",
-       PASTECC:       "paste.",
+       BRD:            "brd",
+       BRH:            "brh",
+       BRW:            "brw",
+       CFUGED:         "cfuged",
+       CNTLZDM:        "cntlzdm",
+       CNTTZDM:        "cnttzdm",
+       DCFFIXQQ:       "dcffixqq",
+       DCTFIXQQ:       "dctfixqq",
+       LXVKQ:          "lxvkq",
+       LXVP:           "lxvp",
+       LXVPX:          "lxvpx",
+       LXVRBX:         "lxvrbx",
+       LXVRDX:         "lxvrdx",
+       LXVRHX:         "lxvrhx",
+       LXVRWX:         "lxvrwx",
+       MTVSRBM:        "mtvsrbm",
+       MTVSRBMI:       "mtvsrbmi",
+       MTVSRDM:        "mtvsrdm",
+       MTVSRHM:        "mtvsrhm",
+       MTVSRQM:        "mtvsrqm",
+       MTVSRWM:        "mtvsrwm",
+       PADDI:          "paddi",
+       PDEPD:          "pdepd",
+       PEXTD:          "pextd",
+       PLBZ:           "plbz",
+       PLD:            "pld",
+       PLFD:           "plfd",
+       PLFS:           "plfs",
+       PLHA:           "plha",
+       PLHZ:           "plhz",
+       PLQ:            "plq",
+       PLWA:           "plwa",
+       PLWZ:           "plwz",
+       PLXSD:          "plxsd",
+       PLXSSP:         "plxssp",
+       PLXV:           "plxv",
+       PLXVP:          "plxvp",
+       PMXVBF16GER2:   "pmxvbf16ger2",
+       PMXVBF16GER2NN: "pmxvbf16ger2nn",
+       PMXVBF16GER2NP: "pmxvbf16ger2np",
+       PMXVBF16GER2PN: "pmxvbf16ger2pn",
+       PMXVBF16GER2PP: "pmxvbf16ger2pp",
+       PMXVF16GER2:    "pmxvf16ger2",
+       PMXVF16GER2NN:  "pmxvf16ger2nn",
+       PMXVF16GER2NP:  "pmxvf16ger2np",
+       PMXVF16GER2PN:  "pmxvf16ger2pn",
+       PMXVF16GER2PP:  "pmxvf16ger2pp",
+       PMXVF32GER:     "pmxvf32ger",
+       PMXVF32GERNN:   "pmxvf32gernn",
+       PMXVF32GERNP:   "pmxvf32gernp",
+       PMXVF32GERPN:   "pmxvf32gerpn",
+       PMXVF32GERPP:   "pmxvf32gerpp",
+       PMXVF64GER:     "pmxvf64ger",
+       PMXVF64GERNN:   "pmxvf64gernn",
+       PMXVF64GERNP:   "pmxvf64gernp",
+       PMXVF64GERPN:   "pmxvf64gerpn",
+       PMXVF64GERPP:   "pmxvf64gerpp",
+       PMXVI16GER2:    "pmxvi16ger2",
+       PMXVI16GER2PP:  "pmxvi16ger2pp",
+       PMXVI16GER2S:   "pmxvi16ger2s",
+       PMXVI16GER2SPP: "pmxvi16ger2spp",
+       PMXVI4GER8:     "pmxvi4ger8",
+       PMXVI4GER8PP:   "pmxvi4ger8pp",
+       PMXVI8GER4:     "pmxvi8ger4",
+       PMXVI8GER4PP:   "pmxvi8ger4pp",
+       PMXVI8GER4SPP:  "pmxvi8ger4spp",
+       PNOP:           "pnop",
+       PSTB:           "pstb",
+       PSTD:           "pstd",
+       PSTFD:          "pstfd",
+       PSTFS:          "pstfs",
+       PSTH:           "psth",
+       PSTQ:           "pstq",
+       PSTW:           "pstw",
+       PSTXSD:         "pstxsd",
+       PSTXSSP:        "pstxssp",
+       PSTXV:          "pstxv",
+       PSTXVP:         "pstxvp",
+       SETBC:          "setbc",
+       SETBCR:         "setbcr",
+       SETNBC:         "setnbc",
+       SETNBCR:        "setnbcr",
+       STXVP:          "stxvp",
+       STXVPX:         "stxvpx",
+       STXVRBX:        "stxvrbx",
+       STXVRDX:        "stxvrdx",
+       STXVRHX:        "stxvrhx",
+       STXVRWX:        "stxvrwx",
+       VCFUGED:        "vcfuged",
+       VCLRLB:         "vclrlb",
+       VCLRRB:         "vclrrb",
+       VCLZDM:         "vclzdm",
+       VCMPEQUQ:       "vcmpequq",
+       VCMPEQUQCC:     "vcmpequq.",
+       VCMPGTSQ:       "vcmpgtsq",
+       VCMPGTSQCC:     "vcmpgtsq.",
+       VCMPGTUQ:       "vcmpgtuq",
+       VCMPGTUQCC:     "vcmpgtuq.",
+       VCMPSQ:         "vcmpsq",
+       VCMPUQ:         "vcmpuq",
+       VCNTMBB:        "vcntmbb",
+       VCNTMBD:        "vcntmbd",
+       VCNTMBH:        "vcntmbh",
+       VCNTMBW:        "vcntmbw",
+       VCTZDM:         "vctzdm",
+       VDIVESD:        "vdivesd",
+       VDIVESQ:        "vdivesq",
+       VDIVESW:        "vdivesw",
+       VDIVEUD:        "vdiveud",
+       VDIVEUQ:        "vdiveuq",
+       VDIVEUW:        "vdiveuw",
+       VDIVSD:         "vdivsd",
+       VDIVSQ:         "vdivsq",
+       VDIVSW:         "vdivsw",
+       VDIVUD:         "vdivud",
+       VDIVUQ:         "vdivuq",
+       VDIVUW:         "vdivuw",
+       VEXPANDBM:      "vexpandbm",
+       VEXPANDDM:      "vexpanddm",
+       VEXPANDHM:      "vexpandhm",
+       VEXPANDQM:      "vexpandqm",
+       VEXPANDWM:      "vexpandwm",
+       VEXTDDVLX:      "vextddvlx",
+       VEXTDDVRX:      "vextddvrx",
+       VEXTDUBVLX:     "vextdubvlx",
+       VEXTDUBVRX:     "vextdubvrx",
+       VEXTDUHVLX:     "vextduhvlx",
+       VEXTDUHVRX:     "vextduhvrx",
+       VEXTDUWVLX:     "vextduwvlx",
+       VEXTDUWVRX:     "vextduwvrx",
+       VEXTRACTBM:     "vextractbm",
+       VEXTRACTDM:     "vextractdm",
+       VEXTRACTHM:     "vextracthm",
+       VEXTRACTQM:     "vextractqm",
+       VEXTRACTWM:     "vextractwm",
+       VEXTSD2Q:       "vextsd2q",
+       VGNB:           "vgnb",
+       VINSBLX:        "vinsblx",
+       VINSBRX:        "vinsbrx",
+       VINSBVLX:       "vinsbvlx",
+       VINSBVRX:       "vinsbvrx",
+       VINSD:          "vinsd",
+       VINSDLX:        "vinsdlx",
+       VINSDRX:        "vinsdrx",
+       VINSHLX:        "vinshlx",
+       VINSHRX:        "vinshrx",
+       VINSHVLX:       "vinshvlx",
+       VINSHVRX:       "vinshvrx",
+       VINSW:          "vinsw",
+       VINSWLX:        "vinswlx",
+       VINSWRX:        "vinswrx",
+       VINSWVLX:       "vinswvlx",
+       VINSWVRX:       "vinswvrx",
+       VMODSD:         "vmodsd",
+       VMODSQ:         "vmodsq",
+       VMODSW:         "vmodsw",
+       VMODUD:         "vmodud",
+       VMODUQ:         "vmoduq",
+       VMODUW:         "vmoduw",
+       VMSUMCUD:       "vmsumcud",
+       VMULESD:        "vmulesd",
+       VMULEUD:        "vmuleud",
+       VMULHSD:        "vmulhsd",
+       VMULHSW:        "vmulhsw",
+       VMULHUD:        "vmulhud",
+       VMULHUW:        "vmulhuw",
+       VMULLD:         "vmulld",
+       VMULOSD:        "vmulosd",
+       VMULOUD:        "vmuloud",
+       VPDEPD:         "vpdepd",
+       VPEXTD:         "vpextd",
+       VRLQ:           "vrlq",
+       VRLQMI:         "vrlqmi",
+       VRLQNM:         "vrlqnm",
+       VSLDBI:         "vsldbi",
+       VSLQ:           "vslq",
+       VSRAQ:          "vsraq",
+       VSRDBI:         "vsrdbi",
+       VSRQ:           "vsrq",
+       VSTRIBL:        "vstribl",
+       VSTRIBLCC:      "vstribl.",
+       VSTRIBR:        "vstribr",
+       VSTRIBRCC:      "vstribr.",
+       VSTRIHL:        "vstrihl",
+       VSTRIHLCC:      "vstrihl.",
+       VSTRIHR:        "vstrihr",
+       VSTRIHRCC:      "vstrihr.",
+       XSCMPEQQP:      "xscmpeqqp",
+       XSCMPGEQP:      "xscmpgeqp",
+       XSCMPGTQP:      "xscmpgtqp",
+       XSCVQPSQZ:      "xscvqpsqz",
+       XSCVQPUQZ:      "xscvqpuqz",
+       XSCVSQQP:       "xscvsqqp",
+       XSCVUQQP:       "xscvuqqp",
+       XSMAXCQP:       "xsmaxcqp",
+       XSMINCQP:       "xsmincqp",
+       XVBF16GER2:     "xvbf16ger2",
+       XVBF16GER2NN:   "xvbf16ger2nn",
+       XVBF16GER2NP:   "xvbf16ger2np",
+       XVBF16GER2PN:   "xvbf16ger2pn",
+       XVBF16GER2PP:   "xvbf16ger2pp",
+       XVCVBF16SPN:    "xvcvbf16spn",
+       XVCVSPBF16:     "xvcvspbf16",
+       XVF16GER2:      "xvf16ger2",
+       XVF16GER2NN:    "xvf16ger2nn",
+       XVF16GER2NP:    "xvf16ger2np",
+       XVF16GER2PN:    "xvf16ger2pn",
+       XVF16GER2PP:    "xvf16ger2pp",
+       XVF32GER:       "xvf32ger",
+       XVF32GERNN:     "xvf32gernn",
+       XVF32GERNP:     "xvf32gernp",
+       XVF32GERPN:     "xvf32gerpn",
+       XVF32GERPP:     "xvf32gerpp",
+       XVF64GER:       "xvf64ger",
+       XVF64GERNN:     "xvf64gernn",
+       XVF64GERNP:     "xvf64gernp",
+       XVF64GERPN:     "xvf64gerpn",
+       XVF64GERPP:     "xvf64gerpp",
+       XVI16GER2:      "xvi16ger2",
+       XVI16GER2PP:    "xvi16ger2pp",
+       XVI16GER2S:     "xvi16ger2s",
+       XVI16GER2SPP:   "xvi16ger2spp",
+       XVI4GER8:       "xvi4ger8",
+       XVI4GER8PP:     "xvi4ger8pp",
+       XVI8GER4:       "xvi8ger4",
+       XVI8GER4PP:     "xvi8ger4pp",
+       XVI8GER4SPP:    "xvi8ger4spp",
+       XVTLSBB:        "xvtlsbb",
+       XXBLENDVB:      "xxblendvb",
+       XXBLENDVD:      "xxblendvd",
+       XXBLENDVH:      "xxblendvh",
+       XXBLENDVW:      "xxblendvw",
+       XXEVAL:         "xxeval",
+       XXGENPCVBM:     "xxgenpcvbm",
+       XXGENPCVDM:     "xxgenpcvdm",
+       XXGENPCVHM:     "xxgenpcvhm",
+       XXGENPCVWM:     "xxgenpcvwm",
+       XXMFACC:        "xxmfacc",
+       XXMTACC:        "xxmtacc",
+       XXPERMX:        "xxpermx",
+       XXSETACCZ:      "xxsetaccz",
+       XXSPLTI32DX:    "xxsplti32dx",
+       XXSPLTIDP:      "xxspltidp",
+       XXSPLTIW:       "xxspltiw",
+       MSGCLRU:        "msgclru",
+       MSGSNDU:        "msgsndu",
+       URFID:          "urfid",
+       ADDEX:          "addex",
+       MFFSCDRN:       "mffscdrn",
+       MFFSCDRNI:      "mffscdrni",
+       MFFSCE:         "mffsce",
+       MFFSCRN:        "mffscrn",
+       MFFSCRNI:       "mffscrni",
+       MFFSL:          "mffsl",
+       SLBIAG:         "slbiag",
+       VMSUMUDM:       "vmsumudm",
+       ADDPCIS:        "addpcis",
+       BCDCFNCC:       "bcdcfn.",
+       BCDCFSQCC:      "bcdcfsq.",
+       BCDCFZCC:       "bcdcfz.",
+       BCDCPSGNCC:     "bcdcpsgn.",
+       BCDCTNCC:       "bcdctn.",
+       BCDCTSQCC:      "bcdctsq.",
+       BCDCTZCC:       "bcdctz.",
+       BCDSCC:         "bcds.",
+       BCDSETSGNCC:    "bcdsetsgn.",
+       BCDSRCC:        "bcdsr.",
+       BCDTRUNCCC:     "bcdtrunc.",
+       BCDUSCC:        "bcdus.",
+       BCDUTRUNCCC:    "bcdutrunc.",
+       CMPEQB:         "cmpeqb",
+       CMPRB:          "cmprb",
+       CNTTZD:         "cnttzd",
+       CNTTZDCC:       "cnttzd.",
+       CNTTZW:         "cnttzw",
+       CNTTZWCC:       "cnttzw.",
+       COPY:           "copy",
+       CPABORT:        "cpabort",
+       DARN:           "darn",
+       DTSTSFI:        "dtstsfi",
+       DTSTSFIQ:       "dtstsfiq",
+       EXTSWSLI:       "extswsli",
+       EXTSWSLICC:     "extswsli.",
+       LDAT:           "ldat",
+       LWAT:           "lwat",
+       LXSD:           "lxsd",
+       LXSIBZX:        "lxsibzx",
+       LXSIHZX:        "lxsihzx",
+       LXSSP:          "lxssp",
+       LXV:            "lxv",
+       LXVB16X:        "lxvb16x",
+       LXVH8X:         "lxvh8x",
+       LXVL:           "lxvl",
+       LXVLL:          "lxvll",
+       LXVWSX:         "lxvwsx",
+       LXVX:           "lxvx",
+       MADDHD:         "maddhd",
+       MADDHDU:        "maddhdu",
+       MADDLD:         "maddld",
+       MCRXRX:         "mcrxrx",
+       MFVSRLD:        "mfvsrld",
+       MODSD:          "modsd",
+       MODSW:          "modsw",
+       MODUD:          "modud",
+       MODUW:          "moduw",
+       MSGSYNC:        "msgsync",
+       MTVSRDD:        "mtvsrdd",
+       MTVSRWS:        "mtvsrws",
+       PASTECC:        "paste.",
+       SETB:           "setb",
+       SLBIEG:         "slbieg",
+       SLBSYNC:        "slbsync",
+       STDAT:          "stdat",
+       STOP:           "stop",
+       STWAT:          "stwat",
+       STXSD:          "stxsd",
+       STXSIBX:        "stxsibx",
+       STXSIHX:        "stxsihx",
+       STXSSP:         "stxssp",
+       STXV:           "stxv",
+       STXVB16X:       "stxvb16x",
+       STXVH8X:        "stxvh8x",
+       STXVL:          "stxvl",
+       STXVLL:         "stxvll",
+       STXVX:          "stxvx",
+       VABSDUB:        "vabsdub",
+       VABSDUH:        "vabsduh",
+       VABSDUW:        "vabsduw",
+       VBPERMD:        "vbpermd",
+       VCLZLSBB:       "vclzlsbb",
+       VCMPNEB:        "vcmpneb",
+       VCMPNEBCC:      "vcmpneb.",
+       VCMPNEH:        "vcmpneh",
+       VCMPNEHCC:      "vcmpneh.",
+       VCMPNEW:        "vcmpnew",
+       VCMPNEWCC:      "vcmpnew.",
+       VCMPNEZB:       "vcmpnezb",
+       VCMPNEZBCC:     "vcmpnezb.",
+       VCMPNEZH:       "vcmpnezh",
+       VCMPNEZHCC:     "vcmpnezh.",
+       VCMPNEZW:       "vcmpnezw",
+       VCMPNEZWCC:     "vcmpnezw.",
+       VCTZB:          "vctzb",
+       VCTZD:          "vctzd",
+       VCTZH:          "vctzh",
+       VCTZLSBB:       "vctzlsbb",
+       VCTZW:          "vctzw",
+       VEXTRACTD:      "vextractd",
+       VEXTRACTUB:     "vextractub",
+       VEXTRACTUH:     "vextractuh",
+       VEXTRACTUW:     "vextractuw",
+       VEXTSB2D:       "vextsb2d",
+       VEXTSB2W:       "vextsb2w",
+       VEXTSH2D:       "vextsh2d",
+       VEXTSH2W:       "vextsh2w",
+       VEXTSW2D:       "vextsw2d",
+       VEXTUBLX:       "vextublx",
+       VEXTUBRX:       "vextubrx",
+       VEXTUHLX:       "vextuhlx",
+       VEXTUHRX:       "vextuhrx",
+       VEXTUWLX:       "vextuwlx",
+       VEXTUWRX:       "vextuwrx",
+       VINSERTB:       "vinsertb",
+       VINSERTD:       "vinsertd",
+       VINSERTH:       "vinserth",
+       VINSERTW:       "vinsertw",
+       VMUL10CUQ:      "vmul10cuq",
+       VMUL10ECUQ:     "vmul10ecuq",
+       VMUL10EUQ:      "vmul10euq",
+       VMUL10UQ:       "vmul10uq",
+       VNEGD:          "vnegd",
+       VNEGW:          "vnegw",
+       VPERMR:         "vpermr",
+       VPRTYBD:        "vprtybd",
+       VPRTYBQ:        "vprtybq",
+       VPRTYBW:        "vprtybw",
+       VRLDMI:         "vrldmi",
+       VRLDNM:         "vrldnm",
+       VRLWMI:         "vrlwmi",
+       VRLWNM:         "vrlwnm",
+       VSLV:           "vslv",
+       VSRV:           "vsrv",
+       WAIT:           "wait",
+       XSABSQP:        "xsabsqp",
+       XSADDQP:        "xsaddqp",
+       XSADDQPO:       "xsaddqpo",
+       XSCMPEQDP:      "xscmpeqdp",
+       XSCMPEXPDP:     "xscmpexpdp",
+       XSCMPEXPQP:     "xscmpexpqp",
+       XSCMPGEDP:      "xscmpgedp",
+       XSCMPGTDP:      "xscmpgtdp",
+       XSCMPOQP:       "xscmpoqp",
+       XSCMPUQP:       "xscmpuqp",
+       XSCPSGNQP:      "xscpsgnqp",
+       XSCVDPHP:       "xscvdphp",
+       XSCVDPQP:       "xscvdpqp",
+       XSCVHPDP:       "xscvhpdp",
+       XSCVQPDP:       "xscvqpdp",
+       XSCVQPDPO:      "xscvqpdpo",
+       XSCVQPSDZ:      "xscvqpsdz",
+       XSCVQPSWZ:      "xscvqpswz",
+       XSCVQPUDZ:      "xscvqpudz",
+       XSCVQPUWZ:      "xscvqpuwz",
+       XSCVSDQP:       "xscvsdqp",
+       XSCVUDQP:       "xscvudqp",
+       XSDIVQP:        "xsdivqp",
+       XSDIVQPO:       "xsdivqpo",
+       XSIEXPDP:       "xsiexpdp",
+       XSIEXPQP:       "xsiexpqp",
+       XSMADDQP:       "xsmaddqp",
+       XSMADDQPO:      "xsmaddqpo",
+       XSMAXCDP:       "xsmaxcdp",
+       XSMAXJDP:       "xsmaxjdp",
+       XSMINCDP:       "xsmincdp",
+       XSMINJDP:       "xsminjdp",
+       XSMSUBQP:       "xsmsubqp",
+       XSMSUBQPO:      "xsmsubqpo",
+       XSMULQP:        "xsmulqp",
+       XSMULQPO:       "xsmulqpo",
+       XSNABSQP:       "xsnabsqp",
+       XSNEGQP:        "xsnegqp",
+       XSNMADDQP:      "xsnmaddqp",
+       XSNMADDQPO:     "xsnmaddqpo",
+       XSNMSUBQP:      "xsnmsubqp",
+       XSNMSUBQPO:     "xsnmsubqpo",
+       XSRQPI:         "xsrqpi",
+       XSRQPIX:        "xsrqpix",
+       XSRQPXP:        "xsrqpxp",
+       XSSQRTQP:       "xssqrtqp",
+       XSSQRTQPO:      "xssqrtqpo",
+       XSSUBQP:        "xssubqp",
+       XSSUBQPO:       "xssubqpo",
+       XSTSTDCDP:      "xststdcdp",
+       XSTSTDCQP:      "xststdcqp",
+       XSTSTDCSP:      "xststdcsp",
+       XSXEXPDP:       "xsxexpdp",
+       XSXEXPQP:       "xsxexpqp",
+       XSXSIGDP:       "xsxsigdp",
+       XSXSIGQP:       "xsxsigqp",
+       XVCVHPSP:       "xvcvhpsp",
+       XVCVSPHP:       "xvcvsphp",
+       XVIEXPDP:       "xviexpdp",
+       XVIEXPSP:       "xviexpsp",
+       XVTSTDCDP:      "xvtstdcdp",
+       XVTSTDCSP:      "xvtstdcsp",
+       XVXEXPDP:       "xvxexpdp",
+       XVXEXPSP:       "xvxexpsp",
+       XVXSIGDP:       "xvxsigdp",
+       XVXSIGSP:       "xvxsigsp",
+       XXBRD:          "xxbrd",
+       XXBRH:          "xxbrh",
+       XXBRQ:          "xxbrq",
+       XXBRW:          "xxbrw",
+       XXEXTRACTUW:    "xxextractuw",
+       XXINSERTW:      "xxinsertw",
+       XXPERM:         "xxperm",
+       XXPERMR:        "xxpermr",
+       XXSPLTIB:       "xxspltib",
+       BCDADDCC:       "bcdadd.",
+       BCDSUBCC:       "bcdsub.",
+       BCTAR:          "bctar",
+       BCTARL:         "bctarl",
+       CLRBHRB:        "clrbhrb",
+       FMRGEW:         "fmrgew",
+       FMRGOW:         "fmrgow",
+       ICBT:           "icbt",
+       LQARX:          "lqarx",
+       LXSIWAX:        "lxsiwax",
+       LXSIWZX:        "lxsiwzx",
+       LXSSPX:         "lxsspx",
+       MFBHRBE:        "mfbhrbe",
+       MFVSRD:         "mfvsrd",
+       MFVSRWZ:        "mfvsrwz",
+       MSGCLR:         "msgclr",
+       MSGCLRP:        "msgclrp",
+       MSGSND:         "msgsnd",
+       MSGSNDP:        "msgsndp",
+       MTVSRD:         "mtvsrd",
+       MTVSRWA:        "mtvsrwa",
+       MTVSRWZ:        "mtvsrwz",
+       RFEBB:          "rfebb",
+       STQCXCC:        "stqcx.",
+       STXSIWX:        "stxsiwx",
+       STXSSPX:        "stxsspx",
+       VADDCUQ:        "vaddcuq",
+       VADDECUQ:       "vaddecuq",
+       VADDEUQM:       "vaddeuqm",
+       VADDUDM:        "vaddudm",
+       VADDUQM:        "vadduqm",
+       VBPERMQ:        "vbpermq",
+       VCIPHER:        "vcipher",
+       VCIPHERLAST:    "vcipherlast",
+       VCLZB:          "vclzb",
+       VCLZD:          "vclzd",
+       VCLZH:          "vclzh",
+       VCLZW:          "vclzw",
+       VCMPEQUD:       "vcmpequd",
+       VCMPEQUDCC:     "vcmpequd.",
+       VCMPGTSD:       "vcmpgtsd",
+       VCMPGTSDCC:     "vcmpgtsd.",
+       VCMPGTUD:       "vcmpgtud",
+       VCMPGTUDCC:     "vcmpgtud.",
+       VEQV:           "veqv",
+       VGBBD:          "vgbbd",
+       VMAXSD:         "vmaxsd",
+       VMAXUD:         "vmaxud",
+       VMINSD:         "vminsd",
+       VMINUD:         "vminud",
+       VMRGEW:         "vmrgew",
+       VMRGOW:         "vmrgow",
+       VMULESW:        "vmulesw",
+       VMULEUW:        "vmuleuw",
+       VMULOSW:        "vmulosw",
+       VMULOUW:        "vmulouw",
+       VMULUWM:        "vmuluwm",
+       VNAND:          "vnand",
+       VNCIPHER:       "vncipher",
+       VNCIPHERLAST:   "vncipherlast",
+       VORC:           "vorc",
+       VPERMXOR:       "vpermxor",
+       VPKSDSS:        "vpksdss",
+       VPKSDUS:        "vpksdus",
+       VPKUDUM:        "vpkudum",
+       VPKUDUS:        "vpkudus",
+       VPMSUMB:        "vpmsumb",
+       VPMSUMD:        "vpmsumd",
+       VPMSUMH:        "vpmsumh",
+       VPMSUMW:        "vpmsumw",
+       VPOPCNTB:       "vpopcntb",
+       VPOPCNTD:       "vpopcntd",
+       VPOPCNTH:       "vpopcnth",
+       VPOPCNTW:       "vpopcntw",
+       VRLD:           "vrld",
+       VSBOX:          "vsbox",
+       VSHASIGMAD:     "vshasigmad",
+       VSHASIGMAW:     "vshasigmaw",
+       VSLD:           "vsld",
+       VSRAD:          "vsrad",
+       VSRD:           "vsrd",
+       VSUBCUQ:        "vsubcuq",
+       VSUBECUQ:       "vsubecuq",
+       VSUBEUQM:       "vsubeuqm",
+       VSUBUDM:        "vsubudm",
+       VSUBUQM:        "vsubuqm",
+       VUPKHSW:        "vupkhsw",
+       VUPKLSW:        "vupklsw",
+       XSADDSP:        "xsaddsp",
+       XSCVDPSPN:      "xscvdpspn",
+       XSCVSPDPN:      "xscvspdpn",
+       XSCVSXDSP:      "xscvsxdsp",
+       XSCVUXDSP:      "xscvuxdsp",
+       XSDIVSP:        "xsdivsp",
+       XSMADDASP:      "xsmaddasp",
+       XSMADDMSP:      "xsmaddmsp",
+       XSMSUBASP:      "xsmsubasp",
+       XSMSUBMSP:      "xsmsubmsp",
+       XSMULSP:        "xsmulsp",
+       XSNMADDASP:     "xsnmaddasp",
+       XSNMADDMSP:     "xsnmaddmsp",
+       XSNMSUBASP:     "xsnmsubasp",
+       XSNMSUBMSP:     "xsnmsubmsp",
+       XSRESP:         "xsresp",
+       XSRSP:          "xsrsp",
+       XSRSQRTESP:     "xsrsqrtesp",
+       XSSQRTSP:       "xssqrtsp",
+       XSSUBSP:        "xssubsp",
+       XXLEQV:         "xxleqv",
+       XXLNAND:        "xxlnand",
+       XXLORC:         "xxlorc",
+       ADDG6S:         "addg6s",
+       BPERMD:         "bpermd",
+       CBCDTD:         "cbcdtd",
+       CDTBCD:         "cdtbcd",
+       DCFFIX:         "dcffix",
+       DCFFIXCC:       "dcffix.",
+       DIVDE:          "divde",
+       DIVDECC:        "divde.",
+       DIVDEO:         "divdeo",
+       DIVDEOCC:       "divdeo.",
+       DIVDEU:         "divdeu",
+       DIVDEUCC:       "divdeu.",
+       DIVDEUO:        "divdeuo",
+       DIVDEUOCC:      "divdeuo.",
+       DIVWE:          "divwe",
+       DIVWECC:        "divwe.",
+       DIVWEO:         "divweo",
+       DIVWEOCC:       "divweo.",
+       DIVWEU:         "divweu",
+       DIVWEUCC:       "divweu.",
+       DIVWEUO:        "divweuo",
+       DIVWEUOCC:      "divweuo.",
+       FCFIDS:         "fcfids",
+       FCFIDSCC:       "fcfids.",
+       FCFIDU:         "fcfidu",
+       FCFIDUCC:       "fcfidu.",
+       FCFIDUS:        "fcfidus",
+       FCFIDUSCC:      "fcfidus.",
+       FCTIDU:         "fctidu",
+       FCTIDUCC:       "fctidu.",
+       FCTIDUZ:        "fctiduz",
+       FCTIDUZCC:      "fctiduz.",
+       FCTIWU:         "fctiwu",
+       FCTIWUCC:       "fctiwu.",
+       FCTIWUZ:        "fctiwuz",
+       FCTIWUZCC:      "fctiwuz.",
+       FTDIV:          "ftdiv",
+       FTSQRT:         "ftsqrt",
+       LBARX:          "lbarx",
+       LDBRX:          "ldbrx",
+       LFIWZX:         "lfiwzx",
+       LHARX:          "lharx",
+       LXSDX:          "lxsdx",
+       LXVD2X:         "lxvd2x",
+       LXVDSX:         "lxvdsx",
+       LXVW4X:         "lxvw4x",
+       POPCNTD:        "popcntd",
+       POPCNTW:        "popcntw",
+       STBCXCC:        "stbcx.",
+       STDBRX:         "stdbrx",
+       STHCXCC:        "sthcx.",
+       STXSDX:         "stxsdx",
+       STXVD2X:        "stxvd2x",
+       STXVW4X:        "stxvw4x",
+       XSABSDP:        "xsabsdp",
+       XSADDDP:        "xsadddp",
+       XSCMPODP:       "xscmpodp",
+       XSCMPUDP:       "xscmpudp",
+       XSCPSGNDP:      "xscpsgndp",
+       XSCVDPSP:       "xscvdpsp",
+       XSCVDPSXDS:     "xscvdpsxds",
+       XSCVDPSXWS:     "xscvdpsxws",
+       XSCVDPUXDS:     "xscvdpuxds",
+       XSCVDPUXWS:     "xscvdpuxws",
+       XSCVSPDP:       "xscvspdp",
+       XSCVSXDDP:      "xscvsxddp",
+       XSCVUXDDP:      "xscvuxddp",
+       XSDIVDP:        "xsdivdp",
+       XSMADDADP:      "xsmaddadp",
+       XSMADDMDP:      "xsmaddmdp",
+       XSMAXDP:        "xsmaxdp",
+       XSMINDP:        "xsmindp",
+       XSMSUBADP:      "xsmsubadp",
+       XSMSUBMDP:      "xsmsubmdp",
+       XSMULDP:        "xsmuldp",
+       XSNABSDP:       "xsnabsdp",
+       XSNEGDP:        "xsnegdp",
+       XSNMADDADP:     "xsnmaddadp",
+       XSNMADDMDP:     "xsnmaddmdp",
+       XSNMSUBADP:     "xsnmsubadp",
+       XSNMSUBMDP:     "xsnmsubmdp",
+       XSRDPI:         "xsrdpi",
+       XSRDPIC:        "xsrdpic",
+       XSRDPIM:        "xsrdpim",
+       XSRDPIP:        "xsrdpip",
+       XSRDPIZ:        "xsrdpiz",
+       XSREDP:         "xsredp",
+       XSRSQRTEDP:     "xsrsqrtedp",
+       XSSQRTDP:       "xssqrtdp",
+       XSSUBDP:        "xssubdp",
+       XSTDIVDP:       "xstdivdp",
+       XSTSQRTDP:      "xstsqrtdp",
+       XVABSDP:        "xvabsdp",
+       XVABSSP:        "xvabssp",
+       XVADDDP:        "xvadddp",
+       XVADDSP:        "xvaddsp",
+       XVCMPEQDP:      "xvcmpeqdp",
+       XVCMPEQDPCC:    "xvcmpeqdp.",
+       XVCMPEQSP:      "xvcmpeqsp",
+       XVCMPEQSPCC:    "xvcmpeqsp.",
+       XVCMPGEDP:      "xvcmpgedp",
+       XVCMPGEDPCC:    "xvcmpgedp.",
+       XVCMPGESP:      "xvcmpgesp",
+       XVCMPGESPCC:    "xvcmpgesp.",
+       XVCMPGTDP:      "xvcmpgtdp",
+       XVCMPGTDPCC:    "xvcmpgtdp.",
+       XVCMPGTSP:      "xvcmpgtsp",
+       XVCMPGTSPCC:    "xvcmpgtsp.",
+       XVCPSGNDP:      "xvcpsgndp",
+       XVCPSGNSP:      "xvcpsgnsp",
+       XVCVDPSP:       "xvcvdpsp",
+       XVCVDPSXDS:     "xvcvdpsxds",
+       XVCVDPSXWS:     "xvcvdpsxws",
+       XVCVDPUXDS:     "xvcvdpuxds",
+       XVCVDPUXWS:     "xvcvdpuxws",
+       XVCVSPDP:       "xvcvspdp",
+       XVCVSPSXDS:     "xvcvspsxds",
+       XVCVSPSXWS:     "xvcvspsxws",
+       XVCVSPUXDS:     "xvcvspuxds",
+       XVCVSPUXWS:     "xvcvspuxws",
+       XVCVSXDDP:      "xvcvsxddp",
+       XVCVSXDSP:      "xvcvsxdsp",
+       XVCVSXWDP:      "xvcvsxwdp",
+       XVCVSXWSP:      "xvcvsxwsp",
+       XVCVUXDDP:      "xvcvuxddp",
+       XVCVUXDSP:      "xvcvuxdsp",
+       XVCVUXWDP:      "xvcvuxwdp",
+       XVCVUXWSP:      "xvcvuxwsp",
+       XVDIVDP:        "xvdivdp",
+       XVDIVSP:        "xvdivsp",
+       XVMADDADP:      "xvmaddadp",
+       XVMADDASP:      "xvmaddasp",
+       XVMADDMDP:      "xvmaddmdp",
+       XVMADDMSP:      "xvmaddmsp",
+       XVMAXDP:        "xvmaxdp",
+       XVMAXSP:        "xvmaxsp",
+       XVMINDP:        "xvmindp",
+       XVMINSP:        "xvminsp",
+       XVMSUBADP:      "xvmsubadp",
+       XVMSUBASP:      "xvmsubasp",
+       XVMSUBMDP:      "xvmsubmdp",
+       XVMSUBMSP:      "xvmsubmsp",
+       XVMULDP:        "xvmuldp",
+       XVMULSP:        "xvmulsp",
+       XVNABSDP:       "xvnabsdp",
+       XVNABSSP:       "xvnabssp",
+       XVNEGDP:        "xvnegdp",
+       XVNEGSP:        "xvnegsp",
+       XVNMADDADP:     "xvnmaddadp",
+       XVNMADDASP:     "xvnmaddasp",
+       XVNMADDMDP:     "xvnmaddmdp",
+       XVNMADDMSP:     "xvnmaddmsp",
+       XVNMSUBADP:     "xvnmsubadp",
+       XVNMSUBASP:     "xvnmsubasp",
+       XVNMSUBMDP:     "xvnmsubmdp",
+       XVNMSUBMSP:     "xvnmsubmsp",
+       XVRDPI:         "xvrdpi",
+       XVRDPIC:        "xvrdpic",
+       XVRDPIM:        "xvrdpim",
+       XVRDPIP:        "xvrdpip",
+       XVRDPIZ:        "xvrdpiz",
+       XVREDP:         "xvredp",
+       XVRESP:         "xvresp",
+       XVRSPI:         "xvrspi",
+       XVRSPIC:        "xvrspic",
+       XVRSPIM:        "xvrspim",
+       XVRSPIP:        "xvrspip",
+       XVRSPIZ:        "xvrspiz",
+       XVRSQRTEDP:     "xvrsqrtedp",
+       XVRSQRTESP:     "xvrsqrtesp",
+       XVSQRTDP:       "xvsqrtdp",
+       XVSQRTSP:       "xvsqrtsp",
+       XVSUBDP:        "xvsubdp",
+       XVSUBSP:        "xvsubsp",
+       XVTDIVDP:       "xvtdivdp",
+       XVTDIVSP:       "xvtdivsp",
+       XVTSQRTDP:      "xvtsqrtdp",
+       XVTSQRTSP:      "xvtsqrtsp",
+       XXLAND:         "xxland",
+       XXLANDC:        "xxlandc",
+       XXLNOR:         "xxlnor",
+       XXLOR:          "xxlor",
+       XXLXOR:         "xxlxor",
+       XXMRGHW:        "xxmrghw",
+       XXMRGLW:        "xxmrglw",
+       XXPERMDI:       "xxpermdi",
+       XXSEL:          "xxsel",
+       XXSLDWI:        "xxsldwi",
+       XXSPLTW:        "xxspltw",
+       CMPB:           "cmpb",
+       DADD:           "dadd",
+       DADDCC:         "dadd.",
+       DADDQ:          "daddq",
+       DADDQCC:        "daddq.",
+       DCFFIXQ:        "dcffixq",
+       DCFFIXQCC:      "dcffixq.",
+       DCMPO:          "dcmpo",
+       DCMPOQ:         "dcmpoq",
+       DCMPU:          "dcmpu",
+       DCMPUQ:         "dcmpuq",
+       DCTDP:          "dctdp",
+       DCTDPCC:        "dctdp.",
+       DCTFIX:         "dctfix",
+       DCTFIXCC:       "dctfix.",
+       DCTFIXQ:        "dctfixq",
+       DCTFIXQCC:      "dctfixq.",
+       DCTQPQ:         "dctqpq",
+       DCTQPQCC:       "dctqpq.",
+       DDEDPD:         "ddedpd",
+       DDEDPDCC:       "ddedpd.",
+       DDEDPDQ:        "ddedpdq",
+       DDEDPDQCC:      "ddedpdq.",
+       DDIV:           "ddiv",
+       DDIVCC:         "ddiv.",
+       DDIVQ:          "ddivq",
+       DDIVQCC:        "ddivq.",
+       DENBCD:         "denbcd",
+       DENBCDCC:       "denbcd.",
+       DENBCDQ:        "denbcdq",
+       DENBCDQCC:      "denbcdq.",
+       DIEX:           "diex",
+       DIEXCC:         "diex.",
+       DIEXQCC:        "diexq.",
+       DIEXQ:          "diexq",
+       DMUL:           "dmul",
+       DMULCC:         "dmul.",
+       DMULQ:          "dmulq",
+       DMULQCC:        "dmulq.",
+       DQUA:           "dqua",
+       DQUACC:         "dqua.",
+       DQUAI:          "dquai",
+       DQUAICC:        "dquai.",
+       DQUAIQ:         "dquaiq",
+       DQUAIQCC:       "dquaiq.",
+       DQUAQ:          "dquaq",
+       DQUAQCC:        "dquaq.",
+       DRDPQ:          "drdpq",
+       DRDPQCC:        "drdpq.",
+       DRINTN:         "drintn",
+       DRINTNCC:       "drintn.",
+       DRINTNQ:        "drintnq",
+       DRINTNQCC:      "drintnq.",
+       DRINTX:         "drintx",
+       DRINTXCC:       "drintx.",
+       DRINTXQ:        "drintxq",
+       DRINTXQCC:      "drintxq.",
+       DRRND:          "drrnd",
+       DRRNDCC:        "drrnd.",
+       DRRNDQ:         "drrndq",
+       DRRNDQCC:       "drrndq.",
+       DRSP:           "drsp",
+       DRSPCC:         "drsp.",
+       DSCLI:          "dscli",
+       DSCLICC:        "dscli.",
+       DSCLIQ:         "dscliq",
+       DSCLIQCC:       "dscliq.",
+       DSCRI:          "dscri",
+       DSCRICC:        "dscri.",
+       DSCRIQ:         "dscriq",
+       DSCRIQCC:       "dscriq.",
+       DSUB:           "dsub",
+       DSUBCC:         "dsub.",
+       DSUBQ:          "dsubq",
+       DSUBQCC:        "dsubq.",
+       DTSTDC:         "dtstdc",
+       DTSTDCQ:        "dtstdcq",
+       DTSTDG:         "dtstdg",
+       DTSTDGQ:        "dtstdgq",
+       DTSTEX:         "dtstex",
+       DTSTEXQ:        "dtstexq",
+       DTSTSF:         "dtstsf",
+       DTSTSFQ:        "dtstsfq",
+       DXEX:           "dxex",
+       DXEXCC:         "dxex.",
+       DXEXQ:          "dxexq",
+       DXEXQCC:        "dxexq.",
+       FCPSGN:         "fcpsgn",
+       FCPSGNCC:       "fcpsgn.",
+       LBZCIX:         "lbzcix",
+       LDCIX:          "ldcix",
+       LFDP:           "lfdp",
+       LFDPX:          "lfdpx",
+       LFIWAX:         "lfiwax",
+       LHZCIX:         "lhzcix",
+       LWZCIX:         "lwzcix",
+       PRTYD:          "prtyd",
+       PRTYW:          "prtyw",
+       SLBFEECC:       "slbfee.",
+       STBCIX:         "stbcix",
+       STDCIX:         "stdcix",
+       STFDP:          "stfdp",
+       STFDPX:         "stfdpx",
+       STHCIX:         "sthcix",
+       STWCIX:         "stwcix",
+       ISEL:           "isel",
+       LVEBX:          "lvebx",
+       LVEHX:          "lvehx",
+       LVEWX:          "lvewx",
+       LVSL:           "lvsl",
+       LVSR:           "lvsr",
+       LVX:            "lvx",
+       LVXL:           "lvxl",
+       MFVSCR:         "mfvscr",
+       MTVSCR:         "mtvscr",
+       STVEBX:         "stvebx",
+       STVEHX:         "stvehx",
+       STVEWX:         "stvewx",
+       STVX:           "stvx",
+       STVXL:          "stvxl",
+       TLBIEL:         "tlbiel",
+       VADDCUW:        "vaddcuw",
+       VADDFP:         "vaddfp",
+       VADDSBS:        "vaddsbs",
+       VADDSHS:        "vaddshs",
+       VADDSWS:        "vaddsws",
+       VADDUBM:        "vaddubm",
+       VADDUBS:        "vaddubs",
+       VADDUHM:        "vadduhm",
+       VADDUHS:        "vadduhs",
+       VADDUWM:        "vadduwm",
+       VADDUWS:        "vadduws",
+       VAND:           "vand",
+       VANDC:          "vandc",
+       VAVGSB:         "vavgsb",
+       VAVGSH:         "vavgsh",
+       VAVGSW:         "vavgsw",
+       VAVGUB:         "vavgub",
+       VAVGUH:         "vavguh",
+       VAVGUW:         "vavguw",
+       VCFSX:          "vcfsx",
+       VCFUX:          "vcfux",
+       VCMPBFP:        "vcmpbfp",
+       VCMPBFPCC:      "vcmpbfp.",
+       VCMPEQFP:       "vcmpeqfp",
+       VCMPEQFPCC:     "vcmpeqfp.",
+       VCMPEQUB:       "vcmpequb",
+       VCMPEQUBCC:     "vcmpequb.",
+       VCMPEQUH:       "vcmpequh",
+       VCMPEQUHCC:     "vcmpequh.",
+       VCMPEQUW:       "vcmpequw",
+       VCMPEQUWCC:     "vcmpequw.",
+       VCMPGEFP:       "vcmpgefp",
+       VCMPGEFPCC:     "vcmpgefp.",
+       VCMPGTFP:       "vcmpgtfp",
+       VCMPGTFPCC:     "vcmpgtfp.",
+       VCMPGTSB:       "vcmpgtsb",
+       VCMPGTSBCC:     "vcmpgtsb.",
+       VCMPGTSH:       "vcmpgtsh",
+       VCMPGTSHCC:     "vcmpgtsh.",
+       VCMPGTSW:       "vcmpgtsw",
+       VCMPGTSWCC:     "vcmpgtsw.",
+       VCMPGTUB:       "vcmpgtub",
+       VCMPGTUBCC:     "vcmpgtub.",
+       VCMPGTUH:       "vcmpgtuh",
+       VCMPGTUHCC:     "vcmpgtuh.",
+       VCMPGTUW:       "vcmpgtuw",
+       VCMPGTUWCC:     "vcmpgtuw.",
+       VCTSXS:         "vctsxs",
+       VCTUXS:         "vctuxs",
+       VEXPTEFP:       "vexptefp",
+       VLOGEFP:        "vlogefp",
+       VMADDFP:        "vmaddfp",
+       VMAXFP:         "vmaxfp",
+       VMAXSB:         "vmaxsb",
+       VMAXSH:         "vmaxsh",
+       VMAXSW:         "vmaxsw",
+       VMAXUB:         "vmaxub",
+       VMAXUH:         "vmaxuh",
+       VMAXUW:         "vmaxuw",
+       VMHADDSHS:      "vmhaddshs",
+       VMHRADDSHS:     "vmhraddshs",
+       VMINFP:         "vminfp",
+       VMINSB:         "vminsb",
+       VMINSH:         "vminsh",
+       VMINSW:         "vminsw",
+       VMINUB:         "vminub",
+       VMINUH:         "vminuh",
+       VMINUW:         "vminuw",
+       VMLADDUHM:      "vmladduhm",
+       VMRGHB:         "vmrghb",
+       VMRGHH:         "vmrghh",
+       VMRGHW:         "vmrghw",
+       VMRGLB:         "vmrglb",
+       VMRGLH:         "vmrglh",
+       VMRGLW:         "vmrglw",
+       VMSUMMBM:       "vmsummbm",
+       VMSUMSHM:       "vmsumshm",
+       VMSUMSHS:       "vmsumshs",
+       VMSUMUBM:       "vmsumubm",
+       VMSUMUHM:       "vmsumuhm",
+       VMSUMUHS:       "vmsumuhs",
+       VMULESB:        "vmulesb",
+       VMULESH:        "vmulesh",
+       VMULEUB:        "vmuleub",
+       VMULEUH:        "vmuleuh",
+       VMULOSB:        "vmulosb",
+       VMULOSH:        "vmulosh",
+       VMULOUB:        "vmuloub",
+       VMULOUH:        "vmulouh",
+       VNMSUBFP:       "vnmsubfp",
+       VNOR:           "vnor",
+       VOR:            "vor",
+       VPERM:          "vperm",
+       VPKPX:          "vpkpx",
+       VPKSHSS:        "vpkshss",
+       VPKSHUS:        "vpkshus",
+       VPKSWSS:        "vpkswss",
+       VPKSWUS:        "vpkswus",
+       VPKUHUM:        "vpkuhum",
+       VPKUHUS:        "vpkuhus",
+       VPKUWUM:        "vpkuwum",
+       VPKUWUS:        "vpkuwus",
+       VREFP:          "vrefp",
+       VRFIM:          "vrfim",
+       VRFIN:          "vrfin",
+       VRFIP:          "vrfip",
+       VRFIZ:          "vrfiz",
+       VRLB:           "vrlb",
+       VRLH:           "vrlh",
+       VRLW:           "vrlw",
+       VRSQRTEFP:      "vrsqrtefp",
+       VSEL:           "vsel",
+       VSL:            "vsl",
+       VSLB:           "vslb",
+       VSLDOI:         "vsldoi",
+       VSLH:           "vslh",
+       VSLO:           "vslo",
+       VSLW:           "vslw",
+       VSPLTB:         "vspltb",
+       VSPLTH:         "vsplth",
+       VSPLTISB:       "vspltisb",
+       VSPLTISH:       "vspltish",
+       VSPLTISW:       "vspltisw",
+       VSPLTW:         "vspltw",
+       VSR:            "vsr",
+       VSRAB:          "vsrab",
+       VSRAH:          "vsrah",
+       VSRAW:          "vsraw",
+       VSRB:           "vsrb",
+       VSRH:           "vsrh",
+       VSRO:           "vsro",
+       VSRW:           "vsrw",
+       VSUBCUW:        "vsubcuw",
+       VSUBFP:         "vsubfp",
+       VSUBSBS:        "vsubsbs",
+       VSUBSHS:        "vsubshs",
+       VSUBSWS:        "vsubsws",
+       VSUBUBM:        "vsububm",
+       VSUBUBS:        "vsububs",
+       VSUBUHM:        "vsubuhm",
+       VSUBUHS:        "vsubuhs",
+       VSUBUWM:        "vsubuwm",
+       VSUBUWS:        "vsubuws",
+       VSUM2SWS:       "vsum2sws",
+       VSUM4SBS:       "vsum4sbs",
+       VSUM4SHS:       "vsum4shs",
+       VSUM4UBS:       "vsum4ubs",
+       VSUMSWS:        "vsumsws",
+       VUPKHPX:        "vupkhpx",
+       VUPKHSB:        "vupkhsb",
+       VUPKHSH:        "vupkhsh",
+       VUPKLPX:        "vupklpx",
+       VUPKLSB:        "vupklsb",
+       VUPKLSH:        "vupklsh",
+       VXOR:           "vxor",
+       FRE:            "fre",
+       FRECC:          "fre.",
+       FRIM:           "frim",
+       FRIMCC:         "frim.",
+       FRIN:           "frin",
+       FRINCC:         "frin.",
+       FRIP:           "frip",
+       FRIPCC:         "frip.",
+       FRIZ:           "friz",
+       FRIZCC:         "friz.",
+       FRSQRTES:       "frsqrtes",
+       FRSQRTESCC:     "frsqrtes.",
+       HRFID:          "hrfid",
+       POPCNTB:        "popcntb",
+       MFOCRF:         "mfocrf",
+       MTOCRF:         "mtocrf",
+       SLBMFEE:        "slbmfee",
+       SLBMFEV:        "slbmfev",
+       SLBMTE:         "slbmte",
+       RFSCV:          "rfscv",
+       SCV:            "scv",
+       LQ:             "lq",
+       STQ:            "stq",
+       CNTLZD:         "cntlzd",
+       CNTLZDCC:       "cntlzd.",
+       DCBF:           "dcbf",
+       DCBST:          "dcbst",
+       DCBT:           "dcbt",
+       DCBTST:         "dcbtst",
+       DIVD:           "divd",
+       DIVDCC:         "divd.",
+       DIVDO:          "divdo",
+       DIVDOCC:        "divdo.",
+       DIVDU:          "divdu",
+       DIVDUCC:        "divdu.",
+       DIVDUO:         "divduo",
+       DIVDUOCC:       "divduo.",
+       DIVW:           "divw",
+       DIVWCC:         "divw.",
+       DIVWO:          "divwo",
+       DIVWOCC:        "divwo.",
+       DIVWU:          "divwu",
+       DIVWUCC:        "divwu.",
+       DIVWUO:         "divwuo",
+       DIVWUOCC:       "divwuo.",
+       EIEIO:          "eieio",
+       EXTSB:          "extsb",
+       EXTSBCC:        "extsb.",
+       EXTSW:          "extsw",
+       EXTSWCC:        "extsw.",
+       FADDS:          "fadds",
+       FADDSCC:        "fadds.",
+       FCFID:          "fcfid",
+       FCFIDCC:        "fcfid.",
+       FCTID:          "fctid",
+       FCTIDCC:        "fctid.",
+       FCTIDZ:         "fctidz",
+       FCTIDZCC:       "fctidz.",
+       FDIVS:          "fdivs",
+       FDIVSCC:        "fdivs.",
+       FMADDS:         "fmadds",
+       FMADDSCC:       "fmadds.",
+       FMSUBS:         "fmsubs",
+       FMSUBSCC:       "fmsubs.",
+       FMULS:          "fmuls",
+       FMULSCC:        "fmuls.",
+       FNMADDS:        "fnmadds",
+       FNMADDSCC:      "fnmadds.",
+       FNMSUBS:        "fnmsubs",
+       FNMSUBSCC:      "fnmsubs.",
+       FRES:           "fres",
+       FRESCC:         "fres.",
+       FRSQRTE:        "frsqrte",
+       FRSQRTECC:      "frsqrte.",
+       FSEL:           "fsel",
+       FSELCC:         "fsel.",
+       FSQRTS:         "fsqrts",
+       FSQRTSCC:       "fsqrts.",
+       FSUBS:          "fsubs",
+       FSUBSCC:        "fsubs.",
+       ICBI:           "icbi",
+       LD:             "ld",
+       LDARX:          "ldarx",
+       LDU:            "ldu",
+       LDUX:           "ldux",
+       LDX:            "ldx",
+       LWA:            "lwa",
+       LWARX:          "lwarx",
+       LWAUX:          "lwaux",
+       LWAX:           "lwax",
+       MFTB:           "mftb",
+       MTMSRD:         "mtmsrd",
+       MULHD:          "mulhd",
+       MULHDCC:        "mulhd.",
+       MULHDU:         "mulhdu",
+       MULHDUCC:       "mulhdu.",
+       MULHW:          "mulhw",
+       MULHWCC:        "mulhw.",
+       MULHWU:         "mulhwu",
+       MULHWUCC:       "mulhwu.",
+       MULLD:          "mulld",
+       MULLDCC:        "mulld.",
+       MULLDO:         "mulldo",
+       MULLDOCC:       "mulldo.",
+       RFID:           "rfid",
+       RLDCL:          "rldcl",
+       RLDCLCC:        "rldcl.",
+       RLDCR:          "rldcr",
+       RLDCRCC:        "rldcr.",
+       RLDIC:          "rldic",
+       RLDICCC:        "rldic.",
+       RLDICL:         "rldicl",
+       RLDICLCC:       "rldicl.",
+       RLDICR:         "rldicr",
+       RLDICRCC:       "rldicr.",
+       RLDIMI:         "rldimi",
+       RLDIMICC:       "rldimi.",
+       SC:             "sc",
+       SLBIA:          "slbia",
+       SLBIE:          "slbie",
+       SLD:            "sld",
+       SLDCC:          "sld.",
+       SRAD:           "srad",
+       SRADCC:         "srad.",
+       SRADI:          "sradi",
+       SRADICC:        "sradi.",
+       SRD:            "srd",
+       SRDCC:          "srd.",
+       STD:            "std",
+       STDCXCC:        "stdcx.",
+       STDU:           "stdu",
+       STDUX:          "stdux",
+       STDX:           "stdx",
+       STFIWX:         "stfiwx",
+       STWCXCC:        "stwcx.",
+       SUBF:           "subf",
+       SUBFCC:         "subf.",
+       SUBFO:          "subfo",
+       SUBFOCC:        "subfo.",
+       TD:             "td",
+       TDI:            "tdi",
+       TLBSYNC:        "tlbsync",
+       FCTIW:          "fctiw",
+       FCTIWCC:        "fctiw.",
+       FCTIWZ:         "fctiwz",
+       FCTIWZCC:       "fctiwz.",
+       FSQRT:          "fsqrt",
+       FSQRTCC:        "fsqrt.",
+       ADD:            "add",
+       ADDCC:          "add.",
+       ADDO:           "addo",
+       ADDOCC:         "addo.",
+       ADDC:           "addc",
+       ADDCCC:         "addc.",
+       ADDCO:          "addco",
+       ADDCOCC:        "addco.",
+       ADDE:           "adde",
+       ADDECC:         "adde.",
+       ADDEO:          "addeo",
+       ADDEOCC:        "addeo.",
+       LI:             "li",
+       ADDI:           "addi",
+       ADDIC:          "addic",
+       ADDICCC:        "addic.",
+       LIS:            "lis",
+       ADDIS:          "addis",
+       ADDME:          "addme",
+       ADDMECC:        "addme.",
+       ADDMEO:         "addmeo",
+       ADDMEOCC:       "addmeo.",
+       ADDZE:          "addze",
+       ADDZECC:        "addze.",
+       ADDZEO:         "addzeo",
+       ADDZEOCC:       "addzeo.",
+       AND:            "and",
+       ANDCC:          "and.",
+       ANDC:           "andc",
+       ANDCCC:         "andc.",
+       ANDICC:         "andi.",
+       ANDISCC:        "andis.",
+       B:              "b",
+       BA:             "ba",
+       BL:             "bl",
+       BLA:            "bla",
+       BC:             "bc",
+       BCA:            "bca",
+       BCL:            "bcl",
+       BCLA:           "bcla",
+       BCCTR:          "bcctr",
+       BCCTRL:         "bcctrl",
+       BCLR:           "bclr",
+       BCLRL:          "bclrl",
+       CMPW:           "cmpw",
+       CMPD:           "cmpd",
+       CMP:            "cmp",
+       CMPWI:          "cmpwi",
+       CMPDI:          "cmpdi",
+       CMPI:           "cmpi",
+       CMPLW:          "cmplw",
+       CMPLD:          "cmpld",
+       CMPL:           "cmpl",
+       CMPLWI:         "cmplwi",
+       CMPLDI:         "cmpldi",
+       CMPLI:          "cmpli",
+       CNTLZW:         "cntlzw",
+       CNTLZWCC:       "cntlzw.",
+       CRAND:          "crand",
+       CRANDC:         "crandc",
+       CREQV:          "creqv",
+       CRNAND:         "crnand",
+       CRNOR:          "crnor",
+       CROR:           "cror",
+       CRORC:          "crorc",
+       CRXOR:          "crxor",
+       DCBZ:           "dcbz",
+       EQV:            "eqv",
+       EQVCC:          "eqv.",
+       EXTSH:          "extsh",
+       EXTSHCC:        "extsh.",
+       FABS:           "fabs",
+       FABSCC:         "fabs.",
+       FADD:           "fadd",
+       FADDCC:         "fadd.",
+       FCMPO:          "fcmpo",
+       FCMPU:          "fcmpu",
+       FDIV:           "fdiv",
+       FDIVCC:         "fdiv.",
+       FMADD:          "fmadd",
+       FMADDCC:        "fmadd.",
+       FMR:            "fmr",
+       FMRCC:          "fmr.",
+       FMSUB:          "fmsub",
+       FMSUBCC:        "fmsub.",
+       FMUL:           "fmul",
+       FMULCC:         "fmul.",
+       FNABS:          "fnabs",
+       FNABSCC:        "fnabs.",
+       FNEG:           "fneg",
+       FNEGCC:         "fneg.",
+       FNMADD:         "fnmadd",
+       FNMADDCC:       "fnmadd.",
+       FNMSUB:         "fnmsub",
+       FNMSUBCC:       "fnmsub.",
+       FRSP:           "frsp",
+       FRSPCC:         "frsp.",
+       FSUB:           "fsub",
+       FSUBCC:         "fsub.",
+       ISYNC:          "isync",
+       LBZ:            "lbz",
+       LBZU:           "lbzu",
+       LBZUX:          "lbzux",
+       LBZX:           "lbzx",
+       LFD:            "lfd",
+       LFDU:           "lfdu",
+       LFDUX:          "lfdux",
+       LFDX:           "lfdx",
+       LFS:            "lfs",
+       LFSU:           "lfsu",
+       LFSUX:          "lfsux",
+       LFSX:           "lfsx",
+       LHA:            "lha",
+       LHAU:           "lhau",
+       LHAUX:          "lhaux",
+       LHAX:           "lhax",
+       LHBRX:          "lhbrx",
+       LHZ:            "lhz",
+       LHZU:           "lhzu",
+       LHZUX:          "lhzux",
+       LHZX:           "lhzx",
+       LMW:            "lmw",
+       LSWI:           "lswi",
+       LSWX:           "lswx",
+       LWBRX:          "lwbrx",
+       LWZ:            "lwz",
+       LWZU:           "lwzu",
+       LWZUX:          "lwzux",
+       LWZX:           "lwzx",
+       MCRF:           "mcrf",
+       MCRFS:          "mcrfs",
+       MFCR:           "mfcr",
+       MFFS:           "mffs",
+       MFFSCC:         "mffs.",
+       MFMSR:          "mfmsr",
+       MFSPR:          "mfspr",
+       MTCRF:          "mtcrf",
+       MTFSB0:         "mtfsb0",
+       MTFSB0CC:       "mtfsb0.",
+       MTFSB1:         "mtfsb1",
+       MTFSB1CC:       "mtfsb1.",
+       MTFSF:          "mtfsf",
+       MTFSFCC:        "mtfsf.",
+       MTFSFI:         "mtfsfi",
+       MTFSFICC:       "mtfsfi.",
+       MTMSR:          "mtmsr",
+       MTSPR:          "mtspr",
+       MULLI:          "mulli",
+       MULLW:          "mullw",
+       MULLWCC:        "mullw.",
+       MULLWO:         "mullwo",
+       MULLWOCC:       "mullwo.",
+       NAND:           "nand",
+       NANDCC:         "nand.",
+       NEG:            "neg",
+       NEGCC:          "neg.",
+       NEGO:           "nego",
+       NEGOCC:         "nego.",
+       NOR:            "nor",
+       NORCC:          "nor.",
+       OR:             "or",
+       ORCC:           "or.",
+       ORC:            "orc",
+       ORCCC:          "orc.",
+       NOP:            "nop",
+       ORI:            "ori",
+       ORIS:           "oris",
+       RLWIMI:         "rlwimi",
+       RLWIMICC:       "rlwimi.",
+       RLWINM:         "rlwinm",
+       RLWINMCC:       "rlwinm.",
+       RLWNM:          "rlwnm",
+       RLWNMCC:        "rlwnm.",
+       SLW:            "slw",
+       SLWCC:          "slw.",
+       SRAW:           "sraw",
+       SRAWCC:         "sraw.",
+       SRAWI:          "srawi",
+       SRAWICC:        "srawi.",
+       SRW:            "srw",
+       SRWCC:          "srw.",
+       STB:            "stb",
+       STBU:           "stbu",
+       STBUX:          "stbux",
+       STBX:           "stbx",
+       STFD:           "stfd",
+       STFDU:          "stfdu",
+       STFDUX:         "stfdux",
+       STFDX:          "stfdx",
+       STFS:           "stfs",
+       STFSU:          "stfsu",
+       STFSUX:         "stfsux",
+       STFSX:          "stfsx",
+       STH:            "sth",
+       STHBRX:         "sthbrx",
+       STHU:           "sthu",
+       STHUX:          "sthux",
+       STHX:           "sthx",
+       STMW:           "stmw",
+       STSWI:          "stswi",
+       STSWX:          "stswx",
+       STW:            "stw",
+       STWBRX:         "stwbrx",
+       STWU:           "stwu",
+       STWUX:          "stwux",
+       STWX:           "stwx",
+       SUBFC:          "subfc",
+       SUBFCCC:        "subfc.",
+       SUBFCO:         "subfco",
+       SUBFCOCC:       "subfco.",
+       SUBFE:          "subfe",
+       SUBFECC:        "subfe.",
+       SUBFEO:         "subfeo",
+       SUBFEOCC:       "subfeo.",
+       SUBFIC:         "subfic",
+       SUBFME:         "subfme",
+       SUBFMECC:       "subfme.",
+       SUBFMEO:        "subfmeo",
+       SUBFMEOCC:      "subfmeo.",
+       SUBFZE:         "subfze",
+       SUBFZECC:       "subfze.",
+       SUBFZEO:        "subfzeo",
+       SUBFZEOCC:      "subfzeo.",
+       SYNC:           "sync",
+       TLBIE:          "tlbie",
+       TW:             "tw",
+       TWI:            "twi",
+       XOR:            "xor",
+       XORCC:          "xor.",
+       XORI:           "xori",
+       XORIS:          "xoris",
 }
 
 var (
-       ap_Reg_11_15               = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}}
-       ap_Reg_6_10                = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}}
-       ap_PCRel_6_29_shift2       = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}}
-       ap_Label_6_29_shift2       = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}}
-       ap_ImmUnsigned_6_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}}
-       ap_CondRegBit_11_15        = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}}
-       ap_PCRel_16_29_shift2      = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}}
-       ap_Label_16_29_shift2      = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}}
-       ap_ImmUnsigned_19_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}}
-       ap_CondRegBit_6_10         = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}}
-       ap_CondRegBit_16_20        = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}}
-       ap_CondRegField_6_8        = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}}
-       ap_CondRegField_11_13      = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}}
-       ap_ImmUnsigned_20_26       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}}
-       ap_SpReg_11_20             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}}
-       ap_Offset_16_31            = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}}
-       ap_Reg_16_20               = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}}
-       ap_Offset_16_29_shift2     = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}}
-       ap_Offset_16_27_shift4     = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}}
-       ap_ImmUnsigned_16_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}}
-       ap_ImmSigned_16_31         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}}
-       ap_ImmUnsigned_16_31       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}}
-       ap_CondRegBit_21_25        = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}}
-       ap_ImmUnsigned_21_25       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}}
-       ap_ImmUnsigned_26_30       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}}
-       ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
-       ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}}
-       ap_SpReg_16_20_11_15       = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}}
-       ap_ImmUnsigned_12_19       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}}
-       ap_ImmUnsigned_10_10       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}}
-       ap_VecSReg_31_31_6_10      = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}}
-       ap_FPReg_6_10              = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}}
-       ap_FPReg_16_20             = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}}
-       ap_FPReg_11_15             = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}}
-       ap_FPReg_21_25             = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}}
-       ap_ImmUnsigned_6_8         = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 3}}}
-       ap_ImmUnsigned_16_19       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}}
-       ap_ImmUnsigned_15_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}}
-       ap_ImmUnsigned_7_14        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}}
-       ap_ImmUnsigned_6_6         = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}}
-       ap_VecReg_6_10             = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}}
-       ap_VecReg_11_15            = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}}
-       ap_VecReg_16_20            = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}}
-       ap_ImmUnsigned_12_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}}
-       ap_ImmUnsigned_13_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}}
-       ap_ImmUnsigned_14_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}}
-       ap_ImmSigned_11_15         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}}
-       ap_VecReg_21_25            = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}}
-       ap_ImmUnsigned_22_25       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}}
-       ap_ImmUnsigned_11_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}}
-       ap_ImmUnsigned_16_16       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}}
-       ap_ImmUnsigned_17_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}}
-       ap_ImmUnsigned_22_22       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}}
-       ap_ImmUnsigned_16_21       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}}
-       ap_ImmUnsigned_21_22       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
-       ap_ImmUnsigned_11_12       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
-       ap_ImmUnsigned_11_11       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
-       ap_VecSReg_28_28_6_10      = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {6, 5}}}
-       ap_VecSReg_30_30_16_20     = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
-       ap_VecSReg_29_29_11_15     = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
-       ap_ImmUnsigned_22_23       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
-       ap_VecSReg_28_28_21_25     = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}}
-       ap_CondRegField_29_31      = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}}
-       ap_ImmUnsigned_7_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}}
-       ap_ImmUnsigned_9_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}}
-       ap_ImmUnsigned_31_31       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}}
-       ap_ImmSigned_16_20         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}}
-       ap_ImmUnsigned_20_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}}
-       ap_ImmUnsigned_8_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}}
-       ap_SpReg_12_15             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}}
-       ap_ImmUnsigned_6_20        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}}
-       ap_ImmUnsigned_11_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}}
-       ap_Reg_21_25               = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5}}}
+       ap_Reg_11_15                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
+       ap_Reg_6_10                      = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
+       ap_Reg_16_20                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
+       ap_FPReg_6_10                    = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
+       ap_VecReg_16_20                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
+       ap_VecReg_6_10                   = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
+       ap_FPReg_16_20                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
+       ap_VecSReg_31_31_6_10            = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1, 0}, {6, 5, 0}}}
+       ap_ImmUnsigned_16_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
+       ap_VecSpReg_10_10_6_9            = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1, 0}, {6, 4, 0}}}
+       ap_Offset_16_27_shift4           = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12, 0}}}
+       ap_ImmUnsigned_16_25_11_15_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 10, 0}, {11, 5, 0}, {31, 1, 0}}}
+       ap_Reg_38_42                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}}
+       ap_Reg_43_47                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5, 1}}}
+       ap_ImmSigned_14_31_48_63         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{14, 18, 0}, {16, 16, 1}}}
+       ap_ImmUnsigned_11_11             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1, 0}}}
+       ap_Offset_14_31_48_63            = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{14, 18, 0}, {16, 16, 1}}}
+       ap_FPReg_38_42                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}}
+       ap_VecReg_38_42                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}}
+       ap_VecSReg_37_37_38_42           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{5, 1, 1}, {6, 5, 1}}}
+       ap_VecSpReg_42_42_38_41          = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1, 1}, {6, 4, 1}}}
+       ap_MMAReg_38_40                  = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3, 1}}}
+       ap_VecSReg_61_61_43_47           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1, 1}, {11, 5, 1}}}
+       ap_VecSReg_62_62_48_52           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1, 1}, {16, 5, 1}}}
+       ap_ImmUnsigned_24_27             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{24, 4, 0}}}
+       ap_ImmUnsigned_28_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{28, 4, 0}}}
+       ap_ImmUnsigned_16_17             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 2, 0}}}
+       ap_ImmUnsigned_28_29             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{28, 2, 0}}}
+       ap_ImmUnsigned_16_23             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 8, 0}}}
+       ap_ImmUnsigned_16_19             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4, 0}}}
+       ap_CondRegBit_11_15              = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
+       ap_VecReg_11_15                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
+       ap_CondRegField_6_8              = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3, 0}}}
+       ap_ImmUnsigned_15_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1, 0}}}
+       ap_Reg_21_25                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
+       ap_ImmUnsigned_13_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3, 0}}}
+       ap_ImmUnsigned_12_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4, 0}}}
+       ap_VecReg_21_25                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
+       ap_ImmUnsigned_23_25             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{23, 3, 0}}}
+       ap_MMAReg_6_8                    = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3, 0}}}
+       ap_VecSReg_29_29_11_15           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1, 0}, {11, 5, 0}}}
+       ap_VecSReg_30_30_16_20           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1, 0}, {16, 5, 0}}}
+       ap_VecSReg_63_63_38_42           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1, 1}, {6, 5, 1}}}
+       ap_VecSReg_60_60_53_57           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 1}, {21, 5, 1}}}
+       ap_ImmUnsigned_24_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{24, 8, 0}}}
+       ap_ImmUnsigned_11_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
+       ap_ImmUnsigned_29_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{29, 3, 0}}}
+       ap_VecSReg_47_47_38_42           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{15, 1, 1}, {6, 5, 1}}}
+       ap_ImmUnsigned_46_46             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1, 1}}}
+       ap_ImmUnsigned_16_31_48_63       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16, 0}, {16, 16, 1}}}
+       ap_ImmUnsigned_21_22             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2, 0}}}
+       ap_ImmUnsigned_18_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{18, 3, 0}}}
+       ap_ImmUnsigned_19_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2, 0}}}
+       ap_ImmSigned_16_25_11_15_31_31   = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 10, 0}, {11, 5, 0}, {31, 1, 0}}}
+       ap_ImmUnsigned_22_22             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1, 0}}}
+       ap_ImmUnsigned_10_10             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1, 0}}}
+       ap_ImmUnsigned_14_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2, 0}}}
+       ap_ImmUnsigned_10_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 6, 0}}}
+       ap_ImmUnsigned_30_30_16_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1, 0}, {16, 5, 0}}}
+       ap_Offset_16_29_shift2           = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14, 0}}}
+       ap_VecSReg_28_28_6_10            = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 0}, {6, 5, 0}}}
+       ap_CondRegField_11_13            = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3, 0}}}
+       ap_ImmUnsigned_9_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2, 0}}}
+       ap_ImmUnsigned_9_15              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 7, 0}}}
+       ap_ImmUnsigned_25_25_29_29_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{25, 1, 0}, {29, 1, 0}, {11, 5, 0}}}
+       ap_ImmUnsigned_13_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 8, 0}}}
+       ap_ImmUnsigned_6_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
+       ap_FPReg_11_15                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
+       ap_ImmUnsigned_7_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4, 0}}}
+       ap_ImmUnsigned_31_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1, 0}}}
+       ap_SpReg_11_20                   = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10, 0}}}
+       ap_ImmUnsigned_20_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1, 0}}}
+       ap_ImmUnsigned_16_16             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1, 0}}}
+       ap_ImmUnsigned_17_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4, 0}}}
+       ap_ImmUnsigned_22_23             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2, 0}}}
+       ap_VecSReg_28_28_21_25           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 0}, {21, 5, 0}}}
+       ap_ImmUnsigned_11_12             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2, 0}}}
+       ap_ImmSigned_11_15               = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
+       ap_ImmUnsigned_16_21             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6, 0}}}
+       ap_CondRegBit_21_25              = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
+       ap_ImmUnsigned_12_13             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 2, 0}}}
+       ap_ImmUnsigned_14_14             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1, 0}}}
+       ap_ImmUnsigned_22_25             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4, 0}}}
+       ap_ImmUnsigned_12_19             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8, 0}}}
+       ap_ImmUnsigned_20_26             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7, 0}}}
+       ap_ImmUnsigned_8_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3, 0}}}
+       ap_FPReg_21_25                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
+       ap_SpReg_16_20_11_15             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5, 0}, {11, 5, 0}}}
+       ap_ImmUnsigned_26_26_21_25       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1, 0}, {21, 5, 0}}}
+       ap_ImmSigned_16_31               = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16, 0}}}
+       ap_ImmUnsigned_16_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16, 0}}}
+       ap_PCRel_6_29_shift2             = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24, 0}}}
+       ap_Label_6_29_shift2             = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24, 0}}}
+       ap_PCRel_16_29_shift2            = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14, 0}}}
+       ap_Label_16_29_shift2            = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14, 0}}}
+       ap_CondRegBit_6_10               = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
+       ap_CondRegBit_16_20              = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
+       ap_Offset_16_31                  = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16, 0}}}
+       ap_ImmUnsigned_7_14              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8, 0}}}
+       ap_ImmUnsigned_6_6               = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1, 0}}}
+       ap_ImmUnsigned_6_8               = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 3, 0}}}
+       ap_ImmUnsigned_21_25             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
+       ap_ImmUnsigned_26_30             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5, 0}}}
 )
 
 var instFormats = [...]instFormat{
-       {CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CNTLZWCC, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr)
-               [5]*argField{ap_PCRel_6_29_shift2}},
-       {BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr)
-               [5]*argField{ap_Label_6_29_shift2}},
-       {BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr)
-               [5]*argField{ap_PCRel_6_29_shift2}},
-       {BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr)
-               [5]*argField{ap_Label_6_29_shift2}},
-       {BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
-       {BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
-       {BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
-       {BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
-       {BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
-       {BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
-       {BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
-       {BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
-       {BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
-       {BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
-       {CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA)
-               [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
-       {CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB)
-               [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
-       {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
-               [5]*argField{ap_ImmUnsigned_20_26}},
-       {CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb)
-               [5]*argField{}},
-       {MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From Branch History Rolling Buffer XFX-form (mfbhrbe RT,BHRBE)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
-       {LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
-       {STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
-       {LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
-       {STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI)
-               [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
-       {ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT, SI)
-               [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
-       {ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDCC, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDOCC, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFCC, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFOCC, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDICCC, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDCCC, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDCOCC, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFCCC, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFCOCC, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDECC, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDEOCC, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDMECC, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDMEOCC, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFECC, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFEOCC, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFMECC, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFMEOCC, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDZECC, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {ADDZEOCC, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFZECC, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {SUBFZEOCC, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {NEGCC, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {NEGOCC, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLWCC, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLWOCC, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHWCC, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHWUCC, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWCC, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWOCC, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWUCC, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWUOCC, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWECC, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEOCC, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEUCC, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVWEUOCC, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLDCC, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLDOCC, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHDUCC, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHDCC, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDCC, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDOCC, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDUCC, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDUOCC, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDECC, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEOCC, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEUCC, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MODSD, 0xfc0007fe, 0x7c000612, 0x1, // Modulo Signed Doubleword X-form (modsd RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MODUD, 0xfc0007fe, 0x7c000212, 0x1, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MODSW, 0xfc0007fe, 0x7c000616, 0x1, // Modulo Signed Word X-form (modsw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MODUW, 0xfc0007fe, 0x7c000216, 0x1, // Modulo Unsigned Word X-form (moduw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
-       {CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
-       {CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
-       {ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
-       {TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ANDICC, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {ANDISCC, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
-       {AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ANDCC, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {XORCC, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {NANDCC, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ORCC, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {NORCC, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ANDCCC, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSBCC, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {EQVCC, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {ORCCC, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSHCC, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {EXTSWCC, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CNTLZDCC, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWINMCC, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWNMCC, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLWIMICC, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
-       {RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDICLCC, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDICRCC, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDICCC, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDCLCC, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDCRCC, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {RLDIMICC, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
-       {SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SLWCC, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRWCC, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
-       {SRAWICC, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
-       {SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRAWCC, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SLDCC, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRDCC, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
-       {SRADICC, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
-       {SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {SRADCC, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
-               [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-       {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
-       {MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
-               [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
-       {MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT)
-               [5]*argField{ap_Reg_6_10}},
-       {MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801, // Move To Split Little Endian X-form (mtsle L)
-               [5]*argField{ap_ImmUnsigned_10_10}},
-       {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword XX1-form (mfvsrd RA,XS)
-               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-       {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero XX1-form (mfvsrwz RA,XS)
-               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-       {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword XX1-form (mtvsrd XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic XX1-form (mtvsrwa XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero XX1-form (mtvsrwz XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS)
-               [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
-       {MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM)
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
-       {MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801, // Move to Condition Register from XER X-form (mcrxr BF)
-               [5]*argField{ap_CondRegField_6_8}},
-       {MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801, // Move To Device Control Register User-mode Indexed X-form (mtdcrux RS,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801, // Move From Device Control Register User-mode Indexed X-form (mfdcrux RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word and Zero Indexed X-form (lfiwzx FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
-       {STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA))
-               [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
-       {STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FMRCC, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FABSCC, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FNABSCC, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FNEGCC, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FCPSGNCC, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FADDCC, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FADDSCC, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSUBCC, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSUBSCC, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
-       {FMULCC, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
-       {FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
-       {FMULSCC, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
-       {FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FDIVCC, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FDIVSCC, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FSQRTCC, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FSQRTSCC, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRECC, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRESCC, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSQRTECC, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSQRTESCC, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
-       {FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMADDCC, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMADDSCC, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMSUBCC, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FMSUBSCC, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMADDCC, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMADDSCC, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMSUBCC, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FNMSUBSCC, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRSPCC, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDCC, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDZCC, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDUCC, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIDUZCC, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWCC, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWZCC, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWUCC, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCTIWUZCC, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDCC, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDUCC, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDSCC, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCFIDUSCC, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRINCC, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIZCC, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIPCC, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FRIMCC, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {FSELCC, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
-       {MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT)
-               [5]*argField{ap_FPReg_6_10}},
-       {MFFSCC, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT)
-               [5]*argField{ap_FPReg_6_10}},
-       {MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
-               [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
-       {MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
-               [5]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
-       {MTFSFICC, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
-               [5]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
-       {MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
-               [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
-       {MTFSFCC, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
-               [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
-       {MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
-               [5]*argField{ap_ImmUnsigned_6_10}},
-       {MTFSB0CC, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
-               [5]*argField{ap_ImmUnsigned_6_10}},
-       {MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
-               [5]*argField{ap_ImmUnsigned_6_10}},
-       {MTFSB1CC, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
-               [5]*argField{ap_ImmUnsigned_6_10}},
-       {LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVX, 0xfc0007fe, 0x7c0000ce, 0x1, // Load Vector Indexed X-form (lvx VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVXL, 0xfc0007fe, 0x7c0002ce, 0x1, // Load Vector Indexed LRU X-form (lvxl VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVEBX, 0xfc0007fe, 0x7c00010e, 0x1, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVEHX, 0xfc0007fe, 0x7c00014e, 0x1, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVEWX, 0xfc0007fe, 0x7c00018e, 0x1, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVX, 0xfc0007fe, 0x7c0001ce, 0x1, // Store Vector Indexed X-form (stvx VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVXL, 0xfc0007fe, 0x7c0003ce, 0x1, // Store Vector Indexed LRU X-form (stvxl VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVSL, 0xfc0007fe, 0x7c00000c, 0x1, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVSR, 0xfc0007fe, 0x7c00004c, 0x1, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {VPKPX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VUPKLSW, 0xfc0007ff, 0x100006ce, 0x1f0000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VMRGHB, 0xfc0007ff, 0x1000000c, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGHH, 0xfc0007ff, 0x1000004c, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGLB, 0xfc0007ff, 0x1000010c, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGLH, 0xfc0007ff, 0x1000014c, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGHW, 0xfc0007ff, 0x1000008c, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGLW, 0xfc0007ff, 0x1000018c, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGEW, 0xfc0007ff, 0x1000078c, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMRGOW, 0xfc0007ff, 0x1000068c, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSPLTB, 0xfc0007ff, 0x1000020c, 0x100000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
-       {VSPLTH, 0xfc0007ff, 0x1000024c, 0x180000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
-       {VSPLTW, 0xfc0007ff, 0x1000028c, 0x1c0000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}},
-       {VSPLTISB, 0xfc0007ff, 0x1000030c, 0xf800, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM)
-               [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
-       {VSPLTISH, 0xfc0007ff, 0x1000034c, 0xf800, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM)
-               [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
-       {VSPLTISW, 0xfc0007ff, 0x1000038c, 0xf800, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM)
-               [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
-       {VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VPERMR, 0xfc00003f, 0x1000003b, 0x0, // Vector Permute Right-indexed VA-form (vpermr VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSLDOI, 0xfc00003f, 0x1000002c, 0x400, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}},
-       {VSLO, 0xfc0007ff, 0x1000040c, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSR, 0xfc0007ff, 0x100002c4, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRO, 0xfc0007ff, 0x1000044c, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDCUW, 0xfc0007ff, 0x10000180, 0x0, // Vector Add and Write Carry-Out Unsigned Word VX-form (vaddcuw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDSBS, 0xfc0007ff, 0x10000300, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDSHS, 0xfc0007ff, 0x10000340, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDSWS, 0xfc0007ff, 0x10000380, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUBM, 0xfc0007ff, 0x10000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUDM, 0xfc0007ff, 0x100000c0, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUHM, 0xfc0007ff, 0x10000040, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUWM, 0xfc0007ff, 0x10000080, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUBS, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUHS, 0xfc0007ff, 0x10000240, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUWS, 0xfc0007ff, 0x10000280, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDUQM, 0xfc0007ff, 0x10000100, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDEUQM, 0xfc00003f, 0x1000003c, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VADDCUQ, 0xfc0007ff, 0x10000140, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDECUQ, 0xfc00003f, 0x1000003d, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VSUBCUW, 0xfc0007ff, 0x10000580, 0x0, // Vector Subtract and Write Carry-Out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBSBS, 0xfc0007ff, 0x10000700, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBSHS, 0xfc0007ff, 0x10000740, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBSWS, 0xfc0007ff, 0x10000780, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUBM, 0xfc0007ff, 0x10000400, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUDM, 0xfc0007ff, 0x100004c0, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUHM, 0xfc0007ff, 0x10000440, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUWM, 0xfc0007ff, 0x10000480, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUBS, 0xfc0007ff, 0x10000600, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUHS, 0xfc0007ff, 0x10000640, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUWS, 0xfc0007ff, 0x10000680, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBUQM, 0xfc0007ff, 0x10000500, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBEUQM, 0xfc00003f, 0x1000003e, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VSUBCUQ, 0xfc0007ff, 0x10000540, 0x0, // Vector Subtract & write Carry Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBECUQ, 0xfc00003f, 0x1000003f, 0x0, // Vector Subtract Extended & write Carry Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMULESB, 0xfc0007ff, 0x10000308, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULEUB, 0xfc0007ff, 0x10000208, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULOSB, 0xfc0007ff, 0x10000108, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULOUB, 0xfc0007ff, 0x10000008, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULESH, 0xfc0007ff, 0x10000348, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULEUH, 0xfc0007ff, 0x10000248, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULOSH, 0xfc0007ff, 0x10000148, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULOUH, 0xfc0007ff, 0x10000048, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULESW, 0xfc0007ff, 0x10000388, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULEUW, 0xfc0007ff, 0x10000288, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULOSW, 0xfc0007ff, 0x10000188, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULOUW, 0xfc0007ff, 0x10000088, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMULUWM, 0xfc0007ff, 0x10000089, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMHADDSHS, 0xfc00003f, 0x10000020, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMHRADDSHS, 0xfc00003f, 0x10000021, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMLADDUHM, 0xfc00003f, 0x10000022, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMUBM, 0xfc00003f, 0x10000024, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMMBM, 0xfc00003f, 0x10000025, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMSHM, 0xfc00003f, 0x10000028, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMSHS, 0xfc00003f, 0x10000029, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMUHM, 0xfc00003f, 0x10000026, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VMSUMUDM, 0xfc00003f, 0x10000023, 0x0, // Vector Multiply-Sum Unsigned Doubleword Modulo VA-form (vmsumudm VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUM4SBS, 0xfc0007ff, 0x10000708, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUM4SHS, 0xfc0007ff, 0x10000648, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUM4UBS, 0xfc0007ff, 0x10000608, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAVGSB, 0xfc0007ff, 0x10000502, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAVGSH, 0xfc0007ff, 0x10000542, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAVGSW, 0xfc0007ff, 0x10000582, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAVGUB, 0xfc0007ff, 0x10000402, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAVGUW, 0xfc0007ff, 0x10000482, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAVGUH, 0xfc0007ff, 0x10000442, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXSB, 0xfc0007ff, 0x10000102, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXSD, 0xfc0007ff, 0x100001c2, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXUB, 0xfc0007ff, 0x10000002, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXUD, 0xfc0007ff, 0x100000c2, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXSH, 0xfc0007ff, 0x10000142, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXSW, 0xfc0007ff, 0x10000182, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXUH, 0xfc0007ff, 0x10000042, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMAXUW, 0xfc0007ff, 0x10000082, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINSB, 0xfc0007ff, 0x10000302, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINSD, 0xfc0007ff, 0x100003c2, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINUB, 0xfc0007ff, 0x10000202, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINUD, 0xfc0007ff, 0x100002c2, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINSH, 0xfc0007ff, 0x10000342, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINSW, 0xfc0007ff, 0x10000382, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINUH, 0xfc0007ff, 0x10000242, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINUW, 0xfc0007ff, 0x10000282, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUBCC, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUHCC, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUWCC, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQUDCC, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEB, 0xfc0007ff, 0x10000007, 0x0, // Vector Compare Not Equal Byte VX-form (vcmpneb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEBCC, 0xfc0007ff, 0x10000407, 0x0, // Vector Compare Not Equal Byte VX-form (vcmpneb. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEZB, 0xfc0007ff, 0x10000107, 0x0, // Vector Compare Not Equal or Zero Byte VX-form (vcmpnezb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEZBCC, 0xfc0007ff, 0x10000507, 0x0, // Vector Compare Not Equal or Zero Byte VX-form (vcmpnezb. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEH, 0xfc0007ff, 0x10000047, 0x0, // Vector Compare Not Equal Halfword VX-form (vcmpneh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEHCC, 0xfc0007ff, 0x10000447, 0x0, // Vector Compare Not Equal Halfword VX-form (vcmpneh. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEZH, 0xfc0007ff, 0x10000147, 0x0, // Vector Compare Not Equal or Zero Halfword VX-form (vcmpnezh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEZHCC, 0xfc0007ff, 0x10000547, 0x0, // Vector Compare Not Equal or Zero Halfword VX-form (vcmpnezh. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEW, 0xfc0007ff, 0x10000087, 0x0, // Vector Compare Not Equal Word VX-form (vcmpnew VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEWCC, 0xfc0007ff, 0x10000487, 0x0, // Vector Compare Not Equal Word VX-form (vcmpnew. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEZW, 0xfc0007ff, 0x10000187, 0x0, // Vector Compare Not Equal or Zero Word VX-form (vcmpnezw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPNEZWCC, 0xfc0007ff, 0x10000587, 0x0, // Vector Compare Not Equal or Zero Word VX-form (vcmpnezw. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSBCC, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSDCC, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSHCC, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTSWCC, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUBCC, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUDCC, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUHCC, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTUWCC, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VAND, 0xfc0007ff, 0x10000404, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VANDC, 0xfc0007ff, 0x10000444, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VEQV, 0xfc0007ff, 0x10000684, 0x0, // Vector Logical Equivalent VX-form (veqv VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VNAND, 0xfc0007ff, 0x10000584, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VORC, 0xfc0007ff, 0x10000544, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VNOR, 0xfc0007ff, 0x10000504, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VOR, 0xfc0007ff, 0x10000484, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VXOR, 0xfc0007ff, 0x100004c4, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VRLB, 0xfc0007ff, 0x10000004, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VRLH, 0xfc0007ff, 0x10000044, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VRLW, 0xfc0007ff, 0x10000084, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VRLD, 0xfc0007ff, 0x100000c4, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSLB, 0xfc0007ff, 0x10000104, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSLH, 0xfc0007ff, 0x10000144, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSLW, 0xfc0007ff, 0x10000184, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSLD, 0xfc0007ff, 0x100005c4, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRB, 0xfc0007ff, 0x10000204, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRH, 0xfc0007ff, 0x10000244, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRW, 0xfc0007ff, 0x10000284, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRD, 0xfc0007ff, 0x100006c4, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRAB, 0xfc0007ff, 0x10000304, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRAH, 0xfc0007ff, 0x10000344, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRAW, 0xfc0007ff, 0x10000384, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSRAD, 0xfc0007ff, 0x100003c4, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VADDFP, 0xfc0007ff, 0x1000000a, 0x0, // Vector Add Single-Precision VX-form (vaddfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSUBFP, 0xfc0007ff, 0x1000004a, 0x0, // Vector Subtract Single-Precision VX-form (vsubfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMADDFP, 0xfc00003f, 0x1000002e, 0x0, // Vector Multiply-Add Single-Precision VA-form (vmaddfp VRT,VRA,VRC,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
-       {VNMSUBFP, 0xfc00003f, 0x1000002f, 0x0, // Vector Negative Multiply-Subtract Single-Precision VA-form (vnmsubfp VRT,VRA,VRC,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
-       {VMAXFP, 0xfc0007ff, 0x1000040a, 0x0, // Vector Maximum Single-Precision VX-form (vmaxfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VMINFP, 0xfc0007ff, 0x1000044a, 0x0, // Vector Minimum Single-Precision VX-form (vminfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCTSXS, 0xfc0007ff, 0x100003ca, 0x0, // Vector Convert To Signed Fixed-Point Word Saturate VX-form (vctsxs VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
-       {VCTUXS, 0xfc0007ff, 0x1000038a, 0x0, // Vector Convert To Unsigned Fixed-Point Word Saturate VX-form (vctuxs VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
-       {VCFSX, 0xfc0007ff, 0x1000034a, 0x0, // Vector Convert From Signed Fixed-Point Word VX-form (vcfsx VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
-       {VCFUX, 0xfc0007ff, 0x1000030a, 0x0, // Vector Convert From Unsigned Fixed-Point Word VX-form (vcfux VRT,VRB,UIM)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
-       {VRFIM, 0xfc0007ff, 0x100002ca, 0x1f0000, // Vector Round to Single-Precision Integer toward -Infinity VX-form (vrfim VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VRFIN, 0xfc0007ff, 0x1000020a, 0x1f0000, // Vector Round to Single-Precision Integer Nearest VX-form (vrfin VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VRFIP, 0xfc0007ff, 0x1000028a, 0x1f0000, // Vector Round to Single-Precision Integer toward +Infinity VX-form (vrfip VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VRFIZ, 0xfc0007ff, 0x1000024a, 0x1f0000, // Vector Round to Single-Precision Integer toward Zero VX-form (vrfiz VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPBFPCC, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPEQFPCC, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGEFPCC, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCMPGTFPCC, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VLOGEFP, 0xfc0007ff, 0x100001ca, 0x1f0000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VREFP, 0xfc0007ff, 0x1000010a, 0x1f0000, // Vector Reciprocal Estimate Single-Precision VX-form (vrefp VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VRSQRTEFP, 0xfc0007ff, 0x1000014a, 0x1f0000, // Vector Reciprocal Square Root Estimate Single-Precision VX-form (vrsqrtefp VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VCIPHER, 0xfc0007ff, 0x10000508, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VCIPHERLAST, 0xfc0007ff, 0x10000509, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VNCIPHER, 0xfc0007ff, 0x10000548, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VNCIPHERLAST, 0xfc0007ff, 0x10000549, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VSBOX, 0xfc0007ff, 0x100005c8, 0xf800, // Vector AES SubBytes VX-form (vsbox VRT,VRA)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
-       {VSHASIGMAD, 0xfc0007ff, 0x100006c2, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
-       {VSHASIGMAW, 0xfc0007ff, 0x10000682, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
-       {VPMSUMB, 0xfc0007ff, 0x10000408, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPMSUMD, 0xfc0007ff, 0x100004c8, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPMSUMH, 0xfc0007ff, 0x10000448, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPMSUMW, 0xfc0007ff, 0x10000488, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VPERMXOR, 0xfc00003f, 0x1000002d, 0x0, // Vector Permute and Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
-       {VGBBD, 0xfc0007ff, 0x1000050c, 0x1f0000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VCLZB, 0xfc0007ff, 0x10000702, 0x1f0000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VCLZH, 0xfc0007ff, 0x10000742, 0x1f0000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VCLZW, 0xfc0007ff, 0x10000782, 0x1f0000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VCLZD, 0xfc0007ff, 0x100007c2, 0x1f0000, // Vector Count Leading Zeros Doubleword (vclzd VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VPOPCNTB, 0xfc0007ff, 0x10000703, 0x1f0000, // Vector Population Count Byte (vpopcntb VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VPOPCNTD, 0xfc0007ff, 0x100007c3, 0x1f0000, // Vector Population Count Doubleword (vpopcntd VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VPOPCNTH, 0xfc0007ff, 0x10000743, 0x1f0000, // Vector Population Count Halfword (vpopcnth VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VPOPCNTW, 0xfc0007ff, 0x10000783, 0x1f0000, // Vector Population Count Word (vpopcntw VRT,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
-       {VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {VBPERMD, 0xfc0007ff, 0x100005cc, 0x0, // Vector Bit Permute Doubleword VX-form (vbpermd VRT,VRA,VRB)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
-       {BCDADDCC, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
-       {BCDSUBCC, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
-               [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
-       {MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000, // Move To Vector Status and Control Register VX-form (mtvscr VRB)
-               [5]*argField{ap_VecReg_16_20}},
-       {MFVSCR, 0xfc0007ff, 0x10000604, 0x1ff800, // Move From Vector Status and Control Register VX-form (mfvscr VRT)
-               [5]*argField{ap_VecReg_6_10}},
-       {DADD, 0xfc0007ff, 0xec000004, 0x0, // DFP Add [Quad] X-form (dadd FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DADDCC, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DSUB, 0xfc0007ff, 0xec000404, 0x0, // DFP Subtract [Quad] X-form (dsub FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DSUBCC, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DMUL, 0xfc0007ff, 0xec000044, 0x0, // DFP Multiply [Quad] X-form (dmul FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DMULCC, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DDIV, 0xfc0007ff, 0xec000444, 0x0, // DFP Divide [Quad] X-form (ddiv FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DDIVCC, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DCMPU, 0xfc0007fe, 0xec000504, 0x600001, // DFP Compare Unordered [Quad] X-form (dcmpu BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DCMPO, 0xfc0007fe, 0xec000104, 0x600001, // DFP Compare Ordered [Quad] X-form (dcmpo BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DTSTDC, 0xfc0003fe, 0xec000184, 0x600001, // DFP Test Data Class [Quad] Z22-form (dtstdc BF,FRA,DCM)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DTSTDG, 0xfc0003fe, 0xec0001c4, 0x600001, // DFP Test Data Group [Quad] Z22-form (dtstdg BF,FRA,DGM)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DTSTEX, 0xfc0007fe, 0xec000144, 0x600001, // DFP Test Exponent [Quad] X-form (dtstex BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DTSTSF, 0xfc0007fe, 0xec000544, 0x600001, // DFP Test Significance [Quad] X-form (dtstsf BF,FRA,FRB)
-               [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DQUAI, 0xfc0001ff, 0xec000086, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai TE,FRT,FRB,RMC)
-               [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DQUAICC, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC)
-               [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DQUA, 0xfc0001ff, 0xec000006, 0x0, // DFP Quantize [Quad] Z23-form (dqua FRT,FRA,FRB,RMC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DQUACC, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRRND, 0xfc0001ff, 0xec000046, 0x0, // DFP Reround [Quad] Z23-form (drrnd FRT,FRA,FRB,RMC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRRNDCC, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx R,FRT,FRB,RMC)
-               [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRINTXCC, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC)
-               [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn R,FRT,FRB,RMC)
-               [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DRINTNCC, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC)
-               [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
-       {DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTDPCC, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTQPQCC, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DRSP, 0xfc0007ff, 0xec000604, 0x1f0000, // DFP Round To DFP Short X-form (drsp FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DRSPCC, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DRDPQCC, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000, // DFP Convert From Fixed X-form (dcffix FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCFFIXCC, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCFFIXQCC, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DCTFIXCC, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DDEDPD, 0xfc0007ff, 0xec000284, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd SP,FRT,FRB)
-               [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DDEDPDCC, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB)
-               [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DENBCD, 0xfc0007ff, 0xec000684, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd S,FRT,FRB)
-               [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DENBCDCC, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB)
-               [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DXEXCC, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
-       {DIEX, 0xfc0007ff, 0xec0006c4, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DIEXCC, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
-       {DSCLI, 0xfc0003ff, 0xec000084, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli FRT,FRA,SH)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DSCLICC, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DSCRI, 0xfc0003ff, 0xec0000c4, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri FRT,FRA,SH)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {DSCRICC, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH)
-               [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
-       {LXSDX, 0xfc0007fe, 0x7c000498, 0x0, // Load VSX Scalar Doubleword Indexed XX1-form (lxsdx XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXSIWAX, 0xfc0007fe, 0x7c000098, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed XX1-form (lxsiwax XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXSIWZX, 0xfc0007fe, 0x7c000018, 0x0, // Load VSX Scalar as Integer Word and Zero Indexed XX1-form (lxsiwzx XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXSSPX, 0xfc0007fe, 0x7c000418, 0x0, // Load VSX Scalar Single-Precision Indexed XX1-form (lxsspx XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVD2X, 0xfc0007fe, 0x7c000698, 0x0, // Load VSX Vector Doubleword*2 Indexed XX1-form (lxvd2x XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVDSX, 0xfc0007fe, 0x7c000298, 0x0, // Load VSX Vector Doubleword & Splat Indexed XX1-form (lxvdsx XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVH8X, 0xfc0007fe, 0x7c000658, 0x0, // Load VSX Vector Halfword*8 Indexed XX1-form (lxvh8x XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVB16X, 0xfc0007fe, 0x7c0006d8, 0x0, // Load VSX Vector Byte*16 Indexed XX1-form (lxvb16x XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXV, 0xfc000007, 0xf4000001, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
-               [5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
-       {LXVL, 0xfc0007fe, 0x7c00021a, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LXVX, 0xfc0007be, 0x7c000218, 0x40, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXSSPX, 0xfc0007fe, 0x7c000518, 0x0, // Store VSX Scalar Single-Precision Indexed XX1-form (stxsspx XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXVD2X, 0xfc0007fe, 0x7c000798, 0x0, // Store VSX Vector Doubleword*2 Indexed XX1-form (stxvd2x XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXVH8X, 0xfc0007fe, 0x7c000758, 0x0, // Store VSX Vector Halfword*4 Indexed XX1-form (stxvh8x XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXVB16X, 0xfc0007fe, 0x7c0007d8, 0x0, // Store VSX Vector Byte*16 Indexed XX1-form (stxvb16x XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXV, 0xfc000007, 0xf4000005, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
-               [5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
-       {STXVL, 0xfc0007fe, 0x7c00031a, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXVLL, 0xfc0007fe, 0x7c00035a, 0x0, // Store VSX Vector Left-justified with Length X-form (stxvll XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STXVX, 0xfc0007fe, 0x7c000318, 0x0, // Store VSX Vector Indexed X-form (stxvx XS,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSADDSP, 0xfc0007f8, 0xf0000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSCMPODP, 0xfc0007f8, 0xf0000158, 0x600001, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSCMPUDP, 0xfc0007f8, 0xf0000118, 0x600001, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSCPSGNDP, 0xfc0007f8, 0xf0000580, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSCVDPSP, 0xfc0007fc, 0xf0000424, 0x1f0000, // VSX Scalar round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xscvdpsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVDPSPN, 0xfc0007fc, 0xf000042c, 0x1f0000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVDPSXDS, 0xfc0007fc, 0xf0000560, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xscvdpsxds XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVDPSXWS, 0xfc0007fc, 0xf0000160, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xscvdpsxws XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVDPUXDS, 0xfc0007fc, 0xf0000520, 0x1f0000, // VSX Scalar truncate Double-Precision integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xscvdpuxds XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVDPUXWS, 0xfc0007fc, 0xf0000120, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xscvdpuxws XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVSPDP, 0xfc0007fc, 0xf0000524, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVSPDPN, 0xfc0007fc, 0xf000052c, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVSXDDP, 0xfc0007fc, 0xf00005e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvsxddp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVSXDSP, 0xfc0007fc, 0xf00004e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvsxdsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVUXDDP, 0xfc0007fc, 0xf00005a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvuxddp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSCVUXDSP, 0xfc0007fc, 0xf00004a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvuxdsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSDIVDP, 0xfc0007f8, 0xf00001c0, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSDIVSP, 0xfc0007f8, 0xf00000c0, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMADDADP, 0xfc0007f8, 0xf0000108, 0x0, // VSX Scalar Multiply-Add Double-Precision XX3-form (xsmaddadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMADDASP, 0xfc0007f8, 0xf0000008, 0x0, // VSX Scalar Multiply-Add Single-Precision XX3-form (xsmaddasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMAXDP, 0xfc0007f8, 0xf0000500, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMINDP, 0xfc0007f8, 0xf0000540, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMSUBADP, 0xfc0007f8, 0xf0000188, 0x0, // VSX Scalar Multiply-Subtract Double-Precision XX3-form (xsmsubadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMSUBASP, 0xfc0007f8, 0xf0000088, 0x0, // VSX Scalar Multiply-Subtract Single-Precision XX3-form (xsmsubasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMULDP, 0xfc0007f8, 0xf0000180, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSMULSP, 0xfc0007f8, 0xf0000080, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSNABSDP, 0xfc0007fc, 0xf00005a4, 0x1f0000, // VSX Scalar Negative Absolute Value Double-Precision XX2-form (xsnabsdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSNEGDP, 0xfc0007fc, 0xf00005e4, 0x1f0000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSNMADDADP, 0xfc0007f8, 0xf0000508, 0x0, // VSX Scalar Negative Multiply-Add Double-Precision XX3-form (xsnmaddadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSNMADDASP, 0xfc0007f8, 0xf0000408, 0x0, // VSX Scalar Negative Multiply-Add Single-Precision XX3-form (xsnmaddasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSNMSUBADP, 0xfc0007f8, 0xf0000588, 0x0, // VSX Scalar Negative Multiply-Subtract Double-Precision XX3-form (xsnmsubadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSNMSUBASP, 0xfc0007f8, 0xf0000488, 0x0, // VSX Scalar Negative Multiply-Subtract Single-Precision XX3-form (xsnmsubasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSRDPI, 0xfc0007fc, 0xf0000124, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRDPIC, 0xfc0007fc, 0xf00001ac, 0x1f0000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRDPIM, 0xfc0007fc, 0xf00001e4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRDPIP, 0xfc0007fc, 0xf00001a4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRDPIZ, 0xfc0007fc, 0xf0000164, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSREDP, 0xfc0007fc, 0xf0000168, 0x1f0000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRESP, 0xfc0007fc, 0xf0000068, 0x1f0000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRSP, 0xfc0007fc, 0xf0000464, 0x1f0000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRSQRTEDP, 0xfc0007fc, 0xf0000128, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSRSQRTESP, 0xfc0007fc, 0xf0000028, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSSQRTDP, 0xfc0007fc, 0xf000012c, 0x1f0000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSSQRTSP, 0xfc0007fc, 0xf000002c, 0x1f0000, // VSX Scalar Square Root Single-Precision XX-form (xssqrtsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XSSUBDP, 0xfc0007f8, 0xf0000140, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSSUBSP, 0xfc0007f8, 0xf0000040, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSTDIVDP, 0xfc0007f8, 0xf00001e8, 0x600001, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XSTSQRTDP, 0xfc0007fc, 0xf00001a8, 0x7f0001, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
-       {XVABSDP, 0xfc0007fc, 0xf0000764, 0x1f0000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVABSSP, 0xfc0007fc, 0xf0000664, 0x1f0000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVADDDP, 0xfc0007f8, 0xf0000300, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVADDSP, 0xfc0007f8, 0xf0000200, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPEQDPCC, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPEQSPCC, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGEDPCC, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGESPCC, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGTDPCC, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCMPGTSPCC, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCPSGNSP, 0xfc0007f8, 0xf0000680, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVCVDPSP, 0xfc0007fc, 0xf0000624, 0x1f0000, // VSX Vector round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xvcvdpsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVDPSXDS, 0xfc0007fc, 0xf0000760, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvdpsxds XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVDPSXWS, 0xfc0007fc, 0xf0000360, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvdpsxws XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVDPUXDS, 0xfc0007fc, 0xf0000720, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvdpuxds XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVDPUXWS, 0xfc0007fc, 0xf0000320, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvdpuxws XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSPDP, 0xfc0007fc, 0xf0000724, 0x1f0000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSPSXDS, 0xfc0007fc, 0xf0000660, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvspsxds XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSPSXWS, 0xfc0007fc, 0xf0000260, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvspsxws XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSPUXDS, 0xfc0007fc, 0xf0000620, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvspuxds XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSPUXWS, 0xfc0007fc, 0xf0000220, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvspuxws XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSXDDP, 0xfc0007fc, 0xf00007e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSXDSP, 0xfc0007fc, 0xf00006e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSXWDP, 0xfc0007fc, 0xf00003e0, 0x1f0000, // VSX Vector Convert Signed Integer Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVSXWSP, 0xfc0007fc, 0xf00002e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVUXDDP, 0xfc0007fc, 0xf00007a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVUXDSP, 0xfc0007fc, 0xf00006a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVUXWDP, 0xfc0007fc, 0xf00003a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVCVUXWSP, 0xfc0007fc, 0xf00002a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVDIVDP, 0xfc0007f8, 0xf00003c0, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVDIVSP, 0xfc0007f8, 0xf00002c0, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMADDADP, 0xfc0007f8, 0xf0000308, 0x0, // VSX Vector Multiply-Add Double-Precision XX3-form (xvmaddadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMADDASP, 0xfc0007f8, 0xf0000208, 0x0, // VSX Vector Multiply-Add Single-Precision XX3-form (xvmaddasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMAXDP, 0xfc0007f8, 0xf0000700, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMAXSP, 0xfc0007f8, 0xf0000600, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMINDP, 0xfc0007f8, 0xf0000740, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMINSP, 0xfc0007f8, 0xf0000640, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMSUBADP, 0xfc0007f8, 0xf0000388, 0x0, // VSX Vector Multiply-Subtract Double-Precision XX3-form (xvmsubadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMSUBASP, 0xfc0007f8, 0xf0000288, 0x0, // VSX Vector Multiply-Subtract Single-Precision XX3-form (xvmsubasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMULDP, 0xfc0007f8, 0xf0000380, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVMULSP, 0xfc0007f8, 0xf0000280, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVNABSDP, 0xfc0007fc, 0xf00007a4, 0x1f0000, // VSX Vector Negative Absolute Value Double-Precision XX2-form (xvnabsdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVNABSSP, 0xfc0007fc, 0xf00006a4, 0x1f0000, // VSX Vector Negative Absolute Value Single-Precision XX2-form (xvnabssp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVNEGDP, 0xfc0007fc, 0xf00007e4, 0x1f0000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVNEGSP, 0xfc0007fc, 0xf00006e4, 0x1f0000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVNMADDADP, 0xfc0007f8, 0xf0000708, 0x0, // VSX Vector Negative Multiply-Add Double-Precision XX3-form (xvnmaddadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVNMADDASP, 0xfc0007f8, 0xf0000608, 0x0, // VSX Vector Negative Multiply-Add Single-Precision XX3-form (xvnmaddasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVNMSUBADP, 0xfc0007f8, 0xf0000788, 0x0, // VSX Vector Negative Multiply-Subtract Double-Precision XX3-form (xvnmsubadp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVNMSUBASP, 0xfc0007f8, 0xf0000688, 0x0, // VSX Vector Negative Multiply-Subtract Single-Precision XX3-form (xvnmsubasp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVRDPI, 0xfc0007fc, 0xf0000324, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRDPIC, 0xfc0007fc, 0xf00003ac, 0x1f0000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRDPIM, 0xfc0007fc, 0xf00003e4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRDPIP, 0xfc0007fc, 0xf00003a4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRDPIZ, 0xfc0007fc, 0xf0000364, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVREDP, 0xfc0007fc, 0xf0000368, 0x1f0000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRESP, 0xfc0007fc, 0xf0000268, 0x1f0000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSPI, 0xfc0007fc, 0xf0000224, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSPIC, 0xfc0007fc, 0xf00002ac, 0x1f0000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSPIM, 0xfc0007fc, 0xf00002e4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSPIP, 0xfc0007fc, 0xf00002a4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSPIZ, 0xfc0007fc, 0xf0000264, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSQRTEDP, 0xfc0007fc, 0xf0000328, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVRSQRTESP, 0xfc0007fc, 0xf0000228, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVSQRTDP, 0xfc0007fc, 0xf000032c, 0x1f0000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVSQRTSP, 0xfc0007fc, 0xf000022c, 0x1f0000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XVSUBDP, 0xfc0007f8, 0xf0000340, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVSUBSP, 0xfc0007f8, 0xf0000240, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVTDIVDP, 0xfc0007f8, 0xf00003e8, 0x600001, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVTDIVSP, 0xfc0007f8, 0xf00002e8, 0x600001, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XVTSQRTDP, 0xfc0007fc, 0xf00003a8, 0x7f0001, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
-       {XVTSQRTSP, 0xfc0007fc, 0xf00002a8, 0x7f0001, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB)
-               [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
-       {XXLAND, 0xfc0007f8, 0xf0000410, 0x0, // VSX Logical AND XX3-form (xxland XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLANDC, 0xfc0007f8, 0xf0000450, 0x0, // VSX Logical AND with Complement XX3-form (xxlandc XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLEQV, 0xfc0007f8, 0xf00005d0, 0x0, // VSX Logical Equivalence XX3-form (xxleqv XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLNAND, 0xfc0007f8, 0xf0000590, 0x0, // VSX Logical NAND XX3-form (xxlnand XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLORC, 0xfc0007f8, 0xf0000550, 0x0, // VSX Logical OR with Complement XX3-form (xxlorc XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLNOR, 0xfc0007f8, 0xf0000510, 0x0, // VSX Logical NOR XX3-form (xxlnor XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLOR, 0xfc0007f8, 0xf0000490, 0x0, // VSX Logical OR XX3-form (xxlor XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXLXOR, 0xfc0007f8, 0xf00004d0, 0x0, // VSX Logical XOR XX3-form (xxlxor XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXMRGHW, 0xfc0007f8, 0xf0000090, 0x0, // VSX Merge High Word XX3-form (xxmrghw XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXMRGLW, 0xfc0007f8, 0xf0000190, 0x0, // VSX Merge Low Word XX3-form (xxmrglw XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
-       {XXPERM, 0xfc0007f8, 0xf00000d0, 0x0, // VSX Permute XX3-form (xxperm XT,XA,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
-       {XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}},
-       {XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
-       {XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}},
-       {XXBRD, 0xfc1f07fc, 0xf017076c, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XXBRW, 0xfc1f07fc, 0xf00f076c, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {XXBRH, 0xfc1f07fc, 0xf007076c, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
-       {BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVADDIW, 0xfc0007ff, 0x10000202, 0x0, // Vector Add Immediate Word EVX-form (evaddiw RT,RB,UI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_11_15}},
-       {EVADDSMIAAW, 0xfc0007ff, 0x100004c9, 0xf800, // Vector Add Signed, Modulo, Integer to Accumulator Word EVX-form (evaddsmiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVADDSSIAAW, 0xfc0007ff, 0x100004c1, 0xf800, // Vector Add Signed, Saturate, Integer to Accumulator Word EVX-form (evaddssiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVADDUMIAAW, 0xfc0007ff, 0x100004c8, 0xf800, // Vector Add Unsigned, Modulo, Integer to Accumulator Word EVX-form (evaddumiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVADDUSIAAW, 0xfc0007ff, 0x100004c0, 0xf800, // Vector Add Unsigned, Saturate, Integer to Accumulator Word EVX-form (evaddusiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVADDW, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Word EVX-form (evaddw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVAND, 0xfc0007ff, 0x10000211, 0x0, // Vector AND EVX-form (evand RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVCMPEQ, 0xfc0007ff, 0x10000234, 0x600000, // Vector Compare Equal EVX-form (evcmpeq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVANDC, 0xfc0007ff, 0x10000212, 0x0, // Vector AND with Complement EVX-form (evandc RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVCMPGTS, 0xfc0007ff, 0x10000231, 0x600000, // Vector Compare Greater Than Signed EVX-form (evcmpgts BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVCMPGTU, 0xfc0007ff, 0x10000230, 0x600000, // Vector Compare Greater Than Unsigned EVX-form (evcmpgtu BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVCMPLTU, 0xfc0007ff, 0x10000232, 0x600000, // Vector Compare Less Than Unsigned EVX-form (evcmpltu BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVCMPLTS, 0xfc0007ff, 0x10000233, 0x600000, // Vector Compare Less Than Signed EVX-form (evcmplts BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVCNTLSW, 0xfc0007ff, 0x1000020e, 0xf800, // Vector Count Leading Signed Bits Word EVX-form (evcntlsw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVCNTLZW, 0xfc0007ff, 0x1000020d, 0xf800, // Vector Count Leading Zeros Word EVX-form (evcntlzw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVDIVWS, 0xfc0007ff, 0x100004c6, 0x0, // Vector Divide Word Signed EVX-form (evdivws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVDIVWU, 0xfc0007ff, 0x100004c7, 0x0, // Vector Divide Word Unsigned EVX-form (evdivwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVEQV, 0xfc0007ff, 0x10000219, 0x0, // Vector Equivalent EVX-form (eveqv RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVEXTSB, 0xfc0007ff, 0x1000020a, 0xf800, // Vector Extend Sign Byte EVX-form (evextsb RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVEXTSH, 0xfc0007ff, 0x1000020b, 0xf800, // Vector Extend Sign Halfword EVX-form (evextsh RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVLDD, 0xfc0007ff, 0x10000301, 0x0, // Vector Load Double Word into Double Word EVX-form (evldd RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLDH, 0xfc0007ff, 0x10000305, 0x0, // Vector Load Double into Four Halfwords EVX-form (evldh RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLDDX, 0xfc0007ff, 0x10000300, 0x0, // Vector Load Double Word into Double Word Indexed EVX-form (evlddx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLDHX, 0xfc0007ff, 0x10000304, 0x0, // Vector Load Double into Four Halfwords Indexed EVX-form (evldhx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLDW, 0xfc0007ff, 0x10000303, 0x0, // Vector Load Double into Two Words EVX-form (evldw RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLHHESPLAT, 0xfc0007ff, 0x10000309, 0x0, // Vector Load Halfword into Halfwords Even and Splat EVX-form (evlhhesplat RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLDWX, 0xfc0007ff, 0x10000302, 0x0, // Vector Load Double into Two Words Indexed EVX-form (evldwx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLHHESPLATX, 0xfc0007ff, 0x10000308, 0x0, // Vector Load Halfword into Halfwords Even and Splat Indexed EVX-form (evlhhesplatx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLHHOSSPLAT, 0xfc0007ff, 0x1000030f, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat EVX-form (evlhhossplat RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLHHOUSPLAT, 0xfc0007ff, 0x1000030d, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat EVX-form (evlhhousplat RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLHHOSSPLATX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat Indexed EVX-form (evlhhossplatx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLHHOUSPLATX, 0xfc0007ff, 0x1000030c, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed EVX-form (evlhhousplatx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLWHE, 0xfc0007ff, 0x10000311, 0x0, // Vector Load Word into Two Halfwords Even EVX-form (evlwhe RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLWHOS, 0xfc0007ff, 0x10000317, 0x0, // Vector Load Word into Two Halfwords Odd Signed (with sign extension) EVX-form (evlwhos RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLWHEX, 0xfc0007ff, 0x10000310, 0x0, // Vector Load Word into Two Halfwords Even Indexed EVX-form (evlwhex RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLWHOSX, 0xfc0007ff, 0x10000316, 0x0, // Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) EVX-form (evlwhosx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLWHOU, 0xfc0007ff, 0x10000315, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) EVX-form (evlwhou RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLWHSPLAT, 0xfc0007ff, 0x1000031d, 0x0, // Vector Load Word into Two Halfwords and Splat EVX-form (evlwhsplat RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVLWHOUX, 0xfc0007ff, 0x10000314, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) EVX-form (evlwhoux RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLWHSPLATX, 0xfc0007ff, 0x1000031c, 0x0, // Vector Load Word into Two Halfwords and Splat Indexed EVX-form (evlwhsplatx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLWWSPLAT, 0xfc0007ff, 0x10000319, 0x0, // Vector Load Word into Word and Splat EVX-form (evlwwsplat RT,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVMERGEHI, 0xfc0007ff, 0x1000022c, 0x0, // Vector Merge High EVX-form (evmergehi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLWWSPLATX, 0xfc0007ff, 0x10000318, 0x0, // Vector Load Word into Word and Splat Indexed EVX-form (evlwwsplatx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMERGELO, 0xfc0007ff, 0x1000022d, 0x0, // Vector Merge Low EVX-form (evmergelo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMERGEHILO, 0xfc0007ff, 0x1000022e, 0x0, // Vector Merge High/Low EVX-form (evmergehilo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEGSMFAA, 0xfc0007ff, 0x1000052b, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhegsmfaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMERGELOHI, 0xfc0007ff, 0x1000022f, 0x0, // Vector Merge Low/High EVX-form (evmergelohi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEGSMFAN, 0xfc0007ff, 0x100005ab, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhegsmfan RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEGSMIAA, 0xfc0007ff, 0x10000529, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhegsmiaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEGUMIAA, 0xfc0007ff, 0x10000528, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhegumiaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEGSMIAN, 0xfc0007ff, 0x100005a9, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhegsmian RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEGUMIAN, 0xfc0007ff, 0x100005a8, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhegumian RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMF, 0xfc0007ff, 0x1000040b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional EVX-form (evmhesmf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMFAAW, 0xfc0007ff, 0x1000050b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhesmfaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMFA, 0xfc0007ff, 0x1000042b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator EVX-form (evmhesmfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMFANW, 0xfc0007ff, 0x1000058b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhesmfanw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMI, 0xfc0007ff, 0x10000409, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer EVX-form (evmhesmi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMIAAW, 0xfc0007ff, 0x10000509, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhesmiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMIA, 0xfc0007ff, 0x10000429, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator EVX-form (evmhesmia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESMIANW, 0xfc0007ff, 0x10000589, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhesmianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESSF, 0xfc0007ff, 0x10000403, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional EVX-form (evmhessf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESSFA, 0xfc0007ff, 0x10000423, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator EVX-form (evmhessfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESSFAAW, 0xfc0007ff, 0x10000503, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhessfaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESSFANW, 0xfc0007ff, 0x10000583, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhessfanw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESSIAAW, 0xfc0007ff, 0x10000501, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhessiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHESSIANW, 0xfc0007ff, 0x10000581, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhessianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEUMI, 0xfc0007ff, 0x10000408, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer EVX-form (evmheumi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEUMIAAW, 0xfc0007ff, 0x10000508, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmheumiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEUMIA, 0xfc0007ff, 0x10000428, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator EVX-form (evmheumia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEUMIANW, 0xfc0007ff, 0x10000588, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmheumianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEUSIAAW, 0xfc0007ff, 0x10000500, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmheusiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHEUSIANW, 0xfc0007ff, 0x10000580, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmheusianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOGSMFAA, 0xfc0007ff, 0x1000052f, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhogsmfaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOGSMIAA, 0xfc0007ff, 0x1000052d, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhogsmiaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOGSMFAN, 0xfc0007ff, 0x100005af, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhogsmfan RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOGSMIAN, 0xfc0007ff, 0x100005ad, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhogsmian RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOGUMIAA, 0xfc0007ff, 0x1000052c, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhogumiaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMF, 0xfc0007ff, 0x1000040f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional EVX-form (evmhosmf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOGUMIAN, 0xfc0007ff, 0x100005ac, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhogumian RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMFA, 0xfc0007ff, 0x1000042f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator EVX-form (evmhosmfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMFAAW, 0xfc0007ff, 0x1000050f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhosmfaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMI, 0xfc0007ff, 0x1000040d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer EVX-form (evmhosmi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMFANW, 0xfc0007ff, 0x1000058f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhosmfanw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMIA, 0xfc0007ff, 0x1000042d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator EVX-form (evmhosmia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMIAAW, 0xfc0007ff, 0x1000050d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhosmiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSMIANW, 0xfc0007ff, 0x1000058d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhosmianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSSF, 0xfc0007ff, 0x10000407, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional EVX-form (evmhossf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSSFA, 0xfc0007ff, 0x10000427, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator EVX-form (evmhossfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSSFAAW, 0xfc0007ff, 0x10000507, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhossfaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSSFANW, 0xfc0007ff, 0x10000587, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhossfanw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSSIAAW, 0xfc0007ff, 0x10000505, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhossiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOUMI, 0xfc0007ff, 0x1000040c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer EVX-form (evmhoumi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOSSIANW, 0xfc0007ff, 0x10000585, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhossianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOUMIA, 0xfc0007ff, 0x1000042c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator EVX-form (evmhoumia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOUMIAAW, 0xfc0007ff, 0x1000050c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmhoumiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOUSIAAW, 0xfc0007ff, 0x10000504, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmhousiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOUMIANW, 0xfc0007ff, 0x1000058c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhoumianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMHOUSIANW, 0xfc0007ff, 0x10000584, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhousianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMRA, 0xfc0007ff, 0x100004c4, 0xf800, // Initialize Accumulator EVX-form (evmra RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVMWHSMF, 0xfc0007ff, 0x1000044f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional EVX-form (evmwhsmf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHSMI, 0xfc0007ff, 0x1000044d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer EVX-form (evmwhsmi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHSMFA, 0xfc0007ff, 0x1000046f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional to Accumulator EVX-form (evmwhsmfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHSMIA, 0xfc0007ff, 0x1000046d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer to Accumulator EVX-form (evmwhsmia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHSSF, 0xfc0007ff, 0x10000447, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional EVX-form (evmwhssf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHUMI, 0xfc0007ff, 0x1000044c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer EVX-form (evmwhumi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHSSFA, 0xfc0007ff, 0x10000467, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional to Accumulator EVX-form (evmwhssfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWHUMIA, 0xfc0007ff, 0x1000046c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator EVX-form (evmwhumia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLSMIAAW, 0xfc0007ff, 0x10000549, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words EVX-form (evmwlsmiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLSSIAAW, 0xfc0007ff, 0x10000541, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate into Words EVX-form (evmwlssiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLSMIANW, 0xfc0007ff, 0x100005c9, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlsmianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLSSIANW, 0xfc0007ff, 0x100005c1, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlssianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLUMI, 0xfc0007ff, 0x10000448, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer EVX-form (evmwlumi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLUMIAAW, 0xfc0007ff, 0x10000548, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmwlumiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLUMIA, 0xfc0007ff, 0x10000468, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator EVX-form (evmwlumia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLUMIANW, 0xfc0007ff, 0x100005c8, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlumianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLUSIAAW, 0xfc0007ff, 0x10000540, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmwlusiaaw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMF, 0xfc0007ff, 0x1000045b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional EVX-form (evmwsmf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWLUSIANW, 0xfc0007ff, 0x100005c0, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlusianw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMFA, 0xfc0007ff, 0x1000047b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional to Accumulator EVX-form (evmwsmfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMFAA, 0xfc0007ff, 0x1000055b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate EVX-form (evmwsmfaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMI, 0xfc0007ff, 0x10000459, 0x0, // Vector Multiply Word Signed, Modulo, Integer EVX-form (evmwsmi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMIAA, 0xfc0007ff, 0x10000559, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate EVX-form (evmwsmiaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMFAN, 0xfc0007ff, 0x100005db, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmwsmfan RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMIA, 0xfc0007ff, 0x10000479, 0x0, // Vector Multiply Word Signed, Modulo, Integer to Accumulator EVX-form (evmwsmia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSMIAN, 0xfc0007ff, 0x100005d9, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative EVX-form (evmwsmian RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSSF, 0xfc0007ff, 0x10000453, 0x0, // Vector Multiply Word Signed, Saturate, Fractional EVX-form (evmwssf RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSSFA, 0xfc0007ff, 0x10000473, 0x0, // Vector Multiply Word Signed, Saturate, Fractional to Accumulator EVX-form (evmwssfa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSSFAA, 0xfc0007ff, 0x10000553, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate EVX-form (evmwssfaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWUMI, 0xfc0007ff, 0x10000458, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer EVX-form (evmwumi RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWSSFAN, 0xfc0007ff, 0x100005d3, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative EVX-form (evmwssfan RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWUMIA, 0xfc0007ff, 0x10000478, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer to Accumulator EVX-form (evmwumia RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWUMIAA, 0xfc0007ff, 0x10000558, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate EVX-form (evmwumiaa RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVNAND, 0xfc0007ff, 0x1000021e, 0x0, // Vector NAND EVX-form (evnand RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVMWUMIAN, 0xfc0007ff, 0x100005d8, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmwumian RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVNEG, 0xfc0007ff, 0x10000209, 0xf800, // Vector Negate EVX-form (evneg RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVNOR, 0xfc0007ff, 0x10000218, 0x0, // Vector NOR EVX-form (evnor RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVORC, 0xfc0007ff, 0x1000021b, 0x0, // Vector OR with Complement EVX-form (evorc RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVOR, 0xfc0007ff, 0x10000217, 0x0, // Vector OR EVX-form (evor RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVRLW, 0xfc0007ff, 0x10000228, 0x0, // Vector Rotate Left Word EVX-form (evrlw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVRLWI, 0xfc0007ff, 0x1000022a, 0x0, // Vector Rotate Left Word Immediate EVX-form (evrlwi RT,RA,UI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
-       {EVSEL, 0xfc0007f8, 0x10000278, 0x0, // Vector Select EVS-form (evsel RT,RA,RB,BFA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegField_29_31}},
-       {EVRNDW, 0xfc0007ff, 0x1000020c, 0xf800, // Vector Round Word EVX-form (evrndw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVSLW, 0xfc0007ff, 0x10000224, 0x0, // Vector Shift Left Word EVX-form (evslw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSPLATFI, 0xfc0007ff, 0x1000022b, 0xf800, // Vector Splat Fractional Immediate EVX-form (evsplatfi RT,SI)
-               [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}},
-       {EVSRWIS, 0xfc0007ff, 0x10000223, 0x0, // Vector Shift Right Word Immediate Signed EVX-form (evsrwis RT,RA,UI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
-       {EVSLWI, 0xfc0007ff, 0x10000226, 0x0, // Vector Shift Left Word Immediate EVX-form (evslwi RT,RA,UI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
-       {EVSPLATI, 0xfc0007ff, 0x10000229, 0xf800, // Vector Splat Immediate EVX-form (evsplati RT,SI)
-               [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}},
-       {EVSRWIU, 0xfc0007ff, 0x10000222, 0x0, // Vector Shift Right Word Immediate Unsigned EVX-form (evsrwiu RT,RA,UI)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
-       {EVSRWS, 0xfc0007ff, 0x10000221, 0x0, // Vector Shift Right Word Signed EVX-form (evsrws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTDD, 0xfc0007ff, 0x10000321, 0x0, // Vector Store Double of Double EVX-form (evstdd RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSRWU, 0xfc0007ff, 0x10000220, 0x0, // Vector Shift Right Word Unsigned EVX-form (evsrwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTDDX, 0xfc0007ff, 0x10000320, 0x0, // Vector Store Double of Double Indexed EVX-form (evstddx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTDH, 0xfc0007ff, 0x10000325, 0x0, // Vector Store Double of Four Halfwords EVX-form (evstdh RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSTDW, 0xfc0007ff, 0x10000323, 0x0, // Vector Store Double of Two Words EVX-form (evstdw RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSTDHX, 0xfc0007ff, 0x10000324, 0x0, // Vector Store Double of Four Halfwords Indexed EVX-form (evstdhx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTDWX, 0xfc0007ff, 0x10000322, 0x0, // Vector Store Double of Two Words Indexed EVX-form (evstdwx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTWHE, 0xfc0007ff, 0x10000331, 0x0, // Vector Store Word of Two Halfwords from Even EVX-form (evstwhe RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSTWHO, 0xfc0007ff, 0x10000335, 0x0, // Vector Store Word of Two Halfwords from Odd EVX-form (evstwho RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSTWWE, 0xfc0007ff, 0x10000339, 0x0, // Vector Store Word of Word from Even EVX-form (evstwwe RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSTWHEX, 0xfc0007ff, 0x10000330, 0x0, // Vector Store Word of Two Halfwords from Even Indexed EVX-form (evstwhex RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTWHOX, 0xfc0007ff, 0x10000334, 0x0, // Vector Store Word of Two Halfwords from Odd Indexed EVX-form (evstwhox RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTWWEX, 0xfc0007ff, 0x10000338, 0x0, // Vector Store Word of Word from Even Indexed EVX-form (evstwwex RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTWWO, 0xfc0007ff, 0x1000033d, 0x0, // Vector Store Word of Word from Odd EVX-form (evstwwo RS,D(RA))
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
-       {EVSUBFSMIAAW, 0xfc0007ff, 0x100004cb, 0xf800, // Vector Subtract Signed, Modulo, Integer to Accumulator Word EVX-form (evsubfsmiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVSTWWOX, 0xfc0007ff, 0x1000033c, 0x0, // Vector Store Word of Word from Odd Indexed EVX-form (evstwwox RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSUBFSSIAAW, 0xfc0007ff, 0x100004c3, 0xf800, // Vector Subtract Signed, Saturate, Integer to Accumulator Word EVX-form (evsubfssiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVSUBFUMIAAW, 0xfc0007ff, 0x100004ca, 0xf800, // Vector Subtract Unsigned, Modulo, Integer to Accumulator Word EVX-form (evsubfumiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVSUBFUSIAAW, 0xfc0007ff, 0x100004c2, 0xf800, // Vector Subtract Unsigned, Saturate, Integer to Accumulator Word EVX-form (evsubfusiaaw RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVSUBFW, 0xfc0007ff, 0x10000204, 0x0, // Vector Subtract from Word EVX-form (evsubfw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSUBIFW, 0xfc0007ff, 0x10000206, 0x0, // Vector Subtract Immediate from Word EVX-form (evsubifw RT,UI,RB)
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_15, ap_Reg_16_20}},
-       {EVXOR, 0xfc0007ff, 0x10000216, 0x0, // Vector XOR EVX-form (evxor RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSABS, 0xfc0007ff, 0x10000284, 0xf800, // Vector Floating-Point Single-Precision Absolute Value EVX-form (evfsabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVFSNABS, 0xfc0007ff, 0x10000285, 0xf800, // Vector Floating-Point Single-Precision Negative Absolute Value EVX-form (evfsnabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVFSNEG, 0xfc0007ff, 0x10000286, 0xf800, // Vector Floating-Point Single-Precision Negate EVX-form (evfsneg RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EVFSADD, 0xfc0007ff, 0x10000280, 0x0, // Vector Floating-Point Single-Precision Add EVX-form (evfsadd RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSMUL, 0xfc0007ff, 0x10000288, 0x0, // Vector Floating-Point Single-Precision Multiply EVX-form (evfsmul RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSSUB, 0xfc0007ff, 0x10000281, 0x0, // Vector Floating-Point Single-Precision Subtract EVX-form (evfssub RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSDIV, 0xfc0007ff, 0x10000289, 0x0, // Vector Floating-Point Single-Precision Divide EVX-form (evfsdiv RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSCMPGT, 0xfc0007ff, 0x1000028c, 0x600000, // Vector Floating-Point Single-Precision Compare Greater Than EVX-form (evfscmpgt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSCMPLT, 0xfc0007ff, 0x1000028d, 0x600000, // Vector Floating-Point Single-Precision Compare Less Than EVX-form (evfscmplt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSCMPEQ, 0xfc0007ff, 0x1000028e, 0x600000, // Vector Floating-Point Single-Precision Compare Equal EVX-form (evfscmpeq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSTSTGT, 0xfc0007ff, 0x1000029c, 0x600000, // Vector Floating-Point Single-Precision Test Greater Than EVX-form (evfststgt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSTSTLT, 0xfc0007ff, 0x1000029d, 0x600000, // Vector Floating-Point Single-Precision Test Less Than EVX-form (evfststlt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSTSTEQ, 0xfc0007ff, 0x1000029e, 0x600000, // Vector Floating-Point Single-Precision Test Equal EVX-form (evfststeq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVFSCFSI, 0xfc0007ff, 0x10000291, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Integer EVX-form (evfscfsi RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCFSF, 0xfc0007ff, 0x10000293, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Fraction EVX-form (evfscfsf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCFUI, 0xfc0007ff, 0x10000290, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (evfscfui RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCFUF, 0xfc0007ff, 0x10000292, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (evfscfuf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCTSI, 0xfc0007ff, 0x10000295, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer EVX-form (evfsctsi RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCTUI, 0xfc0007ff, 0x10000294, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (evfsctui RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCTSIZ, 0xfc0007ff, 0x1000029a, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (evfsctsiz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCTUIZ, 0xfc0007ff, 0x10000298, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (evfsctuiz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCTSF, 0xfc0007ff, 0x10000297, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Fraction EVX-form (evfsctsf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EVFSCTUF, 0xfc0007ff, 0x10000296, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (evfsctuf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSABS, 0xfc0007ff, 0x100002c4, 0xf800, // Floating-Point Single-Precision Absolute Value EVX-form (efsabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EFSNEG, 0xfc0007ff, 0x100002c6, 0xf800, // Floating-Point Single-Precision Negate EVX-form (efsneg RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EFSNABS, 0xfc0007ff, 0x100002c5, 0xf800, // Floating-Point Single-Precision Negative Absolute Value EVX-form (efsnabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EFSADD, 0xfc0007ff, 0x100002c0, 0x0, // Floating-Point Single-Precision Add EVX-form (efsadd RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSMUL, 0xfc0007ff, 0x100002c8, 0x0, // Floating-Point Single-Precision Multiply EVX-form (efsmul RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSSUB, 0xfc0007ff, 0x100002c1, 0x0, // Floating-Point Single-Precision Subtract EVX-form (efssub RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSDIV, 0xfc0007ff, 0x100002c9, 0x0, // Floating-Point Single-Precision Divide EVX-form (efsdiv RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSCMPGT, 0xfc0007ff, 0x100002cc, 0x600000, // Floating-Point Single-Precision Compare Greater Than EVX-form (efscmpgt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSCMPLT, 0xfc0007ff, 0x100002cd, 0x600000, // Floating-Point Single-Precision Compare Less Than EVX-form (efscmplt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSCMPEQ, 0xfc0007ff, 0x100002ce, 0x600000, // Floating-Point Single-Precision Compare Equal EVX-form (efscmpeq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSTSTGT, 0xfc0007ff, 0x100002dc, 0x600000, // Floating-Point Single-Precision Test Greater Than EVX-form (efststgt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSTSTLT, 0xfc0007ff, 0x100002dd, 0x600000, // Floating-Point Single-Precision Test Less Than EVX-form (efststlt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSTSTEQ, 0xfc0007ff, 0x100002de, 0x600000, // Floating-Point Single-Precision Test Equal EVX-form (efststeq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFSCFSI, 0xfc0007ff, 0x100002d1, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Integer EVX-form (efscfsi RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCFSF, 0xfc0007ff, 0x100002d3, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Fraction EVX-form (efscfsf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCTSI, 0xfc0007ff, 0x100002d5, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer EVX-form (efsctsi RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCFUI, 0xfc0007ff, 0x100002d0, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (efscfui RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCFUF, 0xfc0007ff, 0x100002d2, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (efscfuf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCTUI, 0xfc0007ff, 0x100002d4, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (efsctui RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCTSIZ, 0xfc0007ff, 0x100002da, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (efsctsiz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCTSF, 0xfc0007ff, 0x100002d7, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Fraction EVX-form (efsctsf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCTUIZ, 0xfc0007ff, 0x100002d8, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (efsctuiz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCTUF, 0xfc0007ff, 0x100002d6, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (efsctuf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDABS, 0xfc0007ff, 0x100002e4, 0xf800, // Floating-Point Double-Precision Absolute Value EVX-form (efdabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EFDNEG, 0xfc0007ff, 0x100002e6, 0xf800, // Floating-Point Double-Precision Negate EVX-form (efdneg RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EFDNABS, 0xfc0007ff, 0x100002e5, 0xf800, // Floating-Point Double-Precision Negative Absolute Value EVX-form (efdnabs RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {EFDADD, 0xfc0007ff, 0x100002e0, 0x0, // Floating-Point Double-Precision Add EVX-form (efdadd RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDMUL, 0xfc0007ff, 0x100002e8, 0x0, // Floating-Point Double-Precision Multiply EVX-form (efdmul RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDSUB, 0xfc0007ff, 0x100002e1, 0x0, // Floating-Point Double-Precision Subtract EVX-form (efdsub RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDDIV, 0xfc0007ff, 0x100002e9, 0x0, // Floating-Point Double-Precision Divide EVX-form (efddiv RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDCMPGT, 0xfc0007ff, 0x100002ec, 0x600000, // Floating-Point Double-Precision Compare Greater Than EVX-form (efdcmpgt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDCMPEQ, 0xfc0007ff, 0x100002ee, 0x600000, // Floating-Point Double-Precision Compare Equal EVX-form (efdcmpeq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDCMPLT, 0xfc0007ff, 0x100002ed, 0x600000, // Floating-Point Double-Precision Compare Less Than EVX-form (efdcmplt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDTSTGT, 0xfc0007ff, 0x100002fc, 0x600000, // Floating-Point Double-Precision Test Greater Than EVX-form (efdtstgt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDTSTLT, 0xfc0007ff, 0x100002fd, 0x600000, // Floating-Point Double-Precision Test Less Than EVX-form (efdtstlt BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDCFSI, 0xfc0007ff, 0x100002f1, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer EVX-form (efdcfsi RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDTSTEQ, 0xfc0007ff, 0x100002fe, 0x600000, // Floating-Point Double-Precision Test Equal EVX-form (efdtsteq BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {EFDCFUI, 0xfc0007ff, 0x100002f0, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer EVX-form (efdcfui RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCFSID, 0xfc0007ff, 0x100002e3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer Doubleword EVX-form (efdcfsid RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCFSF, 0xfc0007ff, 0x100002f3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Fraction EVX-form (efdcfsf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCFUF, 0xfc0007ff, 0x100002f2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Fraction EVX-form (efdcfuf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCFUID, 0xfc0007ff, 0x100002e2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer Doubleword EVX-form (efdcfuid RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTSI, 0xfc0007ff, 0x100002f5, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer EVX-form (efdctsi RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTUI, 0xfc0007ff, 0x100002f4, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer EVX-form (efdctui RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTSIDZ, 0xfc0007ff, 0x100002eb, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero EVX-form (efdctsidz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTUIDZ, 0xfc0007ff, 0x100002ea, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero EVX-form (efdctuidz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTSIZ, 0xfc0007ff, 0x100002fa, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero EVX-form (efdctsiz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTSF, 0xfc0007ff, 0x100002f7, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Fraction EVX-form (efdctsf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTUF, 0xfc0007ff, 0x100002f6, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Fraction EVX-form (efdctuf RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCTUIZ, 0xfc0007ff, 0x100002f8, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero EVX-form (efdctuiz RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFDCFS, 0xfc0007ff, 0x100002ef, 0x1f0000, // Floating-Point Double-Precision Convert from Single-Precision EVX-form (efdcfs RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {EFSCFD, 0xfc0007ff, 0x100002cf, 0x1f0000, // Floating-Point Single-Precision Convert from Double-Precision EVX-form (efscfd RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {DLMZB, 0xfc0007ff, 0x7c00009c, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {DLMZBCC, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {MACCHW, 0xfc0007ff, 0x10000158, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWCC, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWO, 0xfc0007ff, 0x10000558, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWOCC, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWS, 0xfc0007ff, 0x100001d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSCC, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSOCC, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWU, 0xfc0007ff, 0x10000118, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWUCC, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWUO, 0xfc0007ff, 0x10000518, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWUOCC, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSU, 0xfc0007ff, 0x10000198, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSUCC, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACCHWSUOCC, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHW, 0xfc0007ff, 0x10000058, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWCC, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWO, 0xfc0007ff, 0x10000458, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWOCC, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWS, 0xfc0007ff, 0x100000d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSCC, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSOCC, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWU, 0xfc0007ff, 0x10000018, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWUCC, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWUO, 0xfc0007ff, 0x10000418, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWUOCC, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSU, 0xfc0007ff, 0x10000098, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSUCC, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACHHWSUOCC, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHW, 0xfc0007ff, 0x10000358, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWCC, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWO, 0xfc0007ff, 0x10000758, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWOCC, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWS, 0xfc0007ff, 0x100003d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSCC, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSOCC, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWU, 0xfc0007ff, 0x10000318, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWUCC, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWUO, 0xfc0007ff, 0x10000718, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWUOCC, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULCHW, 0xfc0007ff, 0x10000150, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULCHWCC, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSU, 0xfc0007ff, 0x10000398, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSUCC, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MACLHWSUOCC, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULCHWU, 0xfc0007ff, 0x10000110, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULCHWUCC, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHHW, 0xfc0007ff, 0x10000050, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHHWCC, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLHW, 0xfc0007ff, 0x10000350, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLHWCC, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHHWU, 0xfc0007ff, 0x10000010, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULHHWUCC, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLHWU, 0xfc0007ff, 0x10000310, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MULLHWUCC, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHW, 0xfc0007ff, 0x1000015c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWCC, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWOCC, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWSCC, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACCHWSOCC, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHW, 0xfc0007ff, 0x1000005c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWCC, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWOCC, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWSCC, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACHHWSOCC, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHW, 0xfc0007ff, 0x1000035c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWCC, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWOCC, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWSCC, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {NMACLHWSOCC, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001, // Instruction Cache Block Invalidate X-form (icbi RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBT, 0xfc0007fe, 0x7c00002c, 0x2000001, // Instruction Cache Block Touch X-form (icbt CT, RA, RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBA, 0xfc0007fe, 0x7c0005ec, 0x3e00001, // Data Cache Block Allocate X-form (dcba RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt RA,RB,TH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
-       {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt TH,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
-       {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst TH,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBZ, 0xfc0007fe, 0x7c0007ec, 0x3e00001, // Data Cache Block set to Zero X-form (dcbz RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBST, 0xfc0007fe, 0x7c00006c, 0x3e00001, // Data Cache Block Store X-form (dcbst RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBF, 0xfc0007fe, 0x7c0000ac, 0x3800001, // Data Cache Block Flush X-form (dcbf RA,RB,L)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}},
-       {ISYNC, 0xfc0007fe, 0x4c00012c, 0x3fff801, // Instruction Synchronize XL-form (isync)
-               [5]*argField{}},
-       {LBARX, 0xfc0007ff, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LBARX, 0xfc0007fe, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB,EH)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {LHARX, 0xfc0007ff, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHARX, 0xfc0007fe, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB,EH)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWARX, 0xfc0007fe, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB,EH)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {STBCXCC, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHCXCC, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWCXCC, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDARX, 0xfc0007ff, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDARX, 0xfc0007fe, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {STDCXCC, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LQARX, 0xfc0007ff, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LQARX, 0xfc0007fe, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
-       {STQCXCC, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801, // Synchronize X-form (sync L, E)
-               [5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}},
-       {EIEIO, 0xfc0007fe, 0x7c0006ac, 0x3fff801, // Enforce In-order Execution of I/O X-form (eieio)
-               [5]*argField{}},
-       {MBAR, 0xfc0007fe, 0x7c0006ac, 0x1ff801, // Memory Barrier X-form (mbar MO)
-               [5]*argField{ap_ImmUnsigned_6_10}},
-       {WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801, // Wait X-form (wait WC)
-               [5]*argField{ap_ImmUnsigned_9_10}},
-       {TBEGINCC, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R)
-               [5]*argField{ap_ImmUnsigned_10_10}},
-       {TENDCC, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A)
-               [5]*argField{ap_ImmUnsigned_6_6}},
-       {TABORTCC, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA)
-               [5]*argField{ap_Reg_11_15}},
-       {TABORTWCCC, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TABORTWCICC, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
-       {TABORTDCCC, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TABORTDCICC, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
-       {TSRCC, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L)
-               [5]*argField{ap_ImmUnsigned_10_10}},
-       {TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801, // Transaction Check X-form (tcheck BF)
-               [5]*argField{ap_CondRegField_6_8}},
-       {MFTB, 0xfc0007fe, 0x7c0002e6, 0x1, // Move From Time Base XFX-form (mftb RT,TBR)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
-       {RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001, // Return from Event-Based Branch XL-form (rfebb S)
-               [5]*argField{ap_ImmUnsigned_20_20}},
-       {LBDX, 0xfc0007fe, 0x7c000406, 0x1, // Load Byte with Decoration Indexed X-form (lbdx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHDX, 0xfc0007fe, 0x7c000446, 0x1, // Load Halfword with Decoration Indexed X-form (lhdx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWDX, 0xfc0007fe, 0x7c000486, 0x1, // Load Word with Decoration Indexed X-form (lwdx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDDX, 0xfc0007fe, 0x7c0004c6, 0x1, // Load Doubleword with Decoration Indexed X-form (lddx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LFDDX, 0xfc0007fe, 0x7c000646, 0x1, // Load Floating Doubleword with Decoration Indexed X-form (lfddx FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STBDX, 0xfc0007fe, 0x7c000506, 0x1, // Store Byte with Decoration Indexed X-form (stbdx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHDX, 0xfc0007fe, 0x7c000546, 0x1, // Store Halfword with Decoration Indexed X-form (sthdx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWDX, 0xfc0007fe, 0x7c000586, 0x1, // Store Word with Decoration Indexed X-form (stwdx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STDDX, 0xfc0007fe, 0x7c0005c6, 0x1, // Store Doubleword with Decoration Indexed X-form (stddx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFDDX, 0xfc0007fe, 0x7c000746, 0x1, // Store Floating Doubleword with Decoration Indexed X-form (stfddx FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DSN, 0xfc0007fe, 0x7c0003c6, 0x3e00001, // Decorated Storage Notify X-form (dsn RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {ECIWX, 0xfc0007fe, 0x7c00026c, 0x1, // External Control In Word Indexed X-form (eciwx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ECOWX, 0xfc0007fe, 0x7c00036c, 0x1, // External Control Out Word Indexed X-form (ecowx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
-               [5]*argField{ap_ImmUnsigned_20_26}},
-       {RFID, 0xfc0007fe, 0x4c000024, 0x3fff801, // Return From Interrupt Doubleword XL-form (rfid)
-               [5]*argField{}},
-       {HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801, // Hypervisor Return From Interrupt Doubleword XL-form (hrfid)
-               [5]*argField{}},
-       {DOZE, 0xfc0007fe, 0x4c000324, 0x3fff801, // Doze XL-form (doze)
-               [5]*argField{}},
-       {NAP, 0xfc0007fe, 0x4c000364, 0x3fff801, // Nap XL-form (nap)
-               [5]*argField{}},
-       {SLEEP, 0xfc0007fe, 0x4c0003a4, 0x3fff801, // Sleep XL-form (sleep)
-               [5]*argField{}},
-       {RVWINKLE, 0xfc0007fe, 0x4c0003e4, 0x3fff801, // Rip Van Winkle XL-form (rvwinkle)
-               [5]*argField{}},
-       {LBZCIX, 0xfc0007fe, 0x7c0006aa, 0x1, // Load Byte and Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWZCIX, 0xfc0007fe, 0x7c00062a, 0x1, // Load Word and Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHZCIX, 0xfc0007fe, 0x7c00066a, 0x1, // Load Halfword and Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDCIX, 0xfc0007fe, 0x7c0006ea, 0x1, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STBCIX, 0xfc0007fe, 0x7c0007aa, 0x1, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWCIX, 0xfc0007fe, 0x7c00072a, 0x1, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHCIX, 0xfc0007fe, 0x7c00076a, 0x1, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TRECLAIMCC, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA)
-               [5]*argField{ap_Reg_11_15}},
-       {TRECHKPTCC, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.)
-               [5]*argField{}},
-       {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
-               [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-       {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
-       {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To Machine State Register X-form (mtmsr RS,L)
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
-       {MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801, // Move To Machine State Register Doubleword X-form (mtmsrd RS,L)
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
-       {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT)
-               [5]*argField{ap_Reg_6_10}},
-       {SLBIE, 0xfc0007fe, 0x7c000364, 0x3ff0001, // SLB Invalidate Entry X-form (slbie RB)
-               [5]*argField{ap_Reg_16_20}},
-       {SLBIA, 0xfc0007fe, 0x7c0003e4, 0x31ff801, // SLB Invalidate All X-form (slbia IH)
-               [5]*argField{ap_ImmUnsigned_8_10}},
-       {SLBMTE, 0xfc0007fe, 0x7c000324, 0x1f0001, // SLB Move To Entry X-form (slbmte RS,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {SLBMFEV, 0xfc0007fe, 0x7c0006a6, 0x1f0001, // SLB Move From Entry VSID X-form (slbmfev RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001, // SLB Move From Entry ESID X-form (slbmfee RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {SLBFEECC, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801, // Move To Segment Register X-form (mtsr SR,RS)
-               [5]*argField{ap_SpReg_12_15, ap_Reg_6_10}},
-       {MTSRIN, 0xfc0007fe, 0x7c0001e4, 0x1f0001, // Move To Segment Register Indirect X-form (mtsrin RS,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {MFSR, 0xfc0007fe, 0x7c0004a6, 0x10f801, // Move From Segment Register X-form (mfsr RT,SR)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_12_15}},
-       {MFSRIN, 0xfc0007fe, 0x7c000526, 0x1f0001, // Move From Segment Register Indirect X-form (mfsrin RT,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
-       {TLBIE, 0xfc0007fe, 0x7c000264, 0x1f0001, // TLB Invalidate Entry X-form (tlbie RB,RS)
-               [5]*argField{ap_Reg_16_20, ap_Reg_6_10}},
-       {TLBIEL, 0xfc0007fe, 0x7c000224, 0x3ff0001, // TLB Invalidate Entry Local X-form (tlbiel RB)
-               [5]*argField{ap_Reg_16_20}},
-       {TLBIA, 0xfc0007fe, 0x7c0002e4, 0x3fff801, // TLB Invalidate All X-form (tlbia)
-               [5]*argField{}},
-       {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync)
-               [5]*argField{}},
-       {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB)
-               [5]*argField{ap_Reg_16_20}},
-       {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB)
-               [5]*argField{ap_Reg_16_20}},
-       {MSGSNDP, 0xfc0007fe, 0x7c00011c, 0x3ff0001, // Message Send Privileged X-form (msgsndp RB)
-               [5]*argField{ap_Reg_16_20}},
-       {MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001, // Message Clear Privileged X-form (msgclrp RB)
-               [5]*argField{ap_Reg_16_20}},
-       {MTTMR, 0xfc0007fe, 0x7c0003dc, 0x1, // Move To Thread Management Register XFX-form (mttmr TMR,RS)
-               [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-       {SC, 0xfc000002, 0x44000002, 0x3fffffd, // System Call SC-form (sc)
-               [5]*argField{}},
-       {RFI, 0xfc0007fe, 0x4c000064, 0x3fff801, // Return From Interrupt XL-form (rfi)
-               [5]*argField{}},
-       {RFCI, 0xfc0007fe, 0x4c000066, 0x3fff801, // Return From Critical Interrupt XL-form (rfci)
-               [5]*argField{}},
-       {RFDI, 0xfc0007fe, 0x4c00004e, 0x3fff801, // Return From Debug Interrupt X-form (rfdi)
-               [5]*argField{}},
-       {RFMCI, 0xfc0007fe, 0x4c00004c, 0x3fff801, // Return From Machine Check Interrupt XL-form (rfmci)
-               [5]*argField{}},
-       {RFGI, 0xfc0007fe, 0x4c0000cc, 0x3fff801, // Return From Guest Interrupt XL-form (rfgi)
-               [5]*argField{}},
-       {EHPRIV, 0xfc0007fe, 0x7c00021c, 0x1, // Embedded Hypervisor Privilege XL-form (ehpriv OC)
-               [5]*argField{ap_ImmUnsigned_6_20}},
-       {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
-               [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-       {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
-       {MTDCR, 0xfc0007fe, 0x7c000386, 0x1, // Move To Device Control Register XFX-form (mtdcr DCRN,RS)
-               [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-       {MTDCRX, 0xfc0007fe, 0x7c000306, 0xf801, // Move To Device Control Register Indexed X-form (mtdcrx RA,RS)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
-       {MFDCR, 0xfc0007fe, 0x7c000286, 0x1, // Move From Device Control Register XFX-form (mfdcr RT,DCRN)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
-       {MFDCRX, 0xfc0007fe, 0x7c000206, 0xf801, // Move From Device Control Register Indexed X-form (mfdcrx RT,RA)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
-       {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ff801, // Move To Machine State Register X-form (mtmsr RS)
-               [5]*argField{ap_Reg_6_10}},
-       {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT)
-               [5]*argField{ap_Reg_6_10}},
-       {WRTEE, 0xfc0007fe, 0x7c000106, 0x1ff801, // Write MSR External Enable X-form (wrtee RS)
-               [5]*argField{ap_Reg_6_10}},
-       {WRTEEI, 0xfc0007fe, 0x7c000146, 0x3ff7801, // Write MSR External Enable Immediate X-form (wrteei E)
-               [5]*argField{ap_ImmUnsigned_16_16}},
-       {LBEPX, 0xfc0007fe, 0x7c0000be, 0x1, // Load Byte by External Process ID Indexed X-form (lbepx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LHEPX, 0xfc0007fe, 0x7c00023e, 0x1, // Load Halfword by External Process ID Indexed X-form (lhepx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LWEPX, 0xfc0007fe, 0x7c00003e, 0x1, // Load Word by External Process ID Indexed X-form (lwepx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LDEPX, 0xfc0007fe, 0x7c00003a, 0x1, // Load Doubleword by External Process ID Indexed X-form (ldepx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STBEPX, 0xfc0007fe, 0x7c0001be, 0x1, // Store Byte by External Process ID Indexed X-form (stbepx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STHEPX, 0xfc0007fe, 0x7c00033e, 0x1, // Store Halfword by External Process ID Indexed X-form (sthepx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STWEPX, 0xfc0007fe, 0x7c00013e, 0x1, // Store Word by External Process ID Indexed X-form (stwepx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STDEPX, 0xfc0007fe, 0x7c00013a, 0x1, // Store Doubleword by External Process ID Indexed X-form (stdepx RS,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBSTEP, 0xfc0007fe, 0x7c00007e, 0x3e00001, // Data Cache Block Store by External PID X-form (dcbstep RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBTEP, 0xfc0007fe, 0x7c00027e, 0x1, // Data Cache Block Touch by External PID X-form (dcbtep TH,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBFEP, 0xfc0007fe, 0x7c0000fe, 0x3800001, // Data Cache Block Flush by External PID X-form (dcbfep RA,RB,L)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}},
-       {DCBTSTEP, 0xfc0007fe, 0x7c0001fe, 0x1, // Data Cache Block Touch for Store by External PID X-form (dcbtstep TH,RA,RB)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBIEP, 0xfc0007fe, 0x7c0007be, 0x3e00001, // Instruction Cache Block Invalidate by External PID X-form (icbiep RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBZEP, 0xfc0007fe, 0x7c0007fe, 0x3e00001, // Data Cache Block set to Zero by External PID X-form (dcbzep RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {LFDEPX, 0xfc0007fe, 0x7c0004be, 0x1, // Load Floating-Point Double by External Process ID Indexed X-form (lfdepx FRT,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STFDEPX, 0xfc0007fe, 0x7c0005be, 0x1, // Store Floating-Point Double by External Process ID Indexed X-form (stfdepx FRS,RA,RB)
-               [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVLDDEPX, 0xfc0007fe, 0x7c00063e, 0x1, // Vector Load Doubleword into Doubleword by External Process ID Indexed EVX-form (evlddepx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {EVSTDDEPX, 0xfc0007fe, 0x7c00073e, 0x1, // Vector Store Doubleword into Doubleword by External Process ID Indexed EVX-form (evstddepx RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVEPX, 0xfc0007fe, 0x7c00024e, 0x1, // Load Vector by External Process ID Indexed X-form (lvepx VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {LVEPXL, 0xfc0007fe, 0x7c00020e, 0x1, // Load Vector by External Process ID Indexed LRU X-form (lvepxl VRT,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVEPX, 0xfc0007fe, 0x7c00064e, 0x1, // Store Vector by External Process ID Indexed X-form (stvepx VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {STVEPXL, 0xfc0007fe, 0x7c00060e, 0x1, // Store Vector by External Process ID Indexed LRU X-form (stvepxl VRS,RA,RB)
-               [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001, // Data Cache Block Invalidate X-form (dcbi RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBLQCC, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBLQCC, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001, // Data Cache Block Touch and Lock Set X-form (dcbtls CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBTSTLS, 0xfc0007fe, 0x7c00010c, 0x2000001, // Data Cache Block Touch for Store and Lock Set X-form (dcbtstls CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBTLS, 0xfc0007fe, 0x7c0003cc, 0x2000001, // Instruction Cache Block Touch and Lock Set X-form (icbtls CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICBLC, 0xfc0007fe, 0x7c0001cc, 0x2000001, // Instruction Cache Block Lock Clear X-form (icblc CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {DCBLC, 0xfc0007fe, 0x7c00030c, 0x2000001, // Data Cache Block Lock Clear X-form (dcblc CT,RA,RB)
-               [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {TLBIVAX, 0xfc0007fe, 0x7c000624, 0x3e00001, // TLB Invalidate Virtual Address Indexed X-form (tlbivax RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {TLBILX, 0xfc0007fe, 0x7c000024, 0x3800001, // TLB Invalidate Local Indexed X-form (tlbilx RA,RB])
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001, // TLB Search Indexed X-form (tlbsx RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {TLBSRXCC, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801, // TLB Read Entry X-form (tlbre)
-               [5]*argField{}},
-       {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync)
-               [5]*argField{}},
-       {TLBWE, 0xfc0007fe, 0x7c0007a4, 0x3fff801, // TLB Write Entry X-form (tlbwe)
-               [5]*argField{}},
-       {DNH, 0xfc0007fe, 0x4c00018c, 0x1, // Debugger Notify Halt XFX-form (dnh DUI,DUIS)
-               [5]*argField{ap_ImmUnsigned_6_10, ap_ImmUnsigned_11_20}},
-       {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB)
-               [5]*argField{ap_Reg_16_20}},
-       {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB)
-               [5]*argField{ap_Reg_16_20}},
-       {DCI, 0xfc0007fe, 0x7c00038c, 0x21ff801, // Data Cache Invalidate X-form (dci CT)
-               [5]*argField{ap_ImmUnsigned_7_10}},
-       {ICI, 0xfc0007fe, 0x7c00078c, 0x21ff801, // Instruction Cache Invalidate X-form (ici CT)
-               [5]*argField{ap_ImmUnsigned_7_10}},
-       {DCREAD, 0xfc0007fe, 0x7c0003cc, 0x1, // Data Cache Read X-form (dcread RT,RA,RB)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {ICREAD, 0xfc0007fe, 0x7c0007cc, 0x3e00001, // Instruction Cache Read X-form (icread RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {MFPMR, 0xfc0007fe, 0x7c00029c, 0x1, // Move From Performance Monitor Register XFX-form (mfpmr RT,PMRN)
-               [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
-       {MTPMR, 0xfc0007fe, 0x7c00039c, 0x1, // Move To Performance Monitor Register XFX-form (mtpmr PMRN,RS)
-               [5]*argField{ap_SpReg_11_20, ap_Reg_6_10}},
-       {ADDEX, 0xfc0001fe, 0x7c000154, 0x1, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}},
-       {DARN, 0xfc0007fe, 0x7c0005e6, 0x1cf801, // Deliver A Random Number X-form (darn RT,L)
-               [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}},
-       {MADDHD, 0xfc00003f, 0x10000030, 0x0, // Multiply-Add High Doubleword VA-form (maddhd RT,RA,RB,RC)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
-       {MADDHDU, 0xfc00003f, 0x10000031, 0x0, // Multiply-Add High Doubleword Unsigned VA-form (maddhdu RT,RA,RB,RC)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
-       {MADDLD, 0xfc00003f, 0x10000033, 0x0, // Multiply-Add Low Doubleword VA-form (maddld RT,RA,RB,RC)
-               [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
-       {CMPRB, 0xfc0007fe, 0x7c000180, 0x400001, // Compare Ranged Byte X-form (cmprb BF,L,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {CMPEQB, 0xfc0007fe, 0x7c0001c0, 0x600001, // Compare Equal Byte X-form (cmpeqb BF,RA,RB)
-               [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-       {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB])
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
-       {EXTSWSLI, 0xfc0007fd, 0x7c0006f4, 0x0, // Extend-Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
-       {EXTSWSLICC, 0xfc0007fd, 0x7c0006f5, 0x0, // Extend-Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH)
-               [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
-       {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
-               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-       {MFVSRLD, 0xfc0007fe, 0x7c000266, 0xf800, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS)
-               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-       {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
-               [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-       {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword X-form (mtvsrd XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MTVSRDD, 0xfc0007fe, 0x7c000366, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-       {MTVSRWS, 0xfc0007fe, 0x7c000326, 0xf800, // Move To VSR Word & Splat X-form (mtvsrws XT,RA)
-               [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-       {MCRXRX, 0xfc0007fe, 0x7c000480, 0x7ff801, // Move to CR from XER Extended X-form (mcrxrx BF)
-               [5]*argField{ap_CondRegField_6_8}},
-       {COPY, 0xfc2007fe, 0x7c20060c, 0x3c00001, // Copy X-form (copy RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
-       {PASTECC, 0xfc2007ff, 0x7c20070d, 0x3c00000, // Paste X-form (paste. RA,RB)
-               [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+       {BRD, 0xfc0007fe00000000, 0x7c00017600000000, 0xf80100000000, // Byte-Reverse Doubleword X-form (brd RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {BRH, 0xfc0007fe00000000, 0x7c0001b600000000, 0xf80100000000, // Byte-Reverse Halfword X-form (brh RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {BRW, 0xfc0007fe00000000, 0x7c00013600000000, 0xf80100000000, // Byte-Reverse Word X-form (brw RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CFUGED, 0xfc0007fe00000000, 0x7c0001b800000000, 0x100000000, // Centrifuge Doubleword X-form (cfuged RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {CNTLZDM, 0xfc0007fe00000000, 0x7c00007600000000, 0x100000000, // Count Leading Zeros Doubleword under bit Mask X-form (cntlzdm RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {CNTTZDM, 0xfc0007fe00000000, 0x7c00047600000000, 0x100000000, // Count Trailing Zeros Doubleword under bit Mask X-form (cnttzdm RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {DCFFIXQQ, 0xfc1f07fe00000000, 0xfc0007c400000000, 0x100000000, // DFP Convert From Fixed Quadword Quad X-form (dcffixqq FRTp,VRB)
+               [6]*argField{ap_FPReg_6_10, ap_VecReg_16_20}},
+       {DCTFIXQQ, 0xfc1f07fe00000000, 0xfc0107c400000000, 0x100000000, // DFP Convert To Fixed Quadword Quad X-form (dctfixqq VRT,FRBp)
+               [6]*argField{ap_VecReg_6_10, ap_FPReg_16_20}},
+       {LXVKQ, 0xfc1f07fe00000000, 0xf01f02d000000000, 0x0, // Load VSX Vector Special Value Quadword X-form (lxvkq XT,UIM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_ImmUnsigned_16_20}},
+       {LXVP, 0xfc00000f00000000, 0x1800000000000000, 0x0, // Load VSX Vector Paired DQ-form (lxvp XTp,DQ(RA))
+               [6]*argField{ap_VecSpReg_10_10_6_9, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+       {LXVPX, 0xfc0007fe00000000, 0x7c00029a00000000, 0x100000000, // Load VSX Vector Paired Indexed X-form (lxvpx XTp,RA,RB)
+               [6]*argField{ap_VecSpReg_10_10_6_9, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVRBX, 0xfc0007fe00000000, 0x7c00001a00000000, 0x0, // Load VSX Vector Rightmost Byte Indexed X-form (lxvrbx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVRDX, 0xfc0007fe00000000, 0x7c0000da00000000, 0x0, // Load VSX Vector Rightmost Doubleword Indexed X-form (lxvrdx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVRHX, 0xfc0007fe00000000, 0x7c00005a00000000, 0x0, // Load VSX Vector Rightmost Halfword Indexed X-form (lxvrhx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVRWX, 0xfc0007fe00000000, 0x7c00009a00000000, 0x0, // Load VSX Vector Rightmost Word Indexed X-form (lxvrwx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MTVSRBM, 0xfc1f07ff00000000, 0x1010064200000000, 0x0, // Move to VSR Byte Mask VX-form (mtvsrbm VRT,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
+       {MTVSRBMI, 0xfc00003e00000000, 0x1000001400000000, 0x0, // Move To VSR Byte Mask Immediate DX-form (mtvsrbmi VRT,bm)
+               [6]*argField{ap_VecReg_6_10, ap_ImmUnsigned_16_25_11_15_31_31}},
+       {MTVSRDM, 0xfc1f07ff00000000, 0x1013064200000000, 0x0, // Move to VSR Doubleword Mask VX-form (mtvsrdm VRT,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
+       {MTVSRHM, 0xfc1f07ff00000000, 0x1011064200000000, 0x0, // Move to VSR Halfword Mask VX-form (mtvsrhm VRT,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
+       {MTVSRQM, 0xfc1f07ff00000000, 0x1014064200000000, 0x0, // Move to VSR Quadword Mask VX-form (mtvsrqm VRT,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
+       {MTVSRWM, 0xfc1f07ff00000000, 0x1012064200000000, 0x0, // Move to VSR Word Mask VX-form (mtvsrwm VRT,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
+       {PADDI, 0xff800000fc000000, 0x600000038000000, 0x6c000000000000, // Prefixed Add Immediate MLS:D-form (paddi RT,RA,SI,R)
+               [6]*argField{ap_Reg_38_42, ap_Reg_43_47, ap_ImmSigned_14_31_48_63, ap_ImmUnsigned_11_11}},
+       {PDEPD, 0xfc0007fe00000000, 0x7c00013800000000, 0x100000000, // Parallel Bits Deposit Doubleword X-form (pdepd RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {PEXTD, 0xfc0007fe00000000, 0x7c00017800000000, 0x100000000, // Parallel Bits Extract Doubleword X-form (pextd RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {PLBZ, 0xff800000fc000000, 0x600000088000000, 0x6c000000000000, // Prefixed Load Byte and Zero MLS:D-form (plbz RT,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLD, 0xff800000fc000000, 0x4000000e4000000, 0x6c000000000000, // Prefixed Load Doubleword 8LS:D-form (pld RT,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLFD, 0xff800000fc000000, 0x6000000c8000000, 0x6c000000000000, // Prefixed Load Floating-Point Double MLS:D-form (plfd FRT,D(RA),R)
+               [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLFS, 0xff800000fc000000, 0x6000000c0000000, 0x6c000000000000, // Prefixed Load Floating-Point Single MLS:D-form (plfs FRT,D(RA),R)
+               [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLHA, 0xff800000fc000000, 0x6000000a8000000, 0x6c000000000000, // Prefixed Load Halfword Algebraic MLS:D-form (plha RT,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLHZ, 0xff800000fc000000, 0x6000000a0000000, 0x6c000000000000, // Prefixed Load Halfword and Zero MLS:D-form (plhz RT,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLQ, 0xff800000fc000000, 0x4000000e0000000, 0x6c000000000000, // Prefixed Load Quadword 8LS:D-form (plq RTp,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLWA, 0xff800000fc000000, 0x4000000a4000000, 0x6c000000000000, // Prefixed Load Word Algebraic 8LS:D-form (plwa RT,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLWZ, 0xff800000fc000000, 0x600000080000000, 0x6c000000000000, // Prefixed Load Word and Zero MLS:D-form (plwz RT,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLXSD, 0xff800000fc000000, 0x4000000a8000000, 0x6c000000000000, // Prefixed Load VSX Scalar Doubleword 8LS:D-form (plxsd VRT,D(RA),R)
+               [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLXSSP, 0xff800000fc000000, 0x4000000ac000000, 0x6c000000000000, // Prefixed Load VSX Scalar Single-Precision 8LS:D-form (plxssp VRT,D(RA),R)
+               [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLXV, 0xff800000f8000000, 0x4000000c8000000, 0x6c000000000000, // Prefixed Load VSX Vector 8LS:D-form (plxv XT,D(RA),R)
+               [6]*argField{ap_VecSReg_37_37_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PLXVP, 0xff800000fc000000, 0x4000000e8000000, 0x6c000000000000, // Prefixed Load VSX Vector Paired 8LS:D-form (plxvp XTp,D(RA),R)
+               [6]*argField{ap_VecSpReg_42_42_38_41, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PMXVBF16GER2, 0xfff00000fc0007f8, 0x7900000ec000198, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) MMIRR:XX3-form (pmxvbf16ger2 AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVBF16GER2NN, 0xfff00000fc0007f8, 0x7900000ec000790, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvbf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVBF16GER2NP, 0xfff00000fc0007f8, 0x7900000ec000390, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVBF16GER2PN, 0xfff00000fc0007f8, 0x7900000ec000590, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvbf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVBF16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000190, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvbf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVF16GER2, 0xfff00000fc0007f8, 0x7900000ec000098, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) MMIRR:XX3-form (pmxvf16ger2 AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVF16GER2NN, 0xfff00000fc0007f8, 0x7900000ec000690, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVF16GER2NP, 0xfff00000fc0007f8, 0x7900000ec000290, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVF16GER2PN, 0xfff00000fc0007f8, 0x7900000ec000490, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVF16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000090, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVF32GER, 0xfff00000fc0007f8, 0x7900000ec0000d8, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form (pmxvf32ger AT,XA,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
+       {PMXVF32GERNN, 0xfff00000fc0007f8, 0x7900000ec0006d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf32gernn AT,XA,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
+       {PMXVF32GERNP, 0xfff00000fc0007f8, 0x7900000ec0002d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf32gernp AT,XA,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
+       {PMXVF32GERPN, 0xfff00000fc0007f8, 0x7900000ec0004d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf32gerpn AT,XA,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
+       {PMXVF32GERPP, 0xfff00000fc0007f8, 0x7900000ec0000d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf32gerpp AT,XA,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
+       {PMXVF64GER, 0xfff00000fc0007f8, 0x7900000ec0001d8, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form (pmxvf64ger AT,XAp,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
+       {PMXVF64GERNN, 0xfff00000fc0007f8, 0x7900000ec0007d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf64gernn AT,XAp,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
+       {PMXVF64GERNP, 0xfff00000fc0007f8, 0x7900000ec0003d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf64gernp AT,XAp,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
+       {PMXVF64GERPN, 0xfff00000fc0007f8, 0x7900000ec0005d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf64gerpn AT,XAp,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
+       {PMXVF64GERPP, 0xfff00000fc0007f8, 0x7900000ec0001d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf64gerpp AT,XAp,XB,XMSK,YMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
+       {PMXVI16GER2, 0xfff00000fc0007f8, 0x7900000ec000258, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) MMIRR:XX3-form (pmxvi16ger2 AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVI16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000358, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi16ger2pp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVI16GER2S, 0xfff00000fc0007f8, 0x7900000ec000158, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation MMIRR:XX3-form (pmxvi16ger2s AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVI16GER2SPP, 0xfff00000fc0007f8, 0x7900000ec000150, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi16ger2spp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
+       {PMXVI4GER8, 0xfff00000fc0007f8, 0x7900000ec000118, 0xf000000000000, // Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) MMIRR:XX3-form (pmxvi4ger8 AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_23}},
+       {PMXVI4GER8PP, 0xfff00000fc0007f8, 0x7900000ec000110, 0xf000000000000, // Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi4ger8pp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_23}},
+       {PMXVI8GER4, 0xfff00000fc0007f8, 0x7900000ec000018, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) MMIRR:XX3-form (pmxvi8ger4 AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}},
+       {PMXVI8GER4PP, 0xfff00000fc0007f8, 0x7900000ec000010, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}},
+       {PMXVI8GER4SPP, 0xfff00000fc0007f8, 0x7900000ec000318, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi8ger4spp AT,XA,XB,XMSK,YMSK,PMSK)
+               [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}},
+       {PNOP, 0xfff3fffe00000000, 0x700000000000000, 0xc000100000000, // Prefixed Nop MRR:*-form (pnop)
+               [6]*argField{}},
+       {PSTB, 0xff800000fc000000, 0x600000098000000, 0x6c000000000000, // Prefixed Store Byte MLS:D-form (pstb RS,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTD, 0xff800000fc000000, 0x4000000f4000000, 0x6c000000000000, // Prefixed Store Doubleword 8LS:D-form (pstd RS,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTFD, 0xff800000fc000000, 0x6000000d8000000, 0x6c000000000000, // Prefixed Store Floating-Point Double MLS:D-form (pstfd FRS,D(RA),R)
+               [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTFS, 0xff800000fc000000, 0x6000000d0000000, 0x6c000000000000, // Prefixed Store Floating-Point Single MLS:D-form (pstfs FRS,D(RA),R)
+               [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTH, 0xff800000fc000000, 0x6000000b0000000, 0x6c000000000000, // Prefixed Store Halfword MLS:D-form (psth RS,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTQ, 0xff800000fc000000, 0x4000000f0000000, 0x6c000000000000, // Prefixed Store Quadword 8LS:D-form (pstq RSp,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTW, 0xff800000fc000000, 0x600000090000000, 0x6c000000000000, // Prefixed Store Word MLS:D-form (pstw RS,D(RA),R)
+               [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTXSD, 0xff800000fc000000, 0x4000000b8000000, 0x6c000000000000, // Prefixed Store VSX Scalar Doubleword 8LS:D-form (pstxsd VRS,D(RA),R)
+               [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTXSSP, 0xff800000fc000000, 0x4000000bc000000, 0x6c000000000000, // Prefixed Store VSX Scalar Single-Precision 8LS:D-form (pstxssp VRS,D(RA),R)
+               [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTXV, 0xff800000f8000000, 0x4000000d8000000, 0x6c000000000000, // Prefixed Store VSX Vector 8LS:D-form (pstxv XS,D(RA),R)
+               [6]*argField{ap_VecSReg_37_37_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {PSTXVP, 0xff800000fc000000, 0x4000000f8000000, 0x6c000000000000, // Prefixed Store VSX Vector Paired 8LS:D-form (pstxvp XSp,D(RA),R)
+               [6]*argField{ap_VecSpReg_42_42_38_41, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
+       {SETBC, 0xfc0007fe00000000, 0x7c00030000000000, 0xf80100000000, // Set Boolean Condition X-form (setbc RT,BI)
+               [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
+       {SETBCR, 0xfc0007fe00000000, 0x7c00034000000000, 0xf80100000000, // Set Boolean Condition Reverse X-form (setbcr RT,BI)
+               [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
+       {SETNBC, 0xfc0007fe00000000, 0x7c00038000000000, 0xf80100000000, // Set Negative Boolean Condition X-form (setnbc RT,BI)
+               [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
+       {SETNBCR, 0xfc0007fe00000000, 0x7c0003c000000000, 0xf80100000000, // Set Negative Boolean Condition Reverse X-form (setnbcr RT,BI)
+               [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
+       {STXVP, 0xfc00000f00000000, 0x1800000100000000, 0x0, // Store VSX Vector Paired DQ-form (stxvp XSp,DQ(RA))
+               [6]*argField{ap_VecSpReg_10_10_6_9, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+       {STXVPX, 0xfc0007fe00000000, 0x7c00039a00000000, 0x100000000, // Store VSX Vector Paired Indexed X-form (stxvpx XSp,RA,RB)
+               [6]*argField{ap_VecSpReg_10_10_6_9, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVRBX, 0xfc0007fe00000000, 0x7c00011a00000000, 0x0, // Store VSX Vector Rightmost Byte Indexed X-form (stxvrbx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVRDX, 0xfc0007fe00000000, 0x7c0001da00000000, 0x0, // Store VSX Vector Rightmost Doubleword Indexed X-form (stxvrdx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVRHX, 0xfc0007fe00000000, 0x7c00015a00000000, 0x0, // Store VSX Vector Rightmost Halfword Indexed X-form (stxvrhx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVRWX, 0xfc0007fe00000000, 0x7c00019a00000000, 0x0, // Store VSX Vector Rightmost Word Indexed X-form (stxvrwx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VCFUGED, 0xfc0007ff00000000, 0x1000054d00000000, 0x0, // Vector Centrifuge Doubleword VX-form (vcfuged VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCLRLB, 0xfc0007ff00000000, 0x1000018d00000000, 0x0, // Vector Clear Leftmost Bytes VX-form (vclrlb VRT,VRA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_Reg_16_20}},
+       {VCLRRB, 0xfc0007ff00000000, 0x100001cd00000000, 0x0, // Vector Clear Rightmost Bytes VX-form (vclrrb VRT,VRA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_Reg_16_20}},
+       {VCLZDM, 0xfc0007ff00000000, 0x1000078400000000, 0x0, // Vector Count Leading Zeros Doubleword under bit Mask VX-form (vclzdm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUQ, 0xfc0007ff00000000, 0x100001c700000000, 0x0, // Vector Compare Equal Quadword VC-form (vcmpequq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUQCC, 0xfc0007ff00000000, 0x100005c700000000, 0x0, // Vector Compare Equal Quadword VC-form (vcmpequq. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSQ, 0xfc0007ff00000000, 0x1000038700000000, 0x0, // Vector Compare Greater Than Signed Quadword VC-form (vcmpgtsq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSQCC, 0xfc0007ff00000000, 0x1000078700000000, 0x0, // Vector Compare Greater Than Signed Quadword VC-form (vcmpgtsq. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUQ, 0xfc0007ff00000000, 0x1000028700000000, 0x0, // Vector Compare Greater Than Unsigned Quadword VC-form (vcmpgtuq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUQCC, 0xfc0007ff00000000, 0x1000068700000000, 0x0, // Vector Compare Greater Than Unsigned Quadword VC-form (vcmpgtuq. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPSQ, 0xfc0007ff00000000, 0x1000014100000000, 0x60000000000000, // Vector Compare Signed Quadword VX-form (vcmpsq BF,VRA,VRB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPUQ, 0xfc0007ff00000000, 0x1000010100000000, 0x60000000000000, // Vector Compare Unsigned Quadword VX-form (vcmpuq BF,VRA,VRB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCNTMBB, 0xfc1e07ff00000000, 0x1018064200000000, 0x0, // Vector Count Mask Bits Byte VX-form (vcntmbb RT,VRB,MP)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
+       {VCNTMBD, 0xfc1e07ff00000000, 0x101e064200000000, 0x0, // Vector Count Mask Bits Doubleword VX-form (vcntmbd RT,VRB,MP)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
+       {VCNTMBH, 0xfc1e07ff00000000, 0x101a064200000000, 0x0, // Vector Count Mask Bits Halfword VX-form (vcntmbh RT,VRB,MP)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
+       {VCNTMBW, 0xfc1e07ff00000000, 0x101c064200000000, 0x0, // Vector Count Mask Bits Word VX-form (vcntmbw RT,VRB,MP)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
+       {VCTZDM, 0xfc0007ff00000000, 0x100007c400000000, 0x0, // Vector Count Trailing Zeros Doubleword under bit Mask VX-form (vctzdm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVESD, 0xfc0007ff00000000, 0x100003cb00000000, 0x0, // Vector Divide Extended Signed Doubleword VX-form (vdivesd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVESQ, 0xfc0007ff00000000, 0x1000030b00000000, 0x0, // Vector Divide Extended Signed Quadword VX-form (vdivesq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVESW, 0xfc0007ff00000000, 0x1000038b00000000, 0x0, // Vector Divide Extended Signed Word VX-form (vdivesw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVEUD, 0xfc0007ff00000000, 0x100002cb00000000, 0x0, // Vector Divide Extended Unsigned Doubleword VX-form (vdiveud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVEUQ, 0xfc0007ff00000000, 0x1000020b00000000, 0x0, // Vector Divide Extended Unsigned Quadword VX-form (vdiveuq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVEUW, 0xfc0007ff00000000, 0x1000028b00000000, 0x0, // Vector Divide Extended Unsigned Word VX-form (vdiveuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVSD, 0xfc0007ff00000000, 0x100001cb00000000, 0x0, // Vector Divide Signed Doubleword VX-form (vdivsd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVSQ, 0xfc0007ff00000000, 0x1000010b00000000, 0x0, // Vector Divide Signed Quadword VX-form (vdivsq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVSW, 0xfc0007ff00000000, 0x1000018b00000000, 0x0, // Vector Divide Signed Word VX-form (vdivsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVUD, 0xfc0007ff00000000, 0x100000cb00000000, 0x0, // Vector Divide Unsigned Doubleword VX-form (vdivud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVUQ, 0xfc0007ff00000000, 0x1000000b00000000, 0x0, // Vector Divide Unsigned Quadword VX-form (vdivuq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VDIVUW, 0xfc0007ff00000000, 0x1000008b00000000, 0x0, // Vector Divide Unsigned Word VX-form (vdivuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VEXPANDBM, 0xfc1f07ff00000000, 0x1000064200000000, 0x0, // Vector Expand Byte Mask VX-form (vexpandbm VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXPANDDM, 0xfc1f07ff00000000, 0x1003064200000000, 0x0, // Vector Expand Doubleword Mask VX-form (vexpanddm VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXPANDHM, 0xfc1f07ff00000000, 0x1001064200000000, 0x0, // Vector Expand Halfword Mask VX-form (vexpandhm VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXPANDQM, 0xfc1f07ff00000000, 0x1004064200000000, 0x0, // Vector Expand Quadword Mask VX-form (vexpandqm VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXPANDWM, 0xfc1f07ff00000000, 0x1002064200000000, 0x0, // Vector Expand Word Mask VX-form (vexpandwm VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTDDVLX, 0xfc00003f00000000, 0x1000001e00000000, 0x0, // Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form (vextddvlx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDDVRX, 0xfc00003f00000000, 0x1000001f00000000, 0x0, // Vector Extract Double Doubleword to VSR using GPR-specified Right-Index VA-form (vextddvrx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDUBVLX, 0xfc00003f00000000, 0x1000001800000000, 0x0, // Vector Extract Double Unsigned Byte to VSR using GPR-specified Left-Index VA-form (vextdubvlx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDUBVRX, 0xfc00003f00000000, 0x1000001900000000, 0x0, // Vector Extract Double Unsigned Byte to VSR using GPR-specified Right-Index VA-form (vextdubvrx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDUHVLX, 0xfc00003f00000000, 0x1000001a00000000, 0x0, // Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form (vextduhvlx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDUHVRX, 0xfc00003f00000000, 0x1000001b00000000, 0x0, // Vector Extract Double Unsigned Halfword to VSR using GPR-specified Right-Index VA-form (vextduhvrx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDUWVLX, 0xfc00003f00000000, 0x1000001c00000000, 0x0, // Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form (vextduwvlx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTDUWVRX, 0xfc00003f00000000, 0x1000001d00000000, 0x0, // Vector Extract Double Unsigned Word to VSR using GPR-specified Right-Index VA-form (vextduwvrx VRT,VRA,VRB,RC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
+       {VEXTRACTBM, 0xfc1f07ff00000000, 0x1008064200000000, 0x0, // Vector Extract Byte Mask VX-form (vextractbm RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VEXTRACTDM, 0xfc1f07ff00000000, 0x100b064200000000, 0x0, // Vector Extract Doubleword Mask VX-form (vextractdm RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VEXTRACTHM, 0xfc1f07ff00000000, 0x1009064200000000, 0x0, // Vector Extract Halfword Mask VX-form (vextracthm RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VEXTRACTQM, 0xfc1f07ff00000000, 0x100c064200000000, 0x0, // Vector Extract Quadword Mask VX-form (vextractqm RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VEXTRACTWM, 0xfc1f07ff00000000, 0x100a064200000000, 0x0, // Vector Extract Word Mask VX-form (vextractwm RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VEXTSD2Q, 0xfc1f07ff00000000, 0x101b060200000000, 0x0, // Vector Extend Sign Doubleword to Quadword VX-form (vextsd2q VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VGNB, 0xfc0007ff00000000, 0x100004cc00000000, 0x18000000000000, // Vector Gather every Nth Bit VX-form (vgnb RT,VRB,N)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
+       {VINSBLX, 0xfc0007ff00000000, 0x1000020f00000000, 0x0, // Vector Insert Byte from GPR using GPR-specified Left-Index VX-form (vinsblx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSBRX, 0xfc0007ff00000000, 0x1000030f00000000, 0x0, // Vector Insert Byte from GPR using GPR-specified Right-Index VX-form (vinsbrx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSBVLX, 0xfc0007ff00000000, 0x1000000f00000000, 0x0, // Vector Insert Byte from VSR using GPR-specified Left-Index VX-form (vinsbvlx VRT,RA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VINSBVRX, 0xfc0007ff00000000, 0x1000010f00000000, 0x0, // Vector Insert Byte from VSR using GPR-specified Right-Index VX-form (vinsbvrx VRT,RA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VINSD, 0xfc0007ff00000000, 0x100001cf00000000, 0x10000000000000, // Vector Insert Doubleword from GPR using immediate-specified index VX-form (vinsd VRT,RB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20, ap_ImmUnsigned_12_15}},
+       {VINSDLX, 0xfc0007ff00000000, 0x100002cf00000000, 0x0, // Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-form (vinsdlx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSDRX, 0xfc0007ff00000000, 0x100003cf00000000, 0x0, // Vector Insert Doubleword from GPR using GPR-specified Right-Index VX-form (vinsdrx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSHLX, 0xfc0007ff00000000, 0x1000024f00000000, 0x0, // Vector Insert Halfword from GPR using GPR-specified Left-Index VX-form (vinshlx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSHRX, 0xfc0007ff00000000, 0x1000034f00000000, 0x0, // Vector Insert Halfword from GPR using GPR-specified Right-Index VX-form (vinshrx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSHVLX, 0xfc0007ff00000000, 0x1000004f00000000, 0x0, // Vector Insert Halfword from VSR using GPR-specified Left-Index VX-form (vinshvlx VRT,RA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VINSHVRX, 0xfc0007ff00000000, 0x1000014f00000000, 0x0, // Vector Insert Halfword from VSR using GPR-specified Right-Index VX-form (vinshvrx VRT,RA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VINSW, 0xfc0007ff00000000, 0x100000cf00000000, 0x10000000000000, // Vector Insert Word from GPR using immediate-specified index VX-form (vinsw VRT,RB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_16_20, ap_ImmUnsigned_12_15}},
+       {VINSWLX, 0xfc0007ff00000000, 0x1000028f00000000, 0x0, // Vector Insert Word from GPR using GPR-specified Left-Index VX-form (vinswlx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSWRX, 0xfc0007ff00000000, 0x1000038f00000000, 0x0, // Vector Insert Word from GPR using GPR-specified Right-Index VX-form (vinswrx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VINSWVLX, 0xfc0007ff00000000, 0x1000008f00000000, 0x0, // Vector Insert Word from VSR using GPR-specified Left-Index VX-form (vinswvlx VRT,RA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VINSWVRX, 0xfc0007ff00000000, 0x1000018f00000000, 0x0, // Vector Insert Word from VSR using GPR-specified Left-Index VX-form (vinswvrx VRT,RA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VMODSD, 0xfc0007ff00000000, 0x100007cb00000000, 0x0, // Vector Modulo Signed Doubleword VX-form (vmodsd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMODSQ, 0xfc0007ff00000000, 0x1000070b00000000, 0x0, // Vector Modulo Signed Quadword VX-form (vmodsq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMODSW, 0xfc0007ff00000000, 0x1000078b00000000, 0x0, // Vector Modulo Signed Word VX-form (vmodsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMODUD, 0xfc0007ff00000000, 0x100006cb00000000, 0x0, // Vector Modulo Unsigned Doubleword VX-form (vmodud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMODUQ, 0xfc0007ff00000000, 0x1000060b00000000, 0x0, // Vector Modulo Unsigned Quadword VX-form (vmoduq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMODUW, 0xfc0007ff00000000, 0x1000068b00000000, 0x0, // Vector Modulo Unsigned Word VX-form (vmoduw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMSUMCUD, 0xfc00003f00000000, 0x1000001700000000, 0x0, // Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form (vmsumcud VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMULESD, 0xfc0007ff00000000, 0x100003c800000000, 0x0, // Vector Multiply Even Signed Doubleword VX-form (vmulesd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULEUD, 0xfc0007ff00000000, 0x100002c800000000, 0x0, // Vector Multiply Even Unsigned Doubleword VX-form (vmuleud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULHSD, 0xfc0007ff00000000, 0x100003c900000000, 0x0, // Vector Multiply High Signed Doubleword VX-form (vmulhsd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULHSW, 0xfc0007ff00000000, 0x1000038900000000, 0x0, // Vector Multiply High Signed Word VX-form (vmulhsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULHUD, 0xfc0007ff00000000, 0x100002c900000000, 0x0, // Vector Multiply High Unsigned Doubleword VX-form (vmulhud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULHUW, 0xfc0007ff00000000, 0x1000028900000000, 0x0, // Vector Multiply High Unsigned Word VX-form (vmulhuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULLD, 0xfc0007ff00000000, 0x100001c900000000, 0x0, // Vector Multiply Low Doubleword VX-form (vmulld VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOSD, 0xfc0007ff00000000, 0x100001c800000000, 0x0, // Vector Multiply Odd Signed Doubleword VX-form (vmulosd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOUD, 0xfc0007ff00000000, 0x100000c800000000, 0x0, // Vector Multiply Odd Unsigned Doubleword VX-form (vmuloud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPDEPD, 0xfc0007ff00000000, 0x100005cd00000000, 0x0, // Vector Parallel Bits Deposit Doubleword VX-form (vpdepd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPEXTD, 0xfc0007ff00000000, 0x1000058d00000000, 0x0, // Vector Parallel Bits Extract Doubleword VX-form (vpextd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLQ, 0xfc0007ff00000000, 0x1000000500000000, 0x0, // Vector Rotate Left Quadword VX-form (vrlq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLQMI, 0xfc0007ff00000000, 0x1000004500000000, 0x0, // Vector Rotate Left Quadword then Mask Insert VX-form (vrlqmi VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLQNM, 0xfc0007ff00000000, 0x1000014500000000, 0x0, // Vector Rotate Left Quadword then AND with Mask VX-form (vrlqnm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSLDBI, 0xfc00063f00000000, 0x1000001600000000, 0x0, // Vector Shift Left Double by Bit Immediate VN-form (vsldbi VRT,VRA,VRB,SH)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_23_25}},
+       {VSLQ, 0xfc0007ff00000000, 0x1000010500000000, 0x0, // Vector Shift Left Quadword VX-form (vslq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRAQ, 0xfc0007ff00000000, 0x1000030500000000, 0x0, // Vector Shift Right Algebraic Quadword VX-form (vsraq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRDBI, 0xfc00063f00000000, 0x1000021600000000, 0x0, // Vector Shift Right Double by Bit Immediate VN-form (vsrdbi VRT,VRA,VRB,SH)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_23_25}},
+       {VSRQ, 0xfc0007ff00000000, 0x1000020500000000, 0x0, // Vector Shift Right Quadword VX-form (vsrq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSTRIBL, 0xfc1f07ff00000000, 0x1000000d00000000, 0x0, // Vector String Isolate Byte Left-justified VX-form (vstribl VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIBLCC, 0xfc1f07ff00000000, 0x1000040d00000000, 0x0, // Vector String Isolate Byte Left-justified VX-form (vstribl. VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIBR, 0xfc1f07ff00000000, 0x1001000d00000000, 0x0, // Vector String Isolate Byte Right-justified VX-form (vstribr VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIBRCC, 0xfc1f07ff00000000, 0x1001040d00000000, 0x0, // Vector String Isolate Byte Right-justified VX-form (vstribr. VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIHL, 0xfc1f07ff00000000, 0x1002000d00000000, 0x0, // Vector String Isolate Halfword Left-justified VX-form (vstrihl VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIHLCC, 0xfc1f07ff00000000, 0x1002040d00000000, 0x0, // Vector String Isolate Halfword Left-justified VX-form (vstrihl. VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIHR, 0xfc1f07ff00000000, 0x1003000d00000000, 0x0, // Vector String Isolate Halfword Right-justified VX-form (vstrihr VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSTRIHRCC, 0xfc1f07ff00000000, 0x1003040d00000000, 0x0, // Vector String Isolate Halfword Right-justified VX-form (vstrihr. VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCMPEQQP, 0xfc0007fe00000000, 0xfc00008800000000, 0x100000000, // VSX Scalar Compare Equal Quad-Precision X-form (xscmpeqqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCMPGEQP, 0xfc0007fe00000000, 0xfc00018800000000, 0x100000000, // VSX Scalar Compare Greater Than or Equal Quad-Precision X-form (xscmpgeqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCMPGTQP, 0xfc0007fe00000000, 0xfc0001c800000000, 0x100000000, // VSX Scalar Compare Greater Than Quad-Precision X-form (xscmpgtqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCVQPSQZ, 0xfc1f07fe00000000, 0xfc08068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword X-form (xscvqpsqz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVQPUQZ, 0xfc1f07fe00000000, 0xfc00068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword X-form (xscvqpuqz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVSQQP, 0xfc1f07fe00000000, 0xfc0b068800000000, 0x100000000, // VSX Scalar Convert with round Signed Quadword to Quad-Precision X-form (xscvsqqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVUQQP, 0xfc1f07fe00000000, 0xfc03068800000000, 0x100000000, // VSX Scalar Convert with round Unsigned Quadword to Quad-Precision X-form (xscvuqqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSMAXCQP, 0xfc0007fe00000000, 0xfc00054800000000, 0x100000000, // VSX Scalar Maximum Type-C Quad-Precision X-form (xsmaxcqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMINCQP, 0xfc0007fe00000000, 0xfc0005c800000000, 0x100000000, // VSX Scalar Minimum Type-C Quad-Precision X-form (xsmincqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XVBF16GER2, 0xfc0007f800000000, 0xec00019800000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) XX3-form (xvbf16ger2 AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVBF16GER2NN, 0xfc0007f800000000, 0xec00079000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate XX3-form (xvbf16ger2nn AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVBF16GER2NP, 0xfc0007f800000000, 0xec00039000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate XX3-form (xvbf16ger2np AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVBF16GER2PN, 0xfc0007f800000000, 0xec00059000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate XX3-form (xvbf16ger2pn AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVBF16GER2PP, 0xfc0007f800000000, 0xec00019000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate XX3-form (xvbf16ger2pp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCVBF16SPN, 0xfc1f07fc00000000, 0xf010076c00000000, 0x0, // VSX Vector Convert bfloat16 to Single-Precision format XX2-form (xvcvbf16spn XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPBF16, 0xfc1f07fc00000000, 0xf011076c00000000, 0x0, // VSX Vector Convert with round Single-Precision to bfloat16 format XX2-form (xvcvspbf16 XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVF16GER2, 0xfc0007f800000000, 0xec00009800000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) XX3-form (xvf16ger2 AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF16GER2NN, 0xfc0007f800000000, 0xec00069000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate XX3-form (xvf16ger2nn AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF16GER2NP, 0xfc0007f800000000, 0xec00029000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate XX3-form (xvf16ger2np AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF16GER2PN, 0xfc0007f800000000, 0xec00049000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate XX3-form (xvf16ger2pn AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF16GER2PP, 0xfc0007f800000000, 0xec00009000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate XX3-form (xvf16ger2pp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF32GER, 0xfc0007f800000000, 0xec0000d800000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) XX3-form (xvf32ger AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF32GERNN, 0xfc0007f800000000, 0xec0006d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form (xvf32gernn AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF32GERNP, 0xfc0007f800000000, 0xec0002d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form (xvf32gernp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF32GERPN, 0xfc0007f800000000, 0xec0004d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form (xvf32gerpn AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF32GERPP, 0xfc0007f800000000, 0xec0000d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form (xvf32gerpp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF64GER, 0xfc0007f800000000, 0xec0001d800000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) XX3-form (xvf64ger AT,XAp,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF64GERNN, 0xfc0007f800000000, 0xec0007d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form (xvf64gernn AT,XAp,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF64GERNP, 0xfc0007f800000000, 0xec0003d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form (xvf64gernp AT,XAp,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF64GERPN, 0xfc0007f800000000, 0xec0005d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form (xvf64gerpn AT,XAp,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVF64GERPP, 0xfc0007f800000000, 0xec0001d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form (xvf64gerpp AT,XAp,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI16GER2, 0xfc0007f800000000, 0xec00025800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) XX3-form (xvi16ger2 AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI16GER2PP, 0xfc0007f800000000, 0xec00035800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate XX3-form (xvi16ger2pp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI16GER2S, 0xfc0007f800000000, 0xec00015800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation XX3-form (xvi16ger2s AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI16GER2SPP, 0xfc0007f800000000, 0xec00015000000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate XX3-form (xvi16ger2spp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI4GER8, 0xfc0007f800000000, 0xec00011800000000, 0x60000100000000, // VSX Vector 4-bit Signed Integer GER (rank-8 update) XX3-form (xvi4ger8 AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI4GER8PP, 0xfc0007f800000000, 0xec00011000000000, 0x60000100000000, // VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate XX3-form (xvi4ger8pp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI8GER4, 0xfc0007f800000000, 0xec00001800000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) XX3-form (xvi8ger4 AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI8GER4PP, 0xfc0007f800000000, 0xec00001000000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate XX3-form (xvi8ger4pp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVI8GER4SPP, 0xfc0007f800000000, 0xec00031800000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate XX3-form (xvi8ger4spp AT,XA,XB)
+               [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVTLSBB, 0xfc1f07fc00000000, 0xf002076c00000000, 0x60000100000000, // VSX Vector Test Least-Significant Bit by Byte XX2-form (xvtlsbb BF,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
+       {XXBLENDVB, 0xfff00000fc000030, 0x500000084000000, 0xfffff00000000, // VSX Vector Blend Variable Byte 8RR:XX4-form (xxblendvb XT,XA,XB,XC)
+               [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
+       {XXBLENDVD, 0xfff00000fc000030, 0x500000084000030, 0xfffff00000000, // VSX Vector Blend Variable Doubleword 8RR:XX4-form (xxblendvd XT,XA,XB,XC)
+               [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
+       {XXBLENDVH, 0xfff00000fc000030, 0x500000084000010, 0xfffff00000000, // VSX Vector Blend Variable Halfword 8RR:XX4-form (xxblendvh XT,XA,XB,XC)
+               [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
+       {XXBLENDVW, 0xfff00000fc000030, 0x500000084000020, 0xfffff00000000, // VSX Vector Blend Variable Word 8RR:XX4-form (xxblendvw XT,XA,XB,XC)
+               [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
+       {XXEVAL, 0xfff00000fc000030, 0x500000088000010, 0xfff0000000000, // VSX Vector Evaluate 8RR-XX4-form (xxeval XT,XA,XB,XC,IMM)
+               [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57, ap_ImmUnsigned_24_31}},
+       {XXGENPCVBM, 0xfc0007fe00000000, 0xf000072800000000, 0x0, // VSX Vector Generate PCV from Byte Mask X-form (xxgenpcvbm XT,VRB,IMM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {XXGENPCVDM, 0xfc0007fe00000000, 0xf000076a00000000, 0x0, // VSX Vector Generate PCV from Doubleword Mask X-form (xxgenpcvdm XT,VRB,IMM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {XXGENPCVHM, 0xfc0007fe00000000, 0xf000072a00000000, 0x0, // VSX Vector Generate PCV from Halfword Mask X-form (xxgenpcvhm XT,VRB,IMM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {XXGENPCVWM, 0xfc0007fe00000000, 0xf000076800000000, 0x0, // VSX Vector Generate PCV from Word Mask X-form (xxgenpcvwm XT,VRB,IMM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {XXMFACC, 0xfc1f07fe00000000, 0x7c00016200000000, 0x60f80100000000, // VSX Move From Accumulator X-form (xxmfacc AS)
+               [6]*argField{ap_MMAReg_6_8}},
+       {XXMTACC, 0xfc1f07fe00000000, 0x7c01016200000000, 0x60f80100000000, // VSX Move To Accumulator X-form (xxmtacc AT)
+               [6]*argField{ap_MMAReg_6_8}},
+       {XXPERMX, 0xfff00000fc000030, 0x500000088000000, 0xffff800000000, // VSX Vector Permute Extended 8RR:XX4-form (xxpermx XT,XA,XB,XC,UIM)
+               [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57, ap_ImmUnsigned_29_31}},
+       {XXSETACCZ, 0xfc1f07fe00000000, 0x7c03016200000000, 0x60f80100000000, // VSX Set Accumulator to Zero X-form (xxsetaccz AT)
+               [6]*argField{ap_MMAReg_6_8}},
+       {XXSPLTI32DX, 0xfff00000fc1c0000, 0x500000080000000, 0xf000000000000, // VSX Vector Splat Immediate32 Doubleword Indexed 8RR:D-form (xxsplti32dx XT,IX,IMM32)
+               [6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_46_46, ap_ImmUnsigned_16_31_48_63}},
+       {XXSPLTIDP, 0xfff00000fc1e0000, 0x500000080040000, 0xf000000000000, // VSX Vector Splat Immediate Double-Precision 8RR:D-form (xxspltidp XT,IMM32)
+               [6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}},
+       {XXSPLTIW, 0xfff00000fc1e0000, 0x500000080060000, 0xf000000000000, // VSX Vector Splat Immediate Word 8RR:D-form (xxspltiw XT,IMM32)
+               [6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}},
+       {MSGCLRU, 0xfc0007fe00000000, 0x7c0000dc00000000, 0x3ff000100000000, // Ultravisor Message Clear X-form (msgclru RB)
+               [6]*argField{ap_Reg_16_20}},
+       {MSGSNDU, 0xfc0007fe00000000, 0x7c00009c00000000, 0x3ff000100000000, // Ultravisor Message SendX-form (msgsndu RB)
+               [6]*argField{ap_Reg_16_20}},
+       {URFID, 0xfc0007fe00000000, 0x4c00026400000000, 0x3fff80100000000, // Ultravisor Return From Interrupt Doubleword XL-form (urfid)
+               [6]*argField{}},
+       {ADDEX, 0xfc0001fe00000000, 0x7c00015400000000, 0x100000000, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}},
+       {MFFSCDRN, 0xfc1f07fe00000000, 0xfc14048e00000000, 0x100000000, // Move From FPSCR Control & Set DRN X-form (mffscdrn FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {MFFSCDRNI, 0xfc1f07fe00000000, 0xfc15048e00000000, 0xc00100000000, // Move From FPSCR Control & Set DRN Immediate X-form (mffscdrni FRT,DRM)
+               [6]*argField{ap_FPReg_6_10, ap_ImmUnsigned_18_20}},
+       {MFFSCE, 0xfc1f07fe00000000, 0xfc01048e00000000, 0xf80100000000, // Move From FPSCR & Clear Enables X-form (mffsce FRT)
+               [6]*argField{ap_FPReg_6_10}},
+       {MFFSCRN, 0xfc1f07fe00000000, 0xfc16048e00000000, 0x100000000, // Move From FPSCR Control & Set RN X-form (mffscrn FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {MFFSCRNI, 0xfc1f07fe00000000, 0xfc17048e00000000, 0xe00100000000, // Move From FPSCR Control & Set RN Immediate X-form (mffscrni FRT,RM)
+               [6]*argField{ap_FPReg_6_10, ap_ImmUnsigned_19_20}},
+       {MFFSL, 0xfc1f07fe00000000, 0xfc18048e00000000, 0xf80100000000, // Move From FPSCR Lightweight X-form (mffsl FRT)
+               [6]*argField{ap_FPReg_6_10}},
+       {SLBIAG, 0xfc0007fe00000000, 0x7c0006a400000000, 0x1ef80100000000, // SLB Invalidate All Global X-form (slbiag RS, L)
+               [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
+       {VMSUMUDM, 0xfc00003f00000000, 0x1000002300000000, 0x0, // Vector Multiply-Sum Unsigned Doubleword Modulo VA-form (vmsumudm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {ADDPCIS, 0xfc00003e00000000, 0x4c00000400000000, 0x0, // Add PC Immediate Shifted DX-form (addpcis RT,D)
+               [6]*argField{ap_Reg_6_10, ap_ImmSigned_16_25_11_15_31_31}},
+       {BCDCFNCC, 0xfc1f05ff00000000, 0x1007058100000000, 0x0, // Decimal Convert From National VX-form (bcdcfn. VRT,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDCFSQCC, 0xfc1f05ff00000000, 0x1002058100000000, 0x0, // Decimal Convert From Signed Quadword VX-form (bcdcfsq. VRT,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDCFZCC, 0xfc1f05ff00000000, 0x1006058100000000, 0x0, // Decimal Convert From Zoned VX-form (bcdcfz. VRT,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDCPSGNCC, 0xfc0007ff00000000, 0x1000034100000000, 0x0, // Decimal Copy Sign VX-form (bcdcpsgn. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {BCDCTNCC, 0xfc1f05ff00000000, 0x1005058100000000, 0x20000000000, // Decimal Convert To National VX-form (bcdctn. VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {BCDCTSQCC, 0xfc1f05ff00000000, 0x1000058100000000, 0x20000000000, // Decimal Convert To Signed Quadword VX-form (bcdctsq. VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {BCDCTZCC, 0xfc1f05ff00000000, 0x1004058100000000, 0x0, // Decimal Convert To Zoned VX-form (bcdctz. VRT,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDSCC, 0xfc0005ff00000000, 0x100004c100000000, 0x0, // Decimal Shift VX-form (bcds. VRT,VRA,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDSETSGNCC, 0xfc1f05ff00000000, 0x101f058100000000, 0x0, // Decimal Set Sign VX-form (bcdsetsgn. VRT,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDSRCC, 0xfc0005ff00000000, 0x100005c100000000, 0x0, // Decimal Shift and Round VX-form (bcdsr. VRT,VRA,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDTRUNCCC, 0xfc0005ff00000000, 0x1000050100000000, 0x0, // Decimal Truncate VX-form (bcdtrunc. VRT,VRA,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDUSCC, 0xfc0005ff00000000, 0x1000048100000000, 0x20000000000, // Decimal Unsigned Shift VX-form (bcdus. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {BCDUTRUNCCC, 0xfc0005ff00000000, 0x1000054100000000, 0x20000000000, // Decimal Unsigned Truncate VX-form (bcdutrunc. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {CMPEQB, 0xfc0007fe00000000, 0x7c0001c000000000, 0x60000100000000, // Compare Equal Byte X-form (cmpeqb BF,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPRB, 0xfc0007fe00000000, 0x7c00018000000000, 0x40000100000000, // Compare Ranged Byte X-form (cmprb BF,L,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {CNTTZD, 0xfc0007ff00000000, 0x7c00047400000000, 0xf80000000000, // Count Trailing Zeros Doubleword X-form (cnttzd RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CNTTZDCC, 0xfc0007ff00000000, 0x7c00047500000000, 0xf80000000000, // Count Trailing Zeros Doubleword X-form (cnttzd. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CNTTZW, 0xfc0007ff00000000, 0x7c00043400000000, 0xf80000000000, // Count Trailing Zeros Word X-form (cnttzw RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CNTTZWCC, 0xfc0007ff00000000, 0x7c00043500000000, 0xf80000000000, // Count Trailing Zeros Word X-form (cnttzw. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {COPY, 0xfc2007fe00000000, 0x7c20060c00000000, 0x3c0000100000000, // Copy X-form (copy RA,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+       {CPABORT, 0xfc0007fe00000000, 0x7c00068c00000000, 0x3fff80100000000, // Copy-Paste Abort X-form (cpabort)
+               [6]*argField{}},
+       {DARN, 0xfc0007fe00000000, 0x7c0005e600000000, 0x1cf80100000000, // Deliver A Random Number X-form (darn RT,L)
+               [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}},
+       {DTSTSFI, 0xfc0007fe00000000, 0xec00054600000000, 0x40000100000000, // DFP Test Significance Immediate X-form (dtstsfi BF,UIM,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_15, ap_FPReg_16_20}},
+       {DTSTSFIQ, 0xfc0007fe00000000, 0xfc00054600000000, 0x40000100000000, // DFP Test Significance Immediate Quad X-form (dtstsfiq BF,UIM,FRBp)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_15, ap_FPReg_16_20}},
+       {EXTSWSLI, 0xfc0007fd00000000, 0x7c0006f400000000, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+       {EXTSWSLICC, 0xfc0007fd00000000, 0x7c0006f500000000, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+       {LDAT, 0xfc0007fe00000000, 0x7c0004cc00000000, 0x100000000, // Load Doubleword ATomic X-form (ldat RT,RA,FC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+       {LWAT, 0xfc0007fe00000000, 0x7c00048c00000000, 0x100000000, // Load Word ATomic X-form (lwat RT,RA,FC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+       {LXSD, 0xfc00000300000000, 0xe400000200000000, 0x0, // Load VSX Scalar Doubleword DS-form (lxsd VRT,DS(RA))
+               [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {LXSIBZX, 0xfc0007fe00000000, 0x7c00061a00000000, 0x0, // Load VSX Scalar as Integer Byte & Zero Indexed X-form (lxsibzx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXSIHZX, 0xfc0007fe00000000, 0x7c00065a00000000, 0x0, // Load VSX Scalar as Integer Halfword & Zero Indexed X-form (lxsihzx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXSSP, 0xfc00000300000000, 0xe400000300000000, 0x0, // Load VSX Scalar Single-Precision DS-form (lxssp VRT,DS(RA))
+               [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {LXV, 0xfc00000700000000, 0xf400000100000000, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
+               [6]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+       {LXVB16X, 0xfc0007fe00000000, 0x7c0006d800000000, 0x0, // Load VSX Vector Byte*16 Indexed X-form (lxvb16x XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVH8X, 0xfc0007fe00000000, 0x7c00065800000000, 0x0, // Load VSX Vector Halfword*8 Indexed X-form (lxvh8x XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVL, 0xfc0007fe00000000, 0x7c00021a00000000, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVLL, 0xfc0007fe00000000, 0x7c00025a00000000, 0x0, // Load VSX Vector with Length Left-justified X-form (lxvll XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVWSX, 0xfc0007fe00000000, 0x7c0002d800000000, 0x0, // Load VSX Vector Word & Splat Indexed X-form (lxvwsx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVX, 0xfc0007be00000000, 0x7c00021800000000, 0x4000000000, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MADDHD, 0xfc00003f00000000, 0x1000003000000000, 0x0, // Multiply-Add High Doubleword VA-form (maddhd RT,RA,RB,RC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
+       {MADDHDU, 0xfc00003f00000000, 0x1000003100000000, 0x0, // Multiply-Add High Doubleword Unsigned VA-form (maddhdu RT,RA,RB,RC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
+       {MADDLD, 0xfc00003f00000000, 0x1000003300000000, 0x0, // Multiply-Add Low Doubleword VA-form (maddld RT,RA,RB,RC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
+       {MCRXRX, 0xfc0007fe00000000, 0x7c00048000000000, 0x7ff80100000000, // Move to CR from XER Extended X-form (mcrxrx BF)
+               [6]*argField{ap_CondRegField_6_8}},
+       {MFVSRLD, 0xfc0007fe00000000, 0x7c00026600000000, 0xf80000000000, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS)
+               [6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
+       {MODSD, 0xfc0007fe00000000, 0x7c00061200000000, 0x100000000, // Modulo Signed Doubleword X-form (modsd RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MODSW, 0xfc0007fe00000000, 0x7c00061600000000, 0x100000000, // Modulo Signed Word X-form (modsw RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MODUD, 0xfc0007fe00000000, 0x7c00021200000000, 0x100000000, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MODUW, 0xfc0007fe00000000, 0x7c00021600000000, 0x100000000, // Modulo Unsigned Word X-form (moduw RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MSGSYNC, 0xfc0007fe00000000, 0x7c0006ec00000000, 0x3fff80100000000, // Message Synchronize X-form (msgsync)
+               [6]*argField{}},
+       {MTVSRDD, 0xfc0007fe00000000, 0x7c00036600000000, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MTVSRWS, 0xfc0007fe00000000, 0x7c00032600000000, 0xf80000000000, // Move To VSR Word & Splat X-form (mtvsrws XT,RA)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {PASTECC, 0xfc0007ff00000000, 0x7c00070d00000000, 0x3c0000000000000, // Paste X-form (paste. RA,RB,L)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_10_10}},
+       {SETB, 0xfc0007fe00000000, 0x7c00010000000000, 0x3f80100000000, // Set Boolean X-form (setb RT,BFA)
+               [6]*argField{ap_Reg_6_10, ap_CondRegField_11_13}},
+       {SLBIEG, 0xfc0007fe00000000, 0x7c0003a400000000, 0x1f000100000000, // SLB Invalidate Entry Global X-form (slbieg RS,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+       {SLBSYNC, 0xfc0007fe00000000, 0x7c0002a400000000, 0x3fff80100000000, // SLB Synchronize X-form (slbsync)
+               [6]*argField{}},
+       {STDAT, 0xfc0007fe00000000, 0x7c0005cc00000000, 0x100000000, // Store Doubleword ATomic X-form (stdat RS,RA,FC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+       {STOP, 0xfc0007fe00000000, 0x4c0002e400000000, 0x3fff80100000000, // Stop XL-form (stop)
+               [6]*argField{}},
+       {STWAT, 0xfc0007fe00000000, 0x7c00058c00000000, 0x100000000, // Store Word ATomic X-form (stwat RS,RA,FC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+       {STXSD, 0xfc00000300000000, 0xf400000200000000, 0x0, // Store VSX Scalar Doubleword DS-form (stxsd VRS,DS(RA))
+               [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {STXSIBX, 0xfc0007fe00000000, 0x7c00071a00000000, 0x0, // Store VSX Scalar as Integer Byte Indexed X-form (stxsibx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXSIHX, 0xfc0007fe00000000, 0x7c00075a00000000, 0x0, // Store VSX Scalar as Integer Halfword Indexed X-form (stxsihx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXSSP, 0xfc00000300000000, 0xf400000300000000, 0x0, // Store VSX Scalar Single DS-form (stxssp VRS,DS(RA))
+               [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {STXV, 0xfc00000700000000, 0xf400000500000000, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
+               [6]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+       {STXVB16X, 0xfc0007fe00000000, 0x7c0007d800000000, 0x0, // Store VSX Vector Byte*16 Indexed X-form (stxvb16x XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVH8X, 0xfc0007fe00000000, 0x7c00075800000000, 0x0, // Store VSX Vector Halfword*8 Indexed X-form (stxvh8x XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVL, 0xfc0007fe00000000, 0x7c00031a00000000, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVLL, 0xfc0007fe00000000, 0x7c00035a00000000, 0x0, // Store VSX Vector with Length Left-justified X-form (stxvll XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVX, 0xfc0007fe00000000, 0x7c00031800000000, 0x0, // Store VSX Vector Indexed X-form (stxvx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VABSDUB, 0xfc0007ff00000000, 0x1000040300000000, 0x0, // Vector Absolute Difference Unsigned Byte VX-form (vabsdub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VABSDUH, 0xfc0007ff00000000, 0x1000044300000000, 0x0, // Vector Absolute Difference Unsigned Halfword VX-form (vabsduh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VABSDUW, 0xfc0007ff00000000, 0x1000048300000000, 0x0, // Vector Absolute Difference Unsigned Word VX-form (vabsduw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VBPERMD, 0xfc0007ff00000000, 0x100005cc00000000, 0x0, // Vector Bit Permute Doubleword VX-form (vbpermd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCLZLSBB, 0xfc1f07ff00000000, 0x1000060200000000, 0x0, // Vector Count Leading Zero Least-Significant Bits Byte VX-form (vclzlsbb RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VCMPNEB, 0xfc0007ff00000000, 0x1000000700000000, 0x0, // Vector Compare Not Equal Byte VC-form (vcmpneb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEBCC, 0xfc0007ff00000000, 0x1000040700000000, 0x0, // Vector Compare Not Equal Byte VC-form (vcmpneb. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEH, 0xfc0007ff00000000, 0x1000004700000000, 0x0, // Vector Compare Not Equal Halfword VC-form (vcmpneh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEHCC, 0xfc0007ff00000000, 0x1000044700000000, 0x0, // Vector Compare Not Equal Halfword VC-form (vcmpneh. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEW, 0xfc0007ff00000000, 0x1000008700000000, 0x0, // Vector Compare Not Equal Word VC-form (vcmpnew VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEWCC, 0xfc0007ff00000000, 0x1000048700000000, 0x0, // Vector Compare Not Equal Word VC-form (vcmpnew. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEZB, 0xfc0007ff00000000, 0x1000010700000000, 0x0, // Vector Compare Not Equal or Zero Byte VC-form (vcmpnezb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEZBCC, 0xfc0007ff00000000, 0x1000050700000000, 0x0, // Vector Compare Not Equal or Zero Byte VC-form (vcmpnezb. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEZH, 0xfc0007ff00000000, 0x1000014700000000, 0x0, // Vector Compare Not Equal or Zero Halfword VC-form (vcmpnezh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEZHCC, 0xfc0007ff00000000, 0x1000054700000000, 0x0, // Vector Compare Not Equal or Zero Halfword VC-form (vcmpnezh. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEZW, 0xfc0007ff00000000, 0x1000018700000000, 0x0, // Vector Compare Not Equal or Zero Word VC-form (vcmpnezw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPNEZWCC, 0xfc0007ff00000000, 0x1000058700000000, 0x0, // Vector Compare Not Equal or Zero Word VC-form (vcmpnezw. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCTZB, 0xfc1f07ff00000000, 0x101c060200000000, 0x0, // Vector Count Trailing Zeros Byte VX-form (vctzb VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCTZD, 0xfc1f07ff00000000, 0x101f060200000000, 0x0, // Vector Count Trailing Zeros Doubleword VX-form (vctzd VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCTZH, 0xfc1f07ff00000000, 0x101d060200000000, 0x0, // Vector Count Trailing Zeros Halfword VX-form (vctzh VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCTZLSBB, 0xfc1f07ff00000000, 0x1001060200000000, 0x0, // Vector Count Trailing Zero Least-Significant Bits Byte VX-form (vctzlsbb RT,VRB)
+               [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
+       {VCTZW, 0xfc1f07ff00000000, 0x101e060200000000, 0x0, // Vector Count Trailing Zeros Word VX-form (vctzw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTRACTD, 0xfc0007ff00000000, 0x100002cd00000000, 0x10000000000000, // Vector Extract Doubleword to VSR using immediate-specified index VX-form (vextractd VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VEXTRACTUB, 0xfc0007ff00000000, 0x1000020d00000000, 0x10000000000000, // Vector Extract Unsigned Byte to VSR using immediate-specified index VX-form (vextractub VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VEXTRACTUH, 0xfc0007ff00000000, 0x1000024d00000000, 0x10000000000000, // Vector Extract Unsigned Halfword to VSR using immediate-specified index VX-form (vextractuh VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VEXTRACTUW, 0xfc0007ff00000000, 0x1000028d00000000, 0x10000000000000, // Vector Extract Unsigned Word to VSR using immediate-specified index VX-form (vextractuw VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VEXTSB2D, 0xfc1f07ff00000000, 0x1018060200000000, 0x0, // Vector Extend Sign Byte To Doubleword VX-form (vextsb2d VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTSB2W, 0xfc1f07ff00000000, 0x1010060200000000, 0x0, // Vector Extend Sign Byte To Word VX-form (vextsb2w VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTSH2D, 0xfc1f07ff00000000, 0x1019060200000000, 0x0, // Vector Extend Sign Halfword To Doubleword VX-form (vextsh2d VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTSH2W, 0xfc1f07ff00000000, 0x1011060200000000, 0x0, // Vector Extend Sign Halfword To Word VX-form (vextsh2w VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTSW2D, 0xfc1f07ff00000000, 0x101a060200000000, 0x0, // Vector Extend Sign Word To Doubleword VX-form (vextsw2d VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VEXTUBLX, 0xfc0007ff00000000, 0x1000060d00000000, 0x0, // Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-form (vextublx RT,RA,VRB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VEXTUBRX, 0xfc0007ff00000000, 0x1000070d00000000, 0x0, // Vector Extract Unsigned Byte to GPR using GPR-specified Right-Index VX-form (vextubrx RT,RA,VRB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VEXTUHLX, 0xfc0007ff00000000, 0x1000064d00000000, 0x0, // Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index VX-form (vextuhlx RT,RA,VRB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VEXTUHRX, 0xfc0007ff00000000, 0x1000074d00000000, 0x0, // Vector Extract Unsigned Halfword to GPR using GPR-specified Right-Index VX-form (vextuhrx RT,RA,VRB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VEXTUWLX, 0xfc0007ff00000000, 0x1000068d00000000, 0x0, // Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-form (vextuwlx RT,RA,VRB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VEXTUWRX, 0xfc0007ff00000000, 0x1000078d00000000, 0x0, // Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-form (vextuwrx RT,RA,VRB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
+       {VINSERTB, 0xfc0007ff00000000, 0x1000030d00000000, 0x10000000000000, // Vector Insert Byte from VSR using immediate-specified index VX-form (vinsertb VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VINSERTD, 0xfc0007ff00000000, 0x100003cd00000000, 0x10000000000000, // Vector Insert Doubleword from VSR using immediate-specified index VX-form (vinsertd VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VINSERTH, 0xfc0007ff00000000, 0x1000034d00000000, 0x10000000000000, // Vector Insert Halfword from VSR using immediate-specified index VX-form (vinserth VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VINSERTW, 0xfc0007ff00000000, 0x1000038d00000000, 0x10000000000000, // Vector Insert Word from VSR using immediate-specified index VX-form (vinsertw VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VMUL10CUQ, 0xfc0007ff00000000, 0x1000000100000000, 0xf80000000000, // Vector Multiply-by-10 & write Carry-out Unsigned Quadword VX-form (vmul10cuq VRT,VRA)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
+       {VMUL10ECUQ, 0xfc0007ff00000000, 0x1000004100000000, 0x0, // Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword VX-form (vmul10ecuq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMUL10EUQ, 0xfc0007ff00000000, 0x1000024100000000, 0x0, // Vector Multiply-by-10 Extended Unsigned Quadword VX-form (vmul10euq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMUL10UQ, 0xfc0007ff00000000, 0x1000020100000000, 0xf80000000000, // Vector Multiply-by-10 Unsigned Quadword VX-form (vmul10uq VRT,VRA)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
+       {VNEGD, 0xfc1f07ff00000000, 0x1007060200000000, 0x0, // Vector Negate Doubleword VX-form (vnegd VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VNEGW, 0xfc1f07ff00000000, 0x1006060200000000, 0x0, // Vector Negate Word VX-form (vnegw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VPERMR, 0xfc00003f00000000, 0x1000003b00000000, 0x0, // Vector Permute Right-indexed VA-form (vpermr VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VPRTYBD, 0xfc1f07ff00000000, 0x1009060200000000, 0x0, // Vector Parity Byte Doubleword VX-form (vprtybd VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VPRTYBQ, 0xfc1f07ff00000000, 0x100a060200000000, 0x0, // Vector Parity Byte Quadword VX-form (vprtybq VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VPRTYBW, 0xfc1f07ff00000000, 0x1008060200000000, 0x0, // Vector Parity Byte Word VX-form (vprtybw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRLDMI, 0xfc0007ff00000000, 0x100000c500000000, 0x0, // Vector Rotate Left Doubleword then Mask Insert VX-form (vrldmi VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLDNM, 0xfc0007ff00000000, 0x100001c500000000, 0x0, // Vector Rotate Left Doubleword then AND with Mask VX-form (vrldnm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLWMI, 0xfc0007ff00000000, 0x1000008500000000, 0x0, // Vector Rotate Left Word then Mask Insert VX-form (vrlwmi VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLWNM, 0xfc0007ff00000000, 0x1000018500000000, 0x0, // Vector Rotate Left Word then AND with Mask VX-form (vrlwnm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSLV, 0xfc0007ff00000000, 0x1000074400000000, 0x0, // Vector Shift Left Variable VX-form (vslv VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRV, 0xfc0007ff00000000, 0x1000070400000000, 0x0, // Vector Shift Right Variable VX-form (vsrv VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {WAIT, 0xfc0007fe00000000, 0x7c00003c00000000, 0x9cf80100000000, // Wait X-form (wait WC,PL)
+               [6]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_14_15}},
+       {XSABSQP, 0xfc1f07fe00000000, 0xfc00064800000000, 0x100000000, // VSX Scalar Absolute Quad-Precision X-form (xsabsqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSADDQP, 0xfc0007ff00000000, 0xfc00000800000000, 0x0, // VSX Scalar Add Quad-Precision [using round to Odd] X-form (xsaddqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSADDQPO, 0xfc0007ff00000000, 0xfc00000900000000, 0x0, // VSX Scalar Add Quad-Precision [using round to Odd] X-form (xsaddqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCMPEQDP, 0xfc0007f800000000, 0xf000001800000000, 0x0, // VSX Scalar Compare Equal Double-Precision XX3-form (xscmpeqdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCMPEXPDP, 0xfc0007f800000000, 0xf00001d800000000, 0x60000100000000, // VSX Scalar Compare Exponents Double-Precision XX3-form (xscmpexpdp BF,XA,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCMPEXPQP, 0xfc0007fe00000000, 0xfc00014800000000, 0x60000100000000, // VSX Scalar Compare Exponents Quad-Precision X-form (xscmpexpqp BF,VRA,VRB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCMPGEDP, 0xfc0007f800000000, 0xf000009800000000, 0x0, // VSX Scalar Compare Greater Than or Equal Double-Precision XX3-form (xscmpgedp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCMPGTDP, 0xfc0007f800000000, 0xf000005800000000, 0x0, // VSX Scalar Compare Greater Than Double-Precision XX3-form (xscmpgtdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCMPOQP, 0xfc0007fe00000000, 0xfc00010800000000, 0x60000100000000, // VSX Scalar Compare Ordered Quad-Precision X-form (xscmpoqp BF,VRA,VRB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCMPUQP, 0xfc0007fe00000000, 0xfc00050800000000, 0x60000100000000, // VSX Scalar Compare Unordered Quad-Precision X-form (xscmpuqp BF,VRA,VRB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCPSGNQP, 0xfc0007fe00000000, 0xfc0000c800000000, 0x100000000, // VSX Scalar Copy Sign Quad-Precision X-form (xscpsgnqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSCVDPHP, 0xfc1f07fc00000000, 0xf011056c00000000, 0x0, // VSX Scalar Convert with round Double-Precision to Half-Precision format XX2-form (xscvdphp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVDPQP, 0xfc1f07fe00000000, 0xfc16068800000000, 0x100000000, // VSX Scalar Convert Double-Precision to Quad-Precision format X-form (xscvdpqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVHPDP, 0xfc1f07fc00000000, 0xf010056c00000000, 0x0, // VSX Scalar Convert Half-Precision to Double-Precision format XX2-form (xscvhpdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVQPDP, 0xfc1f07ff00000000, 0xfc14068800000000, 0x0, // VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form (xscvqpdp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVQPDPO, 0xfc1f07ff00000000, 0xfc14068900000000, 0x0, // VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form (xscvqpdpo VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVQPSDZ, 0xfc1f07fe00000000, 0xfc19068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form (xscvqpsdz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVQPSWZ, 0xfc1f07fe00000000, 0xfc09068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Word format X-form (xscvqpswz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVQPUDZ, 0xfc1f07fe00000000, 0xfc11068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form (xscvqpudz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVQPUWZ, 0xfc1f07fe00000000, 0xfc01068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format X-form (xscvqpuwz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVSDQP, 0xfc1f07fe00000000, 0xfc0a068800000000, 0x100000000, // VSX Scalar Convert Signed Doubleword to Quad-Precision format X-form (xscvsdqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSCVUDQP, 0xfc1f07fe00000000, 0xfc02068800000000, 0x100000000, // VSX Scalar Convert Unsigned Doubleword to Quad-Precision format X-form (xscvudqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSDIVQP, 0xfc0007ff00000000, 0xfc00044800000000, 0x0, // VSX Scalar Divide Quad-Precision [using round to Odd] X-form (xsdivqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSDIVQPO, 0xfc0007ff00000000, 0xfc00044900000000, 0x0, // VSX Scalar Divide Quad-Precision [using round to Odd] X-form (xsdivqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSIEXPDP, 0xfc0007fe00000000, 0xf000072c00000000, 0x0, // VSX Scalar Insert Exponent Double-Precision X-form (xsiexpdp XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {XSIEXPQP, 0xfc0007fe00000000, 0xfc0006c800000000, 0x100000000, // VSX Scalar Insert Exponent Quad-Precision X-form (xsiexpqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMADDQP, 0xfc0007ff00000000, 0xfc00030800000000, 0x0, // VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form (xsmaddqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMADDQPO, 0xfc0007ff00000000, 0xfc00030900000000, 0x0, // VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form (xsmaddqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMAXCDP, 0xfc0007f800000000, 0xf000040000000000, 0x0, // VSX Scalar Maximum Type-C Double-Precision XX3-form (xsmaxcdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMAXJDP, 0xfc0007f800000000, 0xf000048000000000, 0x0, // VSX Scalar Maximum Type-J Double-Precision XX3-form (xsmaxjdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMINCDP, 0xfc0007f800000000, 0xf000044000000000, 0x0, // VSX Scalar Minimum Type-C Double-Precision XX3-form (xsmincdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMINJDP, 0xfc0007f800000000, 0xf00004c000000000, 0x0, // VSX Scalar Minimum Type-J Double-Precision XX3-form (xsminjdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMSUBQP, 0xfc0007ff00000000, 0xfc00034800000000, 0x0, // VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsmsubqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMSUBQPO, 0xfc0007ff00000000, 0xfc00034900000000, 0x0, // VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsmsubqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMULQP, 0xfc0007ff00000000, 0xfc00004800000000, 0x0, // VSX Scalar Multiply Quad-Precision [using round to Odd] X-form (xsmulqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSMULQPO, 0xfc0007ff00000000, 0xfc00004900000000, 0x0, // VSX Scalar Multiply Quad-Precision [using round to Odd] X-form (xsmulqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSNABSQP, 0xfc1f07fe00000000, 0xfc08064800000000, 0x0, // VSX Scalar Negative Absolute Quad-Precision X-form (xsnabsqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSNEGQP, 0xfc1f07fe00000000, 0xfc10064800000000, 0x100000000, // VSX Scalar Negate Quad-Precision X-form (xsnegqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSNMADDQP, 0xfc0007ff00000000, 0xfc00038800000000, 0x0, // VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form (xsnmaddqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSNMADDQPO, 0xfc0007ff00000000, 0xfc00038900000000, 0x0, // VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form (xsnmaddqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSNMSUBQP, 0xfc0007ff00000000, 0xfc0003c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsnmsubqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSNMSUBQPO, 0xfc0007ff00000000, 0xfc0003c900000000, 0x0, // VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsnmsubqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSRQPI, 0xfc0001ff00000000, 0xfc00000a00000000, 0x1e000000000000, // VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form (xsrqpi R,VRT,VRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}},
+       {XSRQPIX, 0xfc0001ff00000000, 0xfc00000b00000000, 0x1e000000000000, // VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form (xsrqpix R,VRT,VRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}},
+       {XSRQPXP, 0xfc0001fe00000000, 0xfc00004a00000000, 0x1e000100000000, // VSX Scalar Round Quad-Precision to Double-Extended Precision Z23-form (xsrqpxp R,VRT,VRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}},
+       {XSSQRTQP, 0xfc1f07ff00000000, 0xfc1b064800000000, 0x0, // VSX Scalar Square Root Quad-Precision [using round to Odd] X-form (xssqrtqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSSQRTQPO, 0xfc1f07ff00000000, 0xfc1b064900000000, 0x0, // VSX Scalar Square Root Quad-Precision [using round to Odd] X-form (xssqrtqpo VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSSUBQP, 0xfc0007ff00000000, 0xfc00040800000000, 0x0, // VSX Scalar Subtract Quad-Precision [using round to Odd] X-form (xssubqp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSSUBQPO, 0xfc0007ff00000000, 0xfc00040900000000, 0x0, // VSX Scalar Subtract Quad-Precision [using round to Odd] X-form (xssubqpo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {XSTSTDCDP, 0xfc0007fc00000000, 0xf00005a800000000, 0x100000000, // VSX Scalar Test Data Class Double-Precision XX2-form (xststdcdp BF,XB,DCMX)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_9_15}},
+       {XSTSTDCQP, 0xfc0007fe00000000, 0xfc00058800000000, 0x100000000, // VSX Scalar Test Data Class Quad-Precision X-form (xststdcqp BF,VRB,DCMX)
+               [6]*argField{ap_CondRegField_6_8, ap_VecReg_16_20, ap_ImmUnsigned_9_15}},
+       {XSTSTDCSP, 0xfc0007fc00000000, 0xf00004a800000000, 0x100000000, // VSX Scalar Test Data Class Single-Precision XX2-form (xststdcsp BF,XB,DCMX)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_9_15}},
+       {XSXEXPDP, 0xfc1f07fc00000000, 0xf000056c00000000, 0x100000000, // VSX Scalar Extract Exponent Double-Precision XX2-form (xsxexpdp RT,XB)
+               [6]*argField{ap_Reg_6_10, ap_VecSReg_30_30_16_20}},
+       {XSXEXPQP, 0xfc1f07fe00000000, 0xfc02064800000000, 0x100000000, // VSX Scalar Extract Exponent Quad-Precision X-form (xsxexpqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSXSIGDP, 0xfc1f07fc00000000, 0xf001056c00000000, 0x100000000, // VSX Scalar Extract Significand Double-Precision XX2-form (xsxsigdp RT,XB)
+               [6]*argField{ap_Reg_6_10, ap_VecSReg_30_30_16_20}},
+       {XSXSIGQP, 0xfc1f07fe00000000, 0xfc12064800000000, 0x100000000, // VSX Scalar Extract Significand Quad-Precision X-form (xsxsigqp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XVCVHPSP, 0xfc1f07fc00000000, 0xf018076c00000000, 0x0, // VSX Vector Convert Half-Precision to Single-Precision format XX2-form (xvcvhpsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPHP, 0xfc1f07fc00000000, 0xf019076c00000000, 0x0, // VSX Vector Convert with round Single-Precision to Half-Precision format XX2-form (xvcvsphp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVIEXPDP, 0xfc0007f800000000, 0xf00007c000000000, 0x0, // VSX Vector Insert Exponent Double-Precision XX3-form (xviexpdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVIEXPSP, 0xfc0007f800000000, 0xf00006c000000000, 0x0, // VSX Vector Insert Exponent Single-Precision XX3-form (xviexpsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVTSTDCDP, 0xfc0007b800000000, 0xf00007a800000000, 0x0, // VSX Vector Test Data Class Double-Precision XX2-form (xvtstdcdp XT,XB,DCMX)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_25_25_29_29_11_15}},
+       {XVTSTDCSP, 0xfc0007b800000000, 0xf00006a800000000, 0x0, // VSX Vector Test Data Class Single-Precision XX2-form (xvtstdcsp XT,XB,DCMX)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_25_25_29_29_11_15}},
+       {XVXEXPDP, 0xfc1f07fc00000000, 0xf000076c00000000, 0x0, // VSX Vector Extract Exponent Double-Precision XX2-form (xvxexpdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVXEXPSP, 0xfc1f07fc00000000, 0xf008076c00000000, 0x0, // VSX Vector Extract Exponent Single-Precision XX2-form (xvxexpsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVXSIGDP, 0xfc1f07fc00000000, 0xf001076c00000000, 0x0, // VSX Vector Extract Significand Double-Precision XX2-form (xvxsigdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVXSIGSP, 0xfc1f07fc00000000, 0xf009076c00000000, 0x0, // VSX Vector Extract Significand Single-Precision XX2-form (xvxsigsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XXBRD, 0xfc1f07fc00000000, 0xf017076c00000000, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XXBRH, 0xfc1f07fc00000000, 0xf007076c00000000, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XXBRQ, 0xfc1f07fc00000000, 0xf01f076c00000000, 0x0, // VSX Vector Byte-Reverse Quadword XX2-form (xxbrq XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XXBRW, 0xfc1f07fc00000000, 0xf00f076c00000000, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XXEXTRACTUW, 0xfc0007fc00000000, 0xf000029400000000, 0x10000000000000, // VSX Vector Extract Unsigned Word XX2-form (xxextractuw XT,XB,UIM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_12_15}},
+       {XXINSERTW, 0xfc0007fc00000000, 0xf00002d400000000, 0x10000000000000, // VSX Vector Insert Word XX2-form (xxinsertw XT,XB,UIM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_12_15}},
+       {XXPERM, 0xfc0007f800000000, 0xf00000d000000000, 0x0, // VSX Vector Permute XX3-form (xxperm XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXPERMR, 0xfc0007f800000000, 0xf00001d000000000, 0x0, // VSX Vector Permute Right-indexed XX3-form (xxpermr XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXSPLTIB, 0xfc1807fe00000000, 0xf00002d000000000, 0x0, // VSX Vector Splat Immediate Byte X-form (xxspltib XT,IMM8)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_ImmUnsigned_13_20}},
+       {BCDADDCC, 0xfc0005ff00000000, 0x1000040100000000, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCDSUBCC, 0xfc0005ff00000000, 0x1000044100000000, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+       {BCTAR, 0xfc0007ff00000000, 0x4c00046000000000, 0xe00000000000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+       {BCTARL, 0xfc0007ff00000000, 0x4c00046100000000, 0xe00000000000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+       {CLRBHRB, 0xfc0007fe00000000, 0x7c00035c00000000, 0x3fff80100000000, // Clear BHRB X-form (clrbhrb)
+               [6]*argField{}},
+       {FMRGEW, 0xfc0007fe00000000, 0xfc00078c00000000, 0x100000000, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FMRGOW, 0xfc0007fe00000000, 0xfc00068c00000000, 0x100000000, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {ICBT, 0xfc0007fe00000000, 0x7c00002c00000000, 0x200000100000000, // Instruction Cache Block Touch X-form (icbt CT, RA, RB)
+               [6]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LQARX, 0xfc0007fe00000000, 0x7c00022800000000, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+       {LXSIWAX, 0xfc0007fe00000000, 0x7c00009800000000, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed X-form (lxsiwax XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXSIWZX, 0xfc0007fe00000000, 0x7c00001800000000, 0x0, // Load VSX Scalar as Integer Word & Zero Indexed X-form (lxsiwzx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXSSPX, 0xfc0007fe00000000, 0x7c00041800000000, 0x0, // Load VSX Scalar Single-Precision Indexed X-form (lxsspx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MFBHRBE, 0xfc0007fe00000000, 0x7c00025c00000000, 0x100000000, // Move From BHRB XFX-form (mfbhrbe RT,BHRBE)
+               [6]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
+       {MFVSRD, 0xfc0007fe00000000, 0x7c00006600000000, 0xf80000000000, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
+               [6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
+       {MFVSRWZ, 0xfc0007fe00000000, 0x7c0000e600000000, 0xf80000000000, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
+               [6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
+       {MSGCLR, 0xfc0007fe00000000, 0x7c0001dc00000000, 0x3ff000100000000, // Message Clear X-form (msgclr RB)
+               [6]*argField{ap_Reg_16_20}},
+       {MSGCLRP, 0xfc0007fe00000000, 0x7c00015c00000000, 0x3ff000100000000, // Message Clear Privileged X-form (msgclrp RB)
+               [6]*argField{ap_Reg_16_20}},
+       {MSGSND, 0xfc0007fe00000000, 0x7c00019c00000000, 0x3ff000100000000, // Message Send X-form (msgsnd RB)
+               [6]*argField{ap_Reg_16_20}},
+       {MSGSNDP, 0xfc0007fe00000000, 0x7c00011c00000000, 0x3ff000100000000, // Message Send Privileged X-form (msgsndp RB)
+               [6]*argField{ap_Reg_16_20}},
+       {MTVSRD, 0xfc0007fe00000000, 0x7c00016600000000, 0xf80000000000, // Move To VSR Doubleword X-form (mtvsrd XT,RA)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {MTVSRWA, 0xfc0007fe00000000, 0x7c0001a600000000, 0xf80000000000, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {MTVSRWZ, 0xfc0007fe00000000, 0x7c0001e600000000, 0xf80000000000, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
+       {RFEBB, 0xfc0007fe00000000, 0x4c00012400000000, 0x3fff00100000000, // Return from Event Based Branch XL-form (rfebb S)
+               [6]*argField{ap_ImmUnsigned_20_20}},
+       {STQCXCC, 0xfc0007ff00000000, 0x7c00016d00000000, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXSIWX, 0xfc0007fe00000000, 0x7c00011800000000, 0x0, // Store VSX Scalar as Integer Word Indexed X-form (stxsiwx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXSSPX, 0xfc0007fe00000000, 0x7c00051800000000, 0x0, // Store VSX Scalar Single-Precision Indexed X-form (stxsspx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {VADDCUQ, 0xfc0007ff00000000, 0x1000014000000000, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDECUQ, 0xfc00003f00000000, 0x1000003d00000000, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VADDEUQM, 0xfc00003f00000000, 0x1000003c00000000, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VADDUDM, 0xfc0007ff00000000, 0x100000c000000000, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUQM, 0xfc0007ff00000000, 0x1000010000000000, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VBPERMQ, 0xfc0007ff00000000, 0x1000054c00000000, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCIPHER, 0xfc0007ff00000000, 0x1000050800000000, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCIPHERLAST, 0xfc0007ff00000000, 0x1000050900000000, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCLZB, 0xfc0007ff00000000, 0x1000070200000000, 0x1f000000000000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCLZD, 0xfc0007ff00000000, 0x100007c200000000, 0x1f000000000000, // Vector Count Leading Zeros Doubleword VX-form (vclzd VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCLZH, 0xfc0007ff00000000, 0x1000074200000000, 0x1f000000000000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCLZW, 0xfc0007ff00000000, 0x1000078200000000, 0x1f000000000000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VCMPEQUD, 0xfc0007ff00000000, 0x100000c700000000, 0x0, // Vector Compare Equal Unsigned Doubleword VC-form (vcmpequd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUDCC, 0xfc0007ff00000000, 0x100004c700000000, 0x0, // Vector Compare Equal Unsigned Doubleword VC-form (vcmpequd. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSD, 0xfc0007ff00000000, 0x100003c700000000, 0x0, // Vector Compare Greater Than Signed Doubleword VC-form (vcmpgtsd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSDCC, 0xfc0007ff00000000, 0x100007c700000000, 0x0, // Vector Compare Greater Than Signed Doubleword VC-form (vcmpgtsd. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUD, 0xfc0007ff00000000, 0x100002c700000000, 0x0, // Vector Compare Greater Than Unsigned Doubleword VC-form (vcmpgtud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUDCC, 0xfc0007ff00000000, 0x100006c700000000, 0x0, // Vector Compare Greater Than Unsigned Doubleword VC-form (vcmpgtud. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VEQV, 0xfc0007ff00000000, 0x1000068400000000, 0x0, // Vector Logical Equivalence VX-form (veqv VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VGBBD, 0xfc0007ff00000000, 0x1000050c00000000, 0x1f000000000000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VMAXSD, 0xfc0007ff00000000, 0x100001c200000000, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXUD, 0xfc0007ff00000000, 0x100000c200000000, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINSD, 0xfc0007ff00000000, 0x100003c200000000, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINUD, 0xfc0007ff00000000, 0x100002c200000000, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGEW, 0xfc0007ff00000000, 0x1000078c00000000, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGOW, 0xfc0007ff00000000, 0x1000068c00000000, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULESW, 0xfc0007ff00000000, 0x1000038800000000, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULEUW, 0xfc0007ff00000000, 0x1000028800000000, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOSW, 0xfc0007ff00000000, 0x1000018800000000, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOUW, 0xfc0007ff00000000, 0x1000008800000000, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULUWM, 0xfc0007ff00000000, 0x1000008900000000, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VNAND, 0xfc0007ff00000000, 0x1000058400000000, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VNCIPHER, 0xfc0007ff00000000, 0x1000054800000000, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VNCIPHERLAST, 0xfc0007ff00000000, 0x1000054900000000, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VORC, 0xfc0007ff00000000, 0x1000054400000000, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPERMXOR, 0xfc00003f00000000, 0x1000002d00000000, 0x0, // Vector Permute & Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VPKSDSS, 0xfc0007ff00000000, 0x100005ce00000000, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKSDUS, 0xfc0007ff00000000, 0x1000054e00000000, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKUDUM, 0xfc0007ff00000000, 0x1000044e00000000, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKUDUS, 0xfc0007ff00000000, 0x100004ce00000000, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPMSUMB, 0xfc0007ff00000000, 0x1000040800000000, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPMSUMD, 0xfc0007ff00000000, 0x100004c800000000, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPMSUMH, 0xfc0007ff00000000, 0x1000044800000000, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPMSUMW, 0xfc0007ff00000000, 0x1000048800000000, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPOPCNTB, 0xfc0007ff00000000, 0x1000070300000000, 0x1f000000000000, // Vector Population Count Byte VX-form (vpopcntb VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VPOPCNTD, 0xfc0007ff00000000, 0x100007c300000000, 0x1f000000000000, // Vector Population Count Doubleword VX-form (vpopcntd VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VPOPCNTH, 0xfc0007ff00000000, 0x1000074300000000, 0x1f000000000000, // Vector Population Count Halfword VX-form (vpopcnth VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VPOPCNTW, 0xfc0007ff00000000, 0x1000078300000000, 0x1f000000000000, // Vector Population Count Word VX-form (vpopcntw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRLD, 0xfc0007ff00000000, 0x100000c400000000, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSBOX, 0xfc0007ff00000000, 0x100005c800000000, 0xf80000000000, // Vector AES SubBytes VX-form (vsbox VRT,VRA)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
+       {VSHASIGMAD, 0xfc0007ff00000000, 0x100006c200000000, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
+       {VSHASIGMAW, 0xfc0007ff00000000, 0x1000068200000000, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
+       {VSLD, 0xfc0007ff00000000, 0x100005c400000000, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRAD, 0xfc0007ff00000000, 0x100003c400000000, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRD, 0xfc0007ff00000000, 0x100006c400000000, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBCUQ, 0xfc0007ff00000000, 0x1000054000000000, 0x0, // Vector Subtract & write Carry-out Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBECUQ, 0xfc00003f00000000, 0x1000003f00000000, 0x0, // Vector Subtract Extended & write Carry-out Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VSUBEUQM, 0xfc00003f00000000, 0x1000003e00000000, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VSUBUDM, 0xfc0007ff00000000, 0x100004c000000000, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUQM, 0xfc0007ff00000000, 0x1000050000000000, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VUPKHSW, 0xfc0007ff00000000, 0x1000064e00000000, 0x1f000000000000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VUPKLSW, 0xfc0007ff00000000, 0x100006ce00000000, 0x1f000000000000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {XSADDSP, 0xfc0007f800000000, 0xf000000000000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCVDPSPN, 0xfc0007fc00000000, 0xf000042c00000000, 0x1f000000000000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVSPDPN, 0xfc0007fc00000000, 0xf000052c00000000, 0x1f000000000000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVSXDSP, 0xfc0007fc00000000, 0xf00004e000000000, 0x1f000000000000, // VSX Scalar Convert with round Signed Doubleword to Single-Precision format XX2-form (xscvsxdsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVUXDSP, 0xfc0007fc00000000, 0xf00004a000000000, 0x1f000000000000, // VSX Scalar Convert with round Unsigned Doubleword to Single-Precision XX2-form (xscvuxdsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSDIVSP, 0xfc0007f800000000, 0xf00000c000000000, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMADDASP, 0xfc0007f800000000, 0xf000000800000000, 0x0, // VSX Scalar Multiply-Add Type-A Single-Precision XX3-form (xsmaddasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMADDMSP, 0xfc0007f800000000, 0xf000004800000000, 0x0, // VSX Scalar Multiply-Add Type-M Single-Precision XX3-form (xsmaddmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMSUBASP, 0xfc0007f800000000, 0xf000008800000000, 0x0, // VSX Scalar Multiply-Subtract Type-A Single-Precision XX3-form (xsmsubasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMSUBMSP, 0xfc0007f800000000, 0xf00000c800000000, 0x0, // VSX Scalar Multiply-Subtract Type-M Single-Precision XX3-form (xsmsubmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMULSP, 0xfc0007f800000000, 0xf000008000000000, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMADDASP, 0xfc0007f800000000, 0xf000040800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-A Single-Precision XX3-form (xsnmaddasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMADDMSP, 0xfc0007f800000000, 0xf000044800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-M Single-Precision XX3-form (xsnmaddmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMSUBASP, 0xfc0007f800000000, 0xf000048800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-A Single-Precision XX3-form (xsnmsubasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMSUBMSP, 0xfc0007f800000000, 0xf00004c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-M Single-Precision XX3-form (xsnmsubmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSRESP, 0xfc0007fc00000000, 0xf000006800000000, 0x1f000000000000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRSP, 0xfc0007fc00000000, 0xf000046400000000, 0x1f000000000000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRSQRTESP, 0xfc0007fc00000000, 0xf000002800000000, 0x1f000000000000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSSQRTSP, 0xfc0007fc00000000, 0xf000002c00000000, 0x1f000000000000, // VSX Scalar Square Root Single-Precision XX2-form (xssqrtsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSSUBSP, 0xfc0007f800000000, 0xf000004000000000, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLEQV, 0xfc0007f800000000, 0xf00005d000000000, 0x0, // VSX Vector Logical Equivalence XX3-form (xxleqv XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLNAND, 0xfc0007f800000000, 0xf000059000000000, 0x0, // VSX Vector Logical NAND XX3-form (xxlnand XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLORC, 0xfc0007f800000000, 0xf000055000000000, 0x0, // VSX Vector Logical OR with Complement XX3-form (xxlorc XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {ADDG6S, 0xfc0003fe00000000, 0x7c00009400000000, 0x40100000000, // Add and Generate Sixes XO-form (addg6s RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {BPERMD, 0xfc0007fe00000000, 0x7c0001f800000000, 0x100000000, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {CBCDTD, 0xfc0007fe00000000, 0x7c00027400000000, 0xf80100000000, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CDTBCD, 0xfc0007fe00000000, 0x7c00023400000000, 0xf80100000000, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {DCFFIX, 0xfc0007ff00000000, 0xec00064400000000, 0x1f000000000000, // DFP Convert From Fixed X-form (dcffix FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCFFIXCC, 0xfc0007ff00000000, 0xec00064500000000, 0x1f000000000000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DIVDE, 0xfc0007ff00000000, 0x7c00035200000000, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDECC, 0xfc0007ff00000000, 0x7c00035300000000, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDEO, 0xfc0007ff00000000, 0x7c00075200000000, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDEOCC, 0xfc0007ff00000000, 0x7c00075300000000, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDEU, 0xfc0007ff00000000, 0x7c00031200000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDEUCC, 0xfc0007ff00000000, 0x7c00031300000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDEUO, 0xfc0007ff00000000, 0x7c00071200000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDEUOCC, 0xfc0007ff00000000, 0x7c00071300000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWE, 0xfc0007ff00000000, 0x7c00035600000000, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWECC, 0xfc0007ff00000000, 0x7c00035700000000, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWEO, 0xfc0007ff00000000, 0x7c00075600000000, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWEOCC, 0xfc0007ff00000000, 0x7c00075700000000, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWEU, 0xfc0007ff00000000, 0x7c00031600000000, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWEUCC, 0xfc0007ff00000000, 0x7c00031700000000, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWEUO, 0xfc0007ff00000000, 0x7c00071600000000, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWEUOCC, 0xfc0007ff00000000, 0x7c00071700000000, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {FCFIDS, 0xfc0007ff00000000, 0xec00069c00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCFIDSCC, 0xfc0007ff00000000, 0xec00069d00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCFIDU, 0xfc0007ff00000000, 0xfc00079c00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCFIDUCC, 0xfc0007ff00000000, 0xfc00079d00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCFIDUS, 0xfc0007ff00000000, 0xec00079c00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCFIDUSCC, 0xfc0007ff00000000, 0xec00079d00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDU, 0xfc0007ff00000000, 0xfc00075c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDUCC, 0xfc0007ff00000000, 0xfc00075d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDUZ, 0xfc0007ff00000000, 0xfc00075e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDUZCC, 0xfc0007ff00000000, 0xfc00075f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWU, 0xfc0007ff00000000, 0xfc00011c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWUCC, 0xfc0007ff00000000, 0xfc00011d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWUZ, 0xfc0007ff00000000, 0xfc00011e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWUZCC, 0xfc0007ff00000000, 0xfc00011f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FTDIV, 0xfc0007fe00000000, 0xfc00010000000000, 0x60000100000000, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FTSQRT, 0xfc0007fe00000000, 0xfc00014000000000, 0x7f000100000000, // Floating Test for software Square Root X-form (ftsqrt BF,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
+       {LBARX, 0xfc0007fe00000000, 0x7c00006800000000, 0x0, // Load Byte And Reserve Indexed X-form (lbarx RT,RA,RB,EH)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+       {LDBRX, 0xfc0007fe00000000, 0x7c00042800000000, 0x100000000, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFIWZX, 0xfc0007fe00000000, 0x7c0006ee00000000, 0x100000000, // Load Floating-Point as Integer Word & Zero Indexed X-form (lfiwzx FRT,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHARX, 0xfc0007fe00000000, 0x7c0000e800000000, 0x0, // Load Halfword And Reserve Indexed Xform (lharx RT,RA,RB,EH)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+       {LXSDX, 0xfc0007fe00000000, 0x7c00049800000000, 0x0, // Load VSX Scalar Doubleword Indexed X-form (lxsdx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVD2X, 0xfc0007fe00000000, 0x7c00069800000000, 0x0, // Load VSX Vector Doubleword*2 Indexed X-form (lxvd2x XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVDSX, 0xfc0007fe00000000, 0x7c00029800000000, 0x0, // Load VSX Vector Doubleword & Splat Indexed X-form (lxvdsx XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LXVW4X, 0xfc0007fe00000000, 0x7c00061800000000, 0x0, // Load VSX Vector Word*4 Indexed X-form (lxvw4x XT,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {POPCNTD, 0xfc0007fe00000000, 0x7c0003f400000000, 0xf80100000000, // Population Count Doubleword X-form (popcntd RA, RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {POPCNTW, 0xfc0007fe00000000, 0x7c0002f400000000, 0xf80100000000, // Population Count Words X-form (popcntw RA, RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {STBCXCC, 0xfc0007ff00000000, 0x7c00056d00000000, 0x0, // Store Byte Conditional Indexed X-form (stbcx. RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STDBRX, 0xfc0007fe00000000, 0x7c00052800000000, 0x100000000, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STHCXCC, 0xfc0007ff00000000, 0x7c0005ad00000000, 0x0, // Store Halfword Conditional Indexed X-form (sthcx. RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXSDX, 0xfc0007fe00000000, 0x7c00059800000000, 0x0, // Store VSX Scalar Doubleword Indexed X-form (stxsdx XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVD2X, 0xfc0007fe00000000, 0x7c00079800000000, 0x0, // Store VSX Vector Doubleword*2 Indexed X-form (stxvd2x XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STXVW4X, 0xfc0007fe00000000, 0x7c00071800000000, 0x0, // Store VSX Vector Word*4 Indexed X-form (stxvw4x XS,RA,RB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {XSABSDP, 0xfc0007fc00000000, 0xf000056400000000, 0x1f000000000000, // VSX Scalar Absolute Double-Precision XX2-form (xsabsdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSADDDP, 0xfc0007f800000000, 0xf000010000000000, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCMPODP, 0xfc0007f800000000, 0xf000015800000000, 0x60000100000000, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCMPUDP, 0xfc0007f800000000, 0xf000011800000000, 0x60000100000000, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCPSGNDP, 0xfc0007f800000000, 0xf000058000000000, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSCVDPSP, 0xfc0007fc00000000, 0xf000042400000000, 0x1f000000000000, // VSX Scalar Convert with round Double-Precision to Single-Precision format XX2-form (xscvdpsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVDPSXDS, 0xfc0007fc00000000, 0xf000056000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Signed Doubleword format XX2-form (xscvdpsxds XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVDPSXWS, 0xfc0007fc00000000, 0xf000016000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Signed Word format XX2-form (xscvdpsxws XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVDPUXDS, 0xfc0007fc00000000, 0xf000052000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form (xscvdpuxds XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVDPUXWS, 0xfc0007fc00000000, 0xf000012000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Unsigned Word format XX2-form (xscvdpuxws XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVSPDP, 0xfc0007fc00000000, 0xf000052400000000, 0x1f000000000000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVSXDDP, 0xfc0007fc00000000, 0xf00005e000000000, 0x1f000000000000, // VSX Scalar Convert with round Signed Doubleword to Double-Precision format XX2-form (xscvsxddp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSCVUXDDP, 0xfc0007fc00000000, 0xf00005a000000000, 0x1f000000000000, // VSX Scalar Convert with round Unsigned Doubleword to Double-Precision format XX2-form (xscvuxddp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSDIVDP, 0xfc0007f800000000, 0xf00001c000000000, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMADDADP, 0xfc0007f800000000, 0xf000010800000000, 0x0, // VSX Scalar Multiply-Add Type-A Double-Precision XX3-form (xsmaddadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMADDMDP, 0xfc0007f800000000, 0xf000014800000000, 0x0, // VSX Scalar Multiply-Add Type-M Double-Precision XX3-form (xsmaddmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMAXDP, 0xfc0007f800000000, 0xf000050000000000, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMINDP, 0xfc0007f800000000, 0xf000054000000000, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMSUBADP, 0xfc0007f800000000, 0xf000018800000000, 0x0, // VSX Scalar Multiply-Subtract Type-A Double-Precision XX3-form (xsmsubadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMSUBMDP, 0xfc0007f800000000, 0xf00001c800000000, 0x0, // VSX Scalar Multiply-Subtract Type-M Double-Precision XX3-form (xsmsubmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSMULDP, 0xfc0007f800000000, 0xf000018000000000, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNABSDP, 0xfc0007fc00000000, 0xf00005a400000000, 0x1f000000000000, // VSX Scalar Negative Absolute Double-Precision XX2-form (xsnabsdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSNEGDP, 0xfc0007fc00000000, 0xf00005e400000000, 0x1f000000000000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSNMADDADP, 0xfc0007f800000000, 0xf000050800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-A Double-Precision XX3-form (xsnmaddadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMADDMDP, 0xfc0007f800000000, 0xf000054800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-M Double-Precision XX3-form (xsnmaddmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMSUBADP, 0xfc0007f800000000, 0xf000058800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-A Double-Precision XX3-form (xsnmsubadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSNMSUBMDP, 0xfc0007f800000000, 0xf00005c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-M Double-Precision XX3-form (xsnmsubmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSRDPI, 0xfc0007fc00000000, 0xf000012400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRDPIC, 0xfc0007fc00000000, 0xf00001ac00000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRDPIM, 0xfc0007fc00000000, 0xf00001e400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRDPIP, 0xfc0007fc00000000, 0xf00001a400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRDPIZ, 0xfc0007fc00000000, 0xf000016400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSREDP, 0xfc0007fc00000000, 0xf000016800000000, 0x1f000000000000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSRSQRTEDP, 0xfc0007fc00000000, 0xf000012800000000, 0x1f000000000000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSSQRTDP, 0xfc0007fc00000000, 0xf000012c00000000, 0x1f000000000000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XSSUBDP, 0xfc0007f800000000, 0xf000014000000000, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSTDIVDP, 0xfc0007f800000000, 0xf00001e800000000, 0x60000100000000, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XSTSQRTDP, 0xfc0007fc00000000, 0xf00001a800000000, 0x7f000100000000, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
+       {XVABSDP, 0xfc0007fc00000000, 0xf000076400000000, 0x1f000000000000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVABSSP, 0xfc0007fc00000000, 0xf000066400000000, 0x1f000000000000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVADDDP, 0xfc0007f800000000, 0xf000030000000000, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVADDSP, 0xfc0007f800000000, 0xf000020000000000, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPEQDP, 0xfc0007f800000000, 0xf000031800000000, 0x0, // VSX Vector Compare Equal To Double-Precision XX3-form (xvcmpeqdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPEQDPCC, 0xfc0007f800000000, 0xf000071800000000, 0x0, // VSX Vector Compare Equal To Double-Precision XX3-form (xvcmpeqdp. XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPEQSP, 0xfc0007f800000000, 0xf000021800000000, 0x0, // VSX Vector Compare Equal To Single-Precision XX3-form (xvcmpeqsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPEQSPCC, 0xfc0007f800000000, 0xf000061800000000, 0x0, // VSX Vector Compare Equal To Single-Precision XX3-form (xvcmpeqsp. XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGEDP, 0xfc0007f800000000, 0xf000039800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form (xvcmpgedp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGEDPCC, 0xfc0007f800000000, 0xf000079800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form (xvcmpgedp. XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGESP, 0xfc0007f800000000, 0xf000029800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form (xvcmpgesp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGESPCC, 0xfc0007f800000000, 0xf000069800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form (xvcmpgesp. XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGTDP, 0xfc0007f800000000, 0xf000035800000000, 0x0, // VSX Vector Compare Greater Than Double-Precision XX3-form (xvcmpgtdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGTDPCC, 0xfc0007f800000000, 0xf000075800000000, 0x0, // VSX Vector Compare Greater Than Double-Precision XX3-form (xvcmpgtdp. XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGTSP, 0xfc0007f800000000, 0xf000025800000000, 0x0, // VSX Vector Compare Greater Than Single-Precision XX3-form (xvcmpgtsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCMPGTSPCC, 0xfc0007f800000000, 0xf000065800000000, 0x0, // VSX Vector Compare Greater Than Single-Precision XX3-form (xvcmpgtsp. XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCPSGNDP, 0xfc0007f800000000, 0xf000078000000000, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCPSGNSP, 0xfc0007f800000000, 0xf000068000000000, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVCVDPSP, 0xfc0007fc00000000, 0xf000062400000000, 0x1f000000000000, // VSX Vector Convert with round Double-Precision to Single-Precision format XX2-form (xvcvdpsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVDPSXDS, 0xfc0007fc00000000, 0xf000076000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Signed Doubleword format XX2-form (xvcvdpsxds XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVDPSXWS, 0xfc0007fc00000000, 0xf000036000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Signed Word format XX2-form (xvcvdpsxws XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVDPUXDS, 0xfc0007fc00000000, 0xf000072000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form (xvcvdpuxds XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVDPUXWS, 0xfc0007fc00000000, 0xf000032000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Unsigned Word format XX2-form (xvcvdpuxws XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPDP, 0xfc0007fc00000000, 0xf000072400000000, 0x1f000000000000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPSXDS, 0xfc0007fc00000000, 0xf000066000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-form (xvcvspsxds XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPSXWS, 0xfc0007fc00000000, 0xf000026000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Signed Word format XX2-form (xvcvspsxws XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPUXDS, 0xfc0007fc00000000, 0xf000062000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Unsigned Doubleword format XX2-form (xvcvspuxds XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSPUXWS, 0xfc0007fc00000000, 0xf000022000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Unsigned Word format XX2-form (xvcvspuxws XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSXDDP, 0xfc0007fc00000000, 0xf00007e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSXDSP, 0xfc0007fc00000000, 0xf00006e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSXWDP, 0xfc0007fc00000000, 0xf00003e000000000, 0x1f000000000000, // VSX Vector Convert Signed Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVSXWSP, 0xfc0007fc00000000, 0xf00002e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVUXDDP, 0xfc0007fc00000000, 0xf00007a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVUXDSP, 0xfc0007fc00000000, 0xf00006a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVUXWDP, 0xfc0007fc00000000, 0xf00003a000000000, 0x1f000000000000, // VSX Vector Convert Unsigned Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVCVUXWSP, 0xfc0007fc00000000, 0xf00002a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVDIVDP, 0xfc0007f800000000, 0xf00003c000000000, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVDIVSP, 0xfc0007f800000000, 0xf00002c000000000, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMADDADP, 0xfc0007f800000000, 0xf000030800000000, 0x0, // VSX Vector Multiply-Add Type-A Double-Precision XX3-form (xvmaddadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMADDASP, 0xfc0007f800000000, 0xf000020800000000, 0x0, // VSX Vector Multiply-Add Type-A Single-Precision XX3-form (xvmaddasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMADDMDP, 0xfc0007f800000000, 0xf000034800000000, 0x0, // VSX Vector Multiply-Add Type-M Double-Precision XX3-form (xvmaddmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMADDMSP, 0xfc0007f800000000, 0xf000024800000000, 0x0, // VSX Vector Multiply-Add Type-M Single-Precision XX3-form (xvmaddmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMAXDP, 0xfc0007f800000000, 0xf000070000000000, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMAXSP, 0xfc0007f800000000, 0xf000060000000000, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMINDP, 0xfc0007f800000000, 0xf000074000000000, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMINSP, 0xfc0007f800000000, 0xf000064000000000, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMSUBADP, 0xfc0007f800000000, 0xf000038800000000, 0x0, // VSX Vector Multiply-Subtract Type-A Double-Precision XX3-form (xvmsubadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMSUBASP, 0xfc0007f800000000, 0xf000028800000000, 0x0, // VSX Vector Multiply-Subtract Type-A Single-Precision XX3-form (xvmsubasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMSUBMDP, 0xfc0007f800000000, 0xf00003c800000000, 0x0, // VSX Vector Multiply-Subtract Type-M Double-Precision XX3-form (xvmsubmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMSUBMSP, 0xfc0007f800000000, 0xf00002c800000000, 0x0, // VSX Vector Multiply-Subtract Type-M Single-Precision XX3-form (xvmsubmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMULDP, 0xfc0007f800000000, 0xf000038000000000, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVMULSP, 0xfc0007f800000000, 0xf000028000000000, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNABSDP, 0xfc0007fc00000000, 0xf00007a400000000, 0x1f000000000000, // VSX Vector Negative Absolute Double-Precision XX2-form (xvnabsdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVNABSSP, 0xfc0007fc00000000, 0xf00006a400000000, 0x1f000000000000, // VSX Vector Negative Absolute Single-Precision XX2-form (xvnabssp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVNEGDP, 0xfc0007fc00000000, 0xf00007e400000000, 0x1f000000000000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVNEGSP, 0xfc0007fc00000000, 0xf00006e400000000, 0x1f000000000000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVNMADDADP, 0xfc0007f800000000, 0xf000070800000000, 0x0, // VSX Vector Negative Multiply-Add Type-A Double-Precision XX3-form (xvnmaddadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMADDASP, 0xfc0007f800000000, 0xf000060800000000, 0x0, // VSX Vector Negative Multiply-Add Type-A Single-Precision XX3-form (xvnmaddasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMADDMDP, 0xfc0007f800000000, 0xf000074800000000, 0x0, // VSX Vector Negative Multiply-Add Type-M Double-Precision XX3-form (xvnmaddmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMADDMSP, 0xfc0007f800000000, 0xf000064800000000, 0x0, // VSX Vector Negative Multiply-Add Type-M Single-Precision XX3-form (xvnmaddmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMSUBADP, 0xfc0007f800000000, 0xf000078800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-A Double-Precision XX3-form (xvnmsubadp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMSUBASP, 0xfc0007f800000000, 0xf000068800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-A Single-Precision XX3-form (xvnmsubasp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMSUBMDP, 0xfc0007f800000000, 0xf00007c800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-M Double-Precision XX3-form (xvnmsubmdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVNMSUBMSP, 0xfc0007f800000000, 0xf00006c800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-M Single-Precision XX3-form (xvnmsubmsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVRDPI, 0xfc0007fc00000000, 0xf000032400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRDPIC, 0xfc0007fc00000000, 0xf00003ac00000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRDPIM, 0xfc0007fc00000000, 0xf00003e400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRDPIP, 0xfc0007fc00000000, 0xf00003a400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRDPIZ, 0xfc0007fc00000000, 0xf000036400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVREDP, 0xfc0007fc00000000, 0xf000036800000000, 0x1f000000000000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRESP, 0xfc0007fc00000000, 0xf000026800000000, 0x1f000000000000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSPI, 0xfc0007fc00000000, 0xf000022400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSPIC, 0xfc0007fc00000000, 0xf00002ac00000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSPIM, 0xfc0007fc00000000, 0xf00002e400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSPIP, 0xfc0007fc00000000, 0xf00002a400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSPIZ, 0xfc0007fc00000000, 0xf000026400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSQRTEDP, 0xfc0007fc00000000, 0xf000032800000000, 0x1f000000000000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVRSQRTESP, 0xfc0007fc00000000, 0xf000022800000000, 0x1f000000000000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVSQRTDP, 0xfc0007fc00000000, 0xf000032c00000000, 0x1f000000000000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVSQRTSP, 0xfc0007fc00000000, 0xf000022c00000000, 0x1f000000000000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+       {XVSUBDP, 0xfc0007f800000000, 0xf000034000000000, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVSUBSP, 0xfc0007f800000000, 0xf000024000000000, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVTDIVDP, 0xfc0007f800000000, 0xf00003e800000000, 0x60000100000000, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVTDIVSP, 0xfc0007f800000000, 0xf00002e800000000, 0x60000100000000, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XVTSQRTDP, 0xfc0007fc00000000, 0xf00003a800000000, 0x7f000100000000, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
+       {XVTSQRTSP, 0xfc0007fc00000000, 0xf00002a800000000, 0x7f000100000000, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB)
+               [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
+       {XXLAND, 0xfc0007f800000000, 0xf000041000000000, 0x0, // VSX Vector Logical AND XX3-form (xxland XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLANDC, 0xfc0007f800000000, 0xf000045000000000, 0x0, // VSX Vector Logical AND with Complement XX3-form (xxlandc XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLNOR, 0xfc0007f800000000, 0xf000051000000000, 0x0, // VSX Vector Logical NOR XX3-form (xxlnor XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLOR, 0xfc0007f800000000, 0xf000049000000000, 0x0, // VSX Vector Logical OR XX3-form (xxlor XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXLXOR, 0xfc0007f800000000, 0xf00004d000000000, 0x0, // VSX Vector Logical XOR XX3-form (xxlxor XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXMRGHW, 0xfc0007f800000000, 0xf000009000000000, 0x0, // VSX Vector Merge High Word XX3-form (xxmrghw XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXMRGLW, 0xfc0007f800000000, 0xf000019000000000, 0x0, // VSX Vector Merge Low Word XX3-form (xxmrglw XT,XA,XB)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
+       {XXPERMDI, 0xfc0004f800000000, 0xf000005000000000, 0x0, // VSX Vector Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
+       {XXSEL, 0xfc00003000000000, 0xf000003000000000, 0x0, // VSX Vector Select XX4-form (xxsel XT,XA,XB,XC)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}},
+       {XXSLDWI, 0xfc0004f800000000, 0xf000001000000000, 0x0, // VSX Vector Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
+       {XXSPLTW, 0xfc0007fc00000000, 0xf000029000000000, 0x1c000000000000, // VSX Vector Splat Word XX2-form (xxspltw XT,XB,UIM)
+               [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}},
+       {CMPB, 0xfc0007fe00000000, 0x7c0003f800000000, 0x100000000, // Compare Bytes X-form (cmpb RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {DADD, 0xfc0007ff00000000, 0xec00000400000000, 0x0, // DFP Add X-form (dadd FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DADDCC, 0xfc0007ff00000000, 0xec00000500000000, 0x0, // DFP Add X-form (dadd. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DADDQ, 0xfc0007ff00000000, 0xfc00000400000000, 0x0, // DFP Add Quad X-form (daddq FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DADDQCC, 0xfc0007ff00000000, 0xfc00000500000000, 0x0, // DFP Add Quad X-form (daddq. FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DCFFIXQ, 0xfc0007ff00000000, 0xfc00064400000000, 0x1f000000000000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCFFIXQCC, 0xfc0007ff00000000, 0xfc00064500000000, 0x1f000000000000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCMPO, 0xfc0007fe00000000, 0xec00010400000000, 0x60000100000000, // DFP Compare Ordered X-form (dcmpo BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DCMPOQ, 0xfc0007fe00000000, 0xfc00010400000000, 0x60000100000000, // DFP Compare Ordered Quad X-form (dcmpoq BF,FRAp,FRBp)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DCMPU, 0xfc0007fe00000000, 0xec00050400000000, 0x60000100000000, // DFP Compare Unordered X-form (dcmpu BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DCMPUQ, 0xfc0007fe00000000, 0xfc00050400000000, 0x60000100000000, // DFP Compare Unordered Quad X-form (dcmpuq BF,FRAp,FRBp)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DCTDP, 0xfc0007ff00000000, 0xec00020400000000, 0x1f000000000000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTDPCC, 0xfc0007ff00000000, 0xec00020500000000, 0x1f000000000000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTFIX, 0xfc0007ff00000000, 0xec00024400000000, 0x1f000000000000, // DFP Convert To Fixed X-form (dctfix FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTFIXCC, 0xfc0007ff00000000, 0xec00024500000000, 0x1f000000000000, // DFP Convert To Fixed X-form (dctfix. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTFIXQ, 0xfc0007ff00000000, 0xfc00024400000000, 0x1f000000000000, // DFP Convert To Fixed Quad X-form (dctfixq FRT,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTFIXQCC, 0xfc0007ff00000000, 0xfc00024500000000, 0x1f000000000000, // DFP Convert To Fixed Quad X-form (dctfixq. FRT,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTQPQ, 0xfc0007ff00000000, 0xfc00020400000000, 0x1f000000000000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DCTQPQCC, 0xfc0007ff00000000, 0xfc00020500000000, 0x1f000000000000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DDEDPD, 0xfc0007ff00000000, 0xec00028400000000, 0x7000000000000, // DFP Decode DPD To BCD X-form (ddedpd SP,FRT,FRB)
+               [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DDEDPDCC, 0xfc0007ff00000000, 0xec00028500000000, 0x7000000000000, // DFP Decode DPD To BCD X-form (ddedpd. SP,FRT,FRB)
+               [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DDEDPDQ, 0xfc0007ff00000000, 0xfc00028400000000, 0x7000000000000, // DFP Decode DPD To BCD Quad X-form (ddedpdq SP,FRTp,FRBp)
+               [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DDEDPDQCC, 0xfc0007ff00000000, 0xfc00028500000000, 0x7000000000000, // DFP Decode DPD To BCD Quad X-form (ddedpdq. SP,FRTp,FRBp)
+               [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DDIV, 0xfc0007ff00000000, 0xec00044400000000, 0x0, // DFP Divide X-form (ddiv FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DDIVCC, 0xfc0007ff00000000, 0xec00044500000000, 0x0, // DFP Divide X-form (ddiv. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DDIVQ, 0xfc0007ff00000000, 0xfc00044400000000, 0x0, // DFP Divide Quad X-form (ddivq FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DDIVQCC, 0xfc0007ff00000000, 0xfc00044500000000, 0x0, // DFP Divide Quad X-form (ddivq. FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DENBCD, 0xfc0007ff00000000, 0xec00068400000000, 0xf000000000000, // DFP Encode BCD To DPD X-form (denbcd S,FRT,FRB)
+               [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DENBCDCC, 0xfc0007ff00000000, 0xec00068500000000, 0xf000000000000, // DFP Encode BCD To DPD X-form (denbcd. S,FRT,FRB)
+               [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DENBCDQ, 0xfc0007ff00000000, 0xfc00068400000000, 0xf000000000000, // DFP Encode BCD To DPD Quad X-form (denbcdq S,FRTp,FRBp)
+               [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DENBCDQCC, 0xfc0007ff00000000, 0xfc00068500000000, 0xf000000000000, // DFP Encode BCD To DPD Quad X-form (denbcdq. S,FRTp,FRBp)
+               [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DIEX, 0xfc0007ff00000000, 0xec0006c400000000, 0x0, // DFP Insert Biased Exponent X-form (diex FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DIEXCC, 0xfc0007ff00000000, 0xec0006c500000000, 0x0, // DFP Insert Biased Exponent X-form (diex. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DIEXQCC, 0xfc0007ff00000000, 0xfc0006c500000000, 0x0, // DFP Insert Biased Exponent Quad X-form (diexq. FRTp,FRA,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DIEXQ, 0xfc0007fe00000000, 0xfc0006c400000000, 0x0, // DFP Insert Biased Exponent Quad X-form (diexq FRTp,FRA,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DMUL, 0xfc0007ff00000000, 0xec00004400000000, 0x0, // DFP Multiply X-form (dmul FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DMULCC, 0xfc0007ff00000000, 0xec00004500000000, 0x0, // DFP Multiply X-form (dmul. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DMULQ, 0xfc0007ff00000000, 0xfc00004400000000, 0x0, // DFP Multiply Quad X-form (dmulq FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DMULQCC, 0xfc0007ff00000000, 0xfc00004500000000, 0x0, // DFP Multiply Quad X-form (dmulq. FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DQUA, 0xfc0001ff00000000, 0xec00000600000000, 0x0, // DFP Quantize Z23-form (dqua FRT,FRA,FRB,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUACC, 0xfc0001ff00000000, 0xec00000700000000, 0x0, // DFP Quantize Z23-form (dqua. FRT,FRA,FRB,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUAI, 0xfc0001ff00000000, 0xec00008600000000, 0x0, // DFP Quantize Immediate Z23-form (dquai TE,FRT,FRB,RMC)
+               [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUAICC, 0xfc0001ff00000000, 0xec00008700000000, 0x0, // DFP Quantize Immediate Z23-form (dquai. TE,FRT,FRB,RMC)
+               [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUAIQ, 0xfc0001ff00000000, 0xfc00008600000000, 0x0, // DFP Quantize Immediate Quad Z23-form (dquaiq TE,FRTp,FRBp,RMC)
+               [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUAIQCC, 0xfc0001ff00000000, 0xfc00008700000000, 0x0, // DFP Quantize Immediate Quad Z23-form (dquaiq. TE,FRTp,FRBp,RMC)
+               [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUAQ, 0xfc0001ff00000000, 0xfc00000600000000, 0x0, // DFP Quantize Quad Z23-form (dquaq FRTp,FRAp,FRBp,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DQUAQCC, 0xfc0001ff00000000, 0xfc00000700000000, 0x0, // DFP Quantize Quad Z23-form (dquaq. FRTp,FRAp,FRBp,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRDPQ, 0xfc0007ff00000000, 0xfc00060400000000, 0x1f000000000000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DRDPQCC, 0xfc0007ff00000000, 0xfc00060500000000, 0x1f000000000000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DRINTN, 0xfc0001ff00000000, 0xec0001c600000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Z23-form (drintn R,FRT,FRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTNCC, 0xfc0001ff00000000, 0xec0001c700000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Z23-form (drintn. R,FRT,FRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTNQ, 0xfc0001ff00000000, 0xfc0001c600000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Quad Z23-form (drintnq R,FRTp,FRBp,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTNQCC, 0xfc0001ff00000000, 0xfc0001c700000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Quad Z23-form (drintnq. R,FRTp,FRBp,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTX, 0xfc0001ff00000000, 0xec0000c600000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Z23-form (drintx R,FRT,FRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTXCC, 0xfc0001ff00000000, 0xec0000c700000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Z23-form (drintx. R,FRT,FRB,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTXQ, 0xfc0001ff00000000, 0xfc0000c600000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Quad Z23-form (drintxq R,FRTp,FRBp,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRINTXQCC, 0xfc0001ff00000000, 0xfc0000c700000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Quad Z23-form (drintxq. R,FRTp,FRBp,RMC)
+               [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRRND, 0xfc0001ff00000000, 0xec00004600000000, 0x0, // DFP Reround Z23-form (drrnd FRT,FRA,FRB,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRRNDCC, 0xfc0001ff00000000, 0xec00004700000000, 0x0, // DFP Reround Z23-form (drrnd. FRT,FRA,FRB,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRRNDQ, 0xfc0001ff00000000, 0xfc00004600000000, 0x0, // DFP Reround Quad Z23-form (drrndq FRTp,FRA,FRBp,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRRNDQCC, 0xfc0001ff00000000, 0xfc00004700000000, 0x0, // DFP Reround Quad Z23-form (drrndq. FRTp,FRA,FRBp,RMC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+       {DRSP, 0xfc0007ff00000000, 0xec00060400000000, 0x1f000000000000, // DFP Round To DFP Short X-form (drsp FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DRSPCC, 0xfc0007ff00000000, 0xec00060500000000, 0x1f000000000000, // DFP Round To DFP Short X-form (drsp. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DSCLI, 0xfc0003ff00000000, 0xec00008400000000, 0x0, // DFP Shift Significand Left Immediate Z22-form (dscli FRT,FRA,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCLICC, 0xfc0003ff00000000, 0xec00008500000000, 0x0, // DFP Shift Significand Left Immediate Z22-form (dscli. FRT,FRA,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCLIQ, 0xfc0003ff00000000, 0xfc00008400000000, 0x0, // DFP Shift Significand Left Immediate Quad Z22-form (dscliq FRTp,FRAp,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCLIQCC, 0xfc0003ff00000000, 0xfc00008500000000, 0x0, // DFP Shift Significand Left Immediate Quad Z22-form (dscliq. FRTp,FRAp,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCRI, 0xfc0003ff00000000, 0xec0000c400000000, 0x0, // DFP Shift Significand Right Immediate Z22-form (dscri FRT,FRA,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCRICC, 0xfc0003ff00000000, 0xec0000c500000000, 0x0, // DFP Shift Significand Right Immediate Z22-form (dscri. FRT,FRA,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCRIQ, 0xfc0003ff00000000, 0xfc0000c400000000, 0x0, // DFP Shift Significand Right Immediate Quad Z22-form (dscriq FRTp,FRAp,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSCRIQCC, 0xfc0003ff00000000, 0xfc0000c500000000, 0x0, // DFP Shift Significand Right Immediate Quad Z22-form (dscriq. FRTp,FRAp,SH)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DSUB, 0xfc0007ff00000000, 0xec00040400000000, 0x0, // DFP Subtract X-form (dsub FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DSUBCC, 0xfc0007ff00000000, 0xec00040500000000, 0x0, // DFP Subtract X-form (dsub. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DSUBQ, 0xfc0007ff00000000, 0xfc00040400000000, 0x0, // DFP Subtract Quad X-form (dsubq FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DSUBQCC, 0xfc0007ff00000000, 0xfc00040500000000, 0x0, // DFP Subtract Quad X-form (dsubq. FRTp,FRAp,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DTSTDC, 0xfc0003fe00000000, 0xec00018400000000, 0x60000100000000, // DFP Test Data Class Z22-form (dtstdc BF,FRA,DCM)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DTSTDCQ, 0xfc0003fe00000000, 0xfc00018400000000, 0x60000100000000, // DFP Test Data Class Quad Z22-form (dtstdcq BF,FRAp,DCM)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DTSTDG, 0xfc0003fe00000000, 0xec0001c400000000, 0x60000100000000, // DFP Test Data Group Z22-form (dtstdg BF,FRA,DGM)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DTSTDGQ, 0xfc0003fe00000000, 0xfc0001c400000000, 0x60000100000000, // DFP Test Data Group Quad Z22-form (dtstdgq BF,FRAp,DGM)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+       {DTSTEX, 0xfc0007fe00000000, 0xec00014400000000, 0x60000100000000, // DFP Test Exponent X-form (dtstex BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DTSTEXQ, 0xfc0007fe00000000, 0xfc00014400000000, 0x60000100000000, // DFP Test Exponent Quad X-form (dtstexq BF,FRAp,FRBp)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DTSTSF, 0xfc0007fe00000000, 0xec00054400000000, 0x60000100000000, // DFP Test Significance X-form (dtstsf BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DTSTSFQ, 0xfc0007fe00000000, 0xfc00054400000000, 0x60000100000000, // DFP Test Significance Quad X-form (dtstsfq BF,FRA,FRBp)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {DXEX, 0xfc0007ff00000000, 0xec0002c400000000, 0x1f000000000000, // DFP Extract Biased Exponent X-form (dxex FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DXEXCC, 0xfc0007ff00000000, 0xec0002c500000000, 0x1f000000000000, // DFP Extract Biased Exponent X-form (dxex. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DXEXQ, 0xfc0007ff00000000, 0xfc0002c400000000, 0x1f000000000000, // DFP Extract Biased Exponent Quad X-form (dxexq FRT,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {DXEXQCC, 0xfc0007ff00000000, 0xfc0002c500000000, 0x1f000000000000, // DFP Extract Biased Exponent Quad X-form (dxexq. FRT,FRBp)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCPSGN, 0xfc0007ff00000000, 0xfc00001000000000, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FCPSGNCC, 0xfc0007ff00000000, 0xfc00001100000000, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {LBZCIX, 0xfc0007fe00000000, 0x7c0006aa00000000, 0x100000000, // Load Byte & Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LDCIX, 0xfc0007fe00000000, 0x7c0006ea00000000, 0x100000000, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFDP, 0xfc00000300000000, 0xe400000000000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {LFDPX, 0xfc0007fe00000000, 0x7c00062e00000000, 0x100000000, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFIWAX, 0xfc0007fe00000000, 0x7c0006ae00000000, 0x100000000, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHZCIX, 0xfc0007fe00000000, 0x7c00066a00000000, 0x100000000, // Load Halfword & Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LWZCIX, 0xfc0007fe00000000, 0x7c00062a00000000, 0x100000000, // Load Word & Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {PRTYD, 0xfc0007fe00000000, 0x7c00017400000000, 0xf80100000000, // Parity Doubleword X-form (prtyd RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {PRTYW, 0xfc0007fe00000000, 0x7c00013400000000, 0xf80100000000, // Parity Word X-form (prtyw RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {SLBFEECC, 0xfc0007ff00000000, 0x7c0007a700000000, 0x1f000000000000, // SLB Find Entry ESID X-form (slbfee. RT,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+       {STBCIX, 0xfc0007fe00000000, 0x7c0007aa00000000, 0x100000000, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STDCIX, 0xfc0007fe00000000, 0x7c0007ea00000000, 0x100000000, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STFDP, 0xfc00000300000000, 0xf400000000000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {STFDPX, 0xfc0007fe00000000, 0x7c00072e00000000, 0x100000000, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STHCIX, 0xfc0007fe00000000, 0x7c00076a00000000, 0x100000000, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STWCIX, 0xfc0007fe00000000, 0x7c00072a00000000, 0x100000000, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ISEL, 0xfc00003e00000000, 0x7c00001e00000000, 0x100000000, // Integer Select A-form (isel RT,RA,RB,BC)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
+       {LVEBX, 0xfc0007fe00000000, 0x7c00000e00000000, 0x100000000, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LVEHX, 0xfc0007fe00000000, 0x7c00004e00000000, 0x100000000, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LVEWX, 0xfc0007fe00000000, 0x7c00008e00000000, 0x100000000, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LVSL, 0xfc0007fe00000000, 0x7c00000c00000000, 0x100000000, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LVSR, 0xfc0007fe00000000, 0x7c00004c00000000, 0x100000000, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LVX, 0xfc0007fe00000000, 0x7c0000ce00000000, 0x100000000, // Load Vector Indexed X-form (lvx VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LVXL, 0xfc0007fe00000000, 0x7c0002ce00000000, 0x100000000, // Load Vector Indexed Last X-form (lvxl VRT,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MFVSCR, 0xfc0007ff00000000, 0x1000060400000000, 0x1ff80000000000, // Move From Vector Status and Control Register VX-form (mfvscr VRT)
+               [6]*argField{ap_VecReg_6_10}},
+       {MTVSCR, 0xfc0007ff00000000, 0x1000064400000000, 0x3ff000000000000, // Move To Vector Status and Control Register VX-form (mtvscr VRB)
+               [6]*argField{ap_VecReg_16_20}},
+       {STVEBX, 0xfc0007fe00000000, 0x7c00010e00000000, 0x100000000, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STVEHX, 0xfc0007fe00000000, 0x7c00014e00000000, 0x100000000, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STVEWX, 0xfc0007fe00000000, 0x7c00018e00000000, 0x100000000, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STVX, 0xfc0007fe00000000, 0x7c0001ce00000000, 0x100000000, // Store Vector Indexed X-form (stvx VRS,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STVXL, 0xfc0007fe00000000, 0x7c0003ce00000000, 0x100000000, // Store Vector Indexed Last X-form (stvxl VRS,RA,RB)
+               [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {TLBIEL, 0xfc0007fe00000000, 0x7c00022400000000, 0x10000100000000, // TLB Invalidate Entry Local X-form (tlbiel RB,RS,RIC,PRS,R)
+               [6]*argField{ap_Reg_16_20, ap_Reg_6_10, ap_ImmUnsigned_12_13, ap_ImmUnsigned_14_14, ap_ImmUnsigned_15_15}},
+       {VADDCUW, 0xfc0007ff00000000, 0x1000018000000000, 0x0, // Vector Add & write Carry Unsigned Word VX-form (vaddcuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDFP, 0xfc0007ff00000000, 0x1000000a00000000, 0x0, // Vector Add Floating-Point VX-form (vaddfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDSBS, 0xfc0007ff00000000, 0x1000030000000000, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDSHS, 0xfc0007ff00000000, 0x1000034000000000, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDSWS, 0xfc0007ff00000000, 0x1000038000000000, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUBM, 0xfc0007ff00000000, 0x1000000000000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUBS, 0xfc0007ff00000000, 0x1000020000000000, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUHM, 0xfc0007ff00000000, 0x1000004000000000, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUHS, 0xfc0007ff00000000, 0x1000024000000000, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUWM, 0xfc0007ff00000000, 0x1000008000000000, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VADDUWS, 0xfc0007ff00000000, 0x1000028000000000, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAND, 0xfc0007ff00000000, 0x1000040400000000, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VANDC, 0xfc0007ff00000000, 0x1000044400000000, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAVGSB, 0xfc0007ff00000000, 0x1000050200000000, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAVGSH, 0xfc0007ff00000000, 0x1000054200000000, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAVGSW, 0xfc0007ff00000000, 0x1000058200000000, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAVGUB, 0xfc0007ff00000000, 0x1000040200000000, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAVGUH, 0xfc0007ff00000000, 0x1000044200000000, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VAVGUW, 0xfc0007ff00000000, 0x1000048200000000, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCFSX, 0xfc0007ff00000000, 0x1000034a00000000, 0x0, // Vector Convert with round to nearest From Signed Word to floating-point format VX-form (vcfsx VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {VCFUX, 0xfc0007ff00000000, 0x1000030a00000000, 0x0, // Vector Convert with round to nearest From Unsigned Word to floating-point format VX-form (vcfux VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {VCMPBFP, 0xfc0007ff00000000, 0x100003c600000000, 0x0, // Vector Compare Bounds Floating-Point VC-form (vcmpbfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPBFPCC, 0xfc0007ff00000000, 0x100007c600000000, 0x0, // Vector Compare Bounds Floating-Point VC-form (vcmpbfp. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQFP, 0xfc0007ff00000000, 0x100000c600000000, 0x0, // Vector Compare Equal Floating-Point VC-form (vcmpeqfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQFPCC, 0xfc0007ff00000000, 0x100004c600000000, 0x0, // Vector Compare Equal Floating-Point VC-form (vcmpeqfp. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUB, 0xfc0007ff00000000, 0x1000000600000000, 0x0, // Vector Compare Equal Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUBCC, 0xfc0007ff00000000, 0x1000040600000000, 0x0, // Vector Compare Equal Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUH, 0xfc0007ff00000000, 0x1000004600000000, 0x0, // Vector Compare Equal Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUHCC, 0xfc0007ff00000000, 0x1000044600000000, 0x0, // Vector Compare Equal Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUW, 0xfc0007ff00000000, 0x1000008600000000, 0x0, // Vector Compare Equal Unsigned Word VC-form (vcmpequw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPEQUWCC, 0xfc0007ff00000000, 0x1000048600000000, 0x0, // Vector Compare Equal Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGEFP, 0xfc0007ff00000000, 0x100001c600000000, 0x0, // Vector Compare Greater Than or Equal Floating-Point VC-form (vcmpgefp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGEFPCC, 0xfc0007ff00000000, 0x100005c600000000, 0x0, // Vector Compare Greater Than or Equal Floating-Point VC-form (vcmpgefp. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTFP, 0xfc0007ff00000000, 0x100002c600000000, 0x0, // Vector Compare Greater Than Floating-Point VC-form (vcmpgtfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTFPCC, 0xfc0007ff00000000, 0x100006c600000000, 0x0, // Vector Compare Greater Than Floating-Point VC-form (vcmpgtfp. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSB, 0xfc0007ff00000000, 0x1000030600000000, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSBCC, 0xfc0007ff00000000, 0x1000070600000000, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSH, 0xfc0007ff00000000, 0x1000034600000000, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSHCC, 0xfc0007ff00000000, 0x1000074600000000, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSW, 0xfc0007ff00000000, 0x1000038600000000, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTSWCC, 0xfc0007ff00000000, 0x1000078600000000, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUB, 0xfc0007ff00000000, 0x1000020600000000, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUBCC, 0xfc0007ff00000000, 0x1000060600000000, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUH, 0xfc0007ff00000000, 0x1000024600000000, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUHCC, 0xfc0007ff00000000, 0x1000064600000000, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUW, 0xfc0007ff00000000, 0x1000028600000000, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCMPGTUWCC, 0xfc0007ff00000000, 0x1000068600000000, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VCTSXS, 0xfc0007ff00000000, 0x100003ca00000000, 0x0, // Vector Convert with round to zero from floating-point To Signed Word format Saturate VX-form (vctsxs VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {VCTUXS, 0xfc0007ff00000000, 0x1000038a00000000, 0x0, // Vector Convert with round to zero from floating-point To Unsigned Word format Saturate VX-form (vctuxs VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+       {VEXPTEFP, 0xfc0007ff00000000, 0x1000018a00000000, 0x1f000000000000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VLOGEFP, 0xfc0007ff00000000, 0x100001ca00000000, 0x1f000000000000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VMADDFP, 0xfc00003f00000000, 0x1000002e00000000, 0x0, // Vector Multiply-Add Floating-Point VA-form (vmaddfp VRT,VRA,VRC,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
+       {VMAXFP, 0xfc0007ff00000000, 0x1000040a00000000, 0x0, // Vector Maximum Floating-Point VX-form (vmaxfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXSB, 0xfc0007ff00000000, 0x1000010200000000, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXSH, 0xfc0007ff00000000, 0x1000014200000000, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXSW, 0xfc0007ff00000000, 0x1000018200000000, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXUB, 0xfc0007ff00000000, 0x1000000200000000, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXUH, 0xfc0007ff00000000, 0x1000004200000000, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMAXUW, 0xfc0007ff00000000, 0x1000008200000000, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMHADDSHS, 0xfc00003f00000000, 0x1000002000000000, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMHRADDSHS, 0xfc00003f00000000, 0x1000002100000000, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMINFP, 0xfc0007ff00000000, 0x1000044a00000000, 0x0, // Vector Minimum Floating-Point VX-form (vminfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINSB, 0xfc0007ff00000000, 0x1000030200000000, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINSH, 0xfc0007ff00000000, 0x1000034200000000, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINSW, 0xfc0007ff00000000, 0x1000038200000000, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINUB, 0xfc0007ff00000000, 0x1000020200000000, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINUH, 0xfc0007ff00000000, 0x1000024200000000, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMINUW, 0xfc0007ff00000000, 0x1000028200000000, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMLADDUHM, 0xfc00003f00000000, 0x1000002200000000, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMRGHB, 0xfc0007ff00000000, 0x1000000c00000000, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGHH, 0xfc0007ff00000000, 0x1000004c00000000, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGHW, 0xfc0007ff00000000, 0x1000008c00000000, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGLB, 0xfc0007ff00000000, 0x1000010c00000000, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGLH, 0xfc0007ff00000000, 0x1000014c00000000, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMRGLW, 0xfc0007ff00000000, 0x1000018c00000000, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMSUMMBM, 0xfc00003f00000000, 0x1000002500000000, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMSUMSHM, 0xfc00003f00000000, 0x1000002800000000, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMSUMSHS, 0xfc00003f00000000, 0x1000002900000000, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMSUMUBM, 0xfc00003f00000000, 0x1000002400000000, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMSUMUHM, 0xfc00003f00000000, 0x1000002600000000, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMSUMUHS, 0xfc00003f00000000, 0x1000002700000000, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VMULESB, 0xfc0007ff00000000, 0x1000030800000000, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULESH, 0xfc0007ff00000000, 0x1000034800000000, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULEUB, 0xfc0007ff00000000, 0x1000020800000000, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULEUH, 0xfc0007ff00000000, 0x1000024800000000, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOSB, 0xfc0007ff00000000, 0x1000010800000000, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOSH, 0xfc0007ff00000000, 0x1000014800000000, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOUB, 0xfc0007ff00000000, 0x1000000800000000, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VMULOUH, 0xfc0007ff00000000, 0x1000004800000000, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VNMSUBFP, 0xfc00003f00000000, 0x1000002f00000000, 0x0, // Vector Negative Multiply-Subtract Floating-Point VA-form (vnmsubfp VRT,VRA,VRC,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
+       {VNOR, 0xfc0007ff00000000, 0x1000050400000000, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VOR, 0xfc0007ff00000000, 0x1000048400000000, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPERM, 0xfc00003f00000000, 0x1000002b00000000, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VPKPX, 0xfc0007ff00000000, 0x1000030e00000000, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKSHSS, 0xfc0007ff00000000, 0x1000018e00000000, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKSHUS, 0xfc0007ff00000000, 0x1000010e00000000, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKSWSS, 0xfc0007ff00000000, 0x100001ce00000000, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKSWUS, 0xfc0007ff00000000, 0x1000014e00000000, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKUHUM, 0xfc0007ff00000000, 0x1000000e00000000, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKUHUS, 0xfc0007ff00000000, 0x1000008e00000000, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKUWUM, 0xfc0007ff00000000, 0x1000004e00000000, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VPKUWUS, 0xfc0007ff00000000, 0x100000ce00000000, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VREFP, 0xfc0007ff00000000, 0x1000010a00000000, 0x1f000000000000, // Vector Reciprocal Estimate Floating-Point VX-form (vrefp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRFIM, 0xfc0007ff00000000, 0x100002ca00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward -Infinity VX-form (vrfim VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRFIN, 0xfc0007ff00000000, 0x1000020a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer Nearest VX-form (vrfin VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRFIP, 0xfc0007ff00000000, 0x1000028a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward +Infinity VX-form (vrfip VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRFIZ, 0xfc0007ff00000000, 0x1000024a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward Zero VX-form (vrfiz VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VRLB, 0xfc0007ff00000000, 0x1000000400000000, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLH, 0xfc0007ff00000000, 0x1000004400000000, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRLW, 0xfc0007ff00000000, 0x1000008400000000, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VRSQRTEFP, 0xfc0007ff00000000, 0x1000014a00000000, 0x1f000000000000, // Vector Reciprocal Square Root Estimate Floating-Point VX-form (vrsqrtefp VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VSEL, 0xfc00003f00000000, 0x1000002a00000000, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+       {VSL, 0xfc0007ff00000000, 0x100001c400000000, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSLB, 0xfc0007ff00000000, 0x1000010400000000, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSLDOI, 0xfc00003f00000000, 0x1000002c00000000, 0x40000000000, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}},
+       {VSLH, 0xfc0007ff00000000, 0x1000014400000000, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSLO, 0xfc0007ff00000000, 0x1000040c00000000, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSLW, 0xfc0007ff00000000, 0x1000018400000000, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSPLTB, 0xfc0007ff00000000, 0x1000020c00000000, 0x10000000000000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+       {VSPLTH, 0xfc0007ff00000000, 0x1000024c00000000, 0x18000000000000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
+       {VSPLTISB, 0xfc0007ff00000000, 0x1000030c00000000, 0xf80000000000, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM)
+               [6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
+       {VSPLTISH, 0xfc0007ff00000000, 0x1000034c00000000, 0xf80000000000, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM)
+               [6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
+       {VSPLTISW, 0xfc0007ff00000000, 0x1000038c00000000, 0xf80000000000, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM)
+               [6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
+       {VSPLTW, 0xfc0007ff00000000, 0x1000028c00000000, 0x1c000000000000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}},
+       {VSR, 0xfc0007ff00000000, 0x100002c400000000, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRAB, 0xfc0007ff00000000, 0x1000030400000000, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRAH, 0xfc0007ff00000000, 0x1000034400000000, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRAW, 0xfc0007ff00000000, 0x1000038400000000, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRB, 0xfc0007ff00000000, 0x1000020400000000, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRH, 0xfc0007ff00000000, 0x1000024400000000, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRO, 0xfc0007ff00000000, 0x1000044c00000000, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSRW, 0xfc0007ff00000000, 0x1000028400000000, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBCUW, 0xfc0007ff00000000, 0x1000058000000000, 0x0, // Vector Subtract & Write Carry-out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBFP, 0xfc0007ff00000000, 0x1000004a00000000, 0x0, // Vector Subtract Floating-Point VX-form (vsubfp VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBSBS, 0xfc0007ff00000000, 0x1000070000000000, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBSHS, 0xfc0007ff00000000, 0x1000074000000000, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBSWS, 0xfc0007ff00000000, 0x1000078000000000, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUBM, 0xfc0007ff00000000, 0x1000040000000000, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUBS, 0xfc0007ff00000000, 0x1000060000000000, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUHM, 0xfc0007ff00000000, 0x1000044000000000, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUHS, 0xfc0007ff00000000, 0x1000064000000000, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUWM, 0xfc0007ff00000000, 0x1000048000000000, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUBUWS, 0xfc0007ff00000000, 0x1000068000000000, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUM2SWS, 0xfc0007ff00000000, 0x1000068800000000, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUM4SBS, 0xfc0007ff00000000, 0x1000070800000000, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUM4SHS, 0xfc0007ff00000000, 0x1000064800000000, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUM4UBS, 0xfc0007ff00000000, 0x1000060800000000, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VSUMSWS, 0xfc0007ff00000000, 0x1000078800000000, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {VUPKHPX, 0xfc0007ff00000000, 0x1000034e00000000, 0x1f000000000000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VUPKHSB, 0xfc0007ff00000000, 0x1000020e00000000, 0x1f000000000000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VUPKHSH, 0xfc0007ff00000000, 0x1000024e00000000, 0x1f000000000000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VUPKLPX, 0xfc0007ff00000000, 0x100003ce00000000, 0x1f000000000000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VUPKLSB, 0xfc0007ff00000000, 0x1000028e00000000, 0x1f000000000000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VUPKLSH, 0xfc0007ff00000000, 0x100002ce00000000, 0x1f000000000000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+       {VXOR, 0xfc0007ff00000000, 0x100004c400000000, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB)
+               [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+       {FRE, 0xfc00003f00000000, 0xfc00003000000000, 0x1f07c000000000, // Floating Reciprocal Estimate A-form (fre FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRECC, 0xfc00003f00000000, 0xfc00003100000000, 0x1f07c000000000, // Floating Reciprocal Estimate A-form (fre. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIM, 0xfc0007ff00000000, 0xfc0003d000000000, 0x1f000000000000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIMCC, 0xfc0007ff00000000, 0xfc0003d100000000, 0x1f000000000000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIN, 0xfc0007ff00000000, 0xfc00031000000000, 0x1f000000000000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRINCC, 0xfc0007ff00000000, 0xfc00031100000000, 0x1f000000000000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIP, 0xfc0007ff00000000, 0xfc00039000000000, 0x1f000000000000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIPCC, 0xfc0007ff00000000, 0xfc00039100000000, 0x1f000000000000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIZ, 0xfc0007ff00000000, 0xfc00035000000000, 0x1f000000000000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRIZCC, 0xfc0007ff00000000, 0xfc00035100000000, 0x1f000000000000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRSQRTES, 0xfc00003f00000000, 0xec00003400000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRSQRTESCC, 0xfc00003f00000000, 0xec00003500000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {HRFID, 0xfc0007fe00000000, 0x4c00022400000000, 0x3fff80100000000, // Return From Interrupt Doubleword Hypervisor XL-form (hrfid)
+               [6]*argField{}},
+       {POPCNTB, 0xfc0007fe00000000, 0x7c0000f400000000, 0xf80100000000, // Population Count Bytes X-form (popcntb RA, RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {MFOCRF, 0xfc1007fe00000000, 0x7c10002600000000, 0x80100000000, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM)
+               [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
+       {MTOCRF, 0xfc1007fe00000000, 0x7c10012000000000, 0x80100000000, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS)
+               [6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
+       {SLBMFEE, 0xfc0007fe00000000, 0x7c00072600000000, 0x1e000100000000, // SLB Move From Entry ESID X-form (slbmfee RT,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+       {SLBMFEV, 0xfc0007fe00000000, 0x7c0006a600000000, 0x1e000100000000, // SLB Move From Entry VSID X-form (slbmfev RT,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+       {SLBMTE, 0xfc0007fe00000000, 0x7c00032400000000, 0x1f000100000000, // SLB Move To Entry X-form (slbmte RS,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+       {RFSCV, 0xfc0007fe00000000, 0x4c0000a400000000, 0x3fff80100000000, // Return From System Call Vectored XL-form (rfscv)
+               [6]*argField{}},
+       {SCV, 0xfc00000300000000, 0x4400000100000000, 0x3fff01c00000000, // System Call Vectored SC-form (scv LEV)
+               [6]*argField{ap_ImmUnsigned_20_26}},
+       {LQ, 0xfc00000000000000, 0xe000000000000000, 0xf00000000, // Load Quadword DQ-form (lq RTp,DQ(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+       {STQ, 0xfc00000300000000, 0xf800000200000000, 0x0, // Store Quadword DS-form (stq RSp,DS(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {CNTLZD, 0xfc0007ff00000000, 0x7c00007400000000, 0xf80000000000, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CNTLZDCC, 0xfc0007ff00000000, 0x7c00007500000000, 0xf80000000000, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {DCBF, 0xfc0007fe00000000, 0x7c0000ac00000000, 0x300000100000000, // Data Cache Block Flush X-form (dcbf RA,RB,L)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_8_10}},
+       {DCBST, 0xfc0007fe00000000, 0x7c00006c00000000, 0x3e0000100000000, // Data Cache Block Store X-form (dcbst RA,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+       {DCBT, 0xfc0007fe00000000, 0x7c00022c00000000, 0x100000000, // Data Cache Block Touch X-form (dcbt RA,RB,TH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
+       {DCBTST, 0xfc0007fe00000000, 0x7c0001ec00000000, 0x100000000, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
+       {DIVD, 0xfc0007ff00000000, 0x7c0003d200000000, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDCC, 0xfc0007ff00000000, 0x7c0003d300000000, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDO, 0xfc0007ff00000000, 0x7c0007d200000000, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDOCC, 0xfc0007ff00000000, 0x7c0007d300000000, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDU, 0xfc0007ff00000000, 0x7c00039200000000, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDUCC, 0xfc0007ff00000000, 0x7c00039300000000, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDUO, 0xfc0007ff00000000, 0x7c00079200000000, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVDUOCC, 0xfc0007ff00000000, 0x7c00079300000000, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVW, 0xfc0007ff00000000, 0x7c0003d600000000, 0x0, // Divide Word XO-form (divw RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWCC, 0xfc0007ff00000000, 0x7c0003d700000000, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWO, 0xfc0007ff00000000, 0x7c0007d600000000, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWOCC, 0xfc0007ff00000000, 0x7c0007d700000000, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWU, 0xfc0007ff00000000, 0x7c00039600000000, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWUCC, 0xfc0007ff00000000, 0x7c00039700000000, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWUO, 0xfc0007ff00000000, 0x7c00079600000000, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {DIVWUOCC, 0xfc0007ff00000000, 0x7c00079700000000, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {EIEIO, 0xfc0007fe00000000, 0x7c0006ac00000000, 0x3fff80100000000, // Enforce In-order Execution of I/O X-form (eieio)
+               [6]*argField{}},
+       {EXTSB, 0xfc0007ff00000000, 0x7c00077400000000, 0xf80000000000, // Extend Sign Byte X-form (extsb RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {EXTSBCC, 0xfc0007ff00000000, 0x7c00077500000000, 0xf80000000000, // Extend Sign Byte X-form (extsb. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {EXTSW, 0xfc0007ff00000000, 0x7c0007b400000000, 0xf80000000000, // Extend Sign Word X-form (extsw RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {EXTSWCC, 0xfc0007ff00000000, 0x7c0007b500000000, 0xf80000000000, // Extend Sign Word X-form (extsw. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {FADDS, 0xfc00003f00000000, 0xec00002a00000000, 0x7c000000000, // Floating Add Single A-form (fadds FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FADDSCC, 0xfc00003f00000000, 0xec00002b00000000, 0x7c000000000, // Floating Add Single A-form (fadds. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FCFID, 0xfc0007ff00000000, 0xfc00069c00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCFIDCC, 0xfc0007ff00000000, 0xfc00069d00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTID, 0xfc0007ff00000000, 0xfc00065c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDCC, 0xfc0007ff00000000, 0xfc00065d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDZ, 0xfc0007ff00000000, 0xfc00065e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIDZCC, 0xfc0007ff00000000, 0xfc00065f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FDIVS, 0xfc00003f00000000, 0xec00002400000000, 0x7c000000000, // Floating Divide Single A-form (fdivs FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FDIVSCC, 0xfc00003f00000000, 0xec00002500000000, 0x7c000000000, // Floating Divide Single A-form (fdivs. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FMADDS, 0xfc00003f00000000, 0xec00003a00000000, 0x0, // Floating Multiply-Add Single A-form (fmadds FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMADDSCC, 0xfc00003f00000000, 0xec00003b00000000, 0x0, // Floating Multiply-Add Single A-form (fmadds. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMSUBS, 0xfc00003f00000000, 0xec00003800000000, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMSUBSCC, 0xfc00003f00000000, 0xec00003900000000, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMULS, 0xfc00003f00000000, 0xec00003200000000, 0xf80000000000, // Floating Multiply Single A-form (fmuls FRT,FRA,FRC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+       {FMULSCC, 0xfc00003f00000000, 0xec00003300000000, 0xf80000000000, // Floating Multiply Single A-form (fmuls. FRT,FRA,FRC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+       {FNMADDS, 0xfc00003f00000000, 0xec00003e00000000, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FNMADDSCC, 0xfc00003f00000000, 0xec00003f00000000, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FNMSUBS, 0xfc00003f00000000, 0xec00003c00000000, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FNMSUBSCC, 0xfc00003f00000000, 0xec00003d00000000, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FRES, 0xfc00003f00000000, 0xec00003000000000, 0x1f07c000000000, // Floating Reciprocal Estimate Single A-form (fres FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRESCC, 0xfc00003f00000000, 0xec00003100000000, 0x1f07c000000000, // Floating Reciprocal Estimate Single A-form (fres. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRSQRTE, 0xfc00003f00000000, 0xfc00003400000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate A-form (frsqrte FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRSQRTECC, 0xfc00003f00000000, 0xfc00003500000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate A-form (frsqrte. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FSEL, 0xfc00003f00000000, 0xfc00002e00000000, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FSELCC, 0xfc00003f00000000, 0xfc00002f00000000, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FSQRTS, 0xfc00003f00000000, 0xec00002c00000000, 0x1f07c000000000, // Floating Square Root Single A-form (fsqrts FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FSQRTSCC, 0xfc00003f00000000, 0xec00002d00000000, 0x1f07c000000000, // Floating Square Root Single A-form (fsqrts. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FSUBS, 0xfc00003f00000000, 0xec00002800000000, 0x7c000000000, // Floating Subtract Single A-form (fsubs FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FSUBSCC, 0xfc00003f00000000, 0xec00002900000000, 0x7c000000000, // Floating Subtract Single A-form (fsubs. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {ICBI, 0xfc0007fe00000000, 0x7c0007ac00000000, 0x3e0000100000000, // Instruction Cache Block Invalidate X-form (icbi RA,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+       {LD, 0xfc00000300000000, 0xe800000000000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {LDARX, 0xfc0007fe00000000, 0x7c0000a800000000, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+       {LDU, 0xfc00000300000000, 0xe800000100000000, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {LDUX, 0xfc0007fe00000000, 0x7c00006a00000000, 0x100000000, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LDX, 0xfc0007fe00000000, 0x7c00002a00000000, 0x100000000, // Load Doubleword Indexed X-form (ldx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LWA, 0xfc00000300000000, 0xe800000200000000, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {LWARX, 0xfc0007fe00000000, 0x7c00002800000000, 0x0, // Load Word & Reserve Indexed X-form (lwarx RT,RA,RB,EH)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+       {LWAUX, 0xfc0007fe00000000, 0x7c0002ea00000000, 0x100000000, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LWAX, 0xfc0007fe00000000, 0x7c0002aa00000000, 0x100000000, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MFTB, 0xfc0007fe00000000, 0x7c0002e600000000, 0x100000000, // Move From Time Base XFX-form (mftb RT,TBR)
+               [6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+       {MTMSRD, 0xfc0007fe00000000, 0x7c00016400000000, 0x1ef80100000000, // Move To MSR Doubleword X-form (mtmsrd RS,L)
+               [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
+       {MULHD, 0xfc0003ff00000000, 0x7c00009200000000, 0x40000000000, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHDCC, 0xfc0003ff00000000, 0x7c00009300000000, 0x40000000000, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHDU, 0xfc0003ff00000000, 0x7c00001200000000, 0x40000000000, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHDUCC, 0xfc0003ff00000000, 0x7c00001300000000, 0x40000000000, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHW, 0xfc0003ff00000000, 0x7c00009600000000, 0x40000000000, // Multiply High Word XO-form (mulhw RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHWCC, 0xfc0003ff00000000, 0x7c00009700000000, 0x40000000000, // Multiply High Word XO-form (mulhw. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHWU, 0xfc0003ff00000000, 0x7c00001600000000, 0x40000000000, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULHWUCC, 0xfc0003ff00000000, 0x7c00001700000000, 0x40000000000, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLD, 0xfc0007ff00000000, 0x7c0001d200000000, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLDCC, 0xfc0007ff00000000, 0x7c0001d300000000, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLDO, 0xfc0007ff00000000, 0x7c0005d200000000, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLDOCC, 0xfc0007ff00000000, 0x7c0005d300000000, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {RFID, 0xfc0007fe00000000, 0x4c00002400000000, 0x3fff80100000000, // Return from Interrupt Doubleword XL-form (rfid)
+               [6]*argField{}},
+       {RLDCL, 0xfc00001f00000000, 0x7800001000000000, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDCLCC, 0xfc00001f00000000, 0x7800001100000000, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDCR, 0xfc00001f00000000, 0x7800001200000000, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDCRCC, 0xfc00001f00000000, 0x7800001300000000, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDIC, 0xfc00001d00000000, 0x7800000800000000, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDICCC, 0xfc00001d00000000, 0x7800000900000000, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDICL, 0xfc00001d00000000, 0x7800000000000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDICLCC, 0xfc00001d00000000, 0x7800000100000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDICR, 0xfc00001d00000000, 0x7800000400000000, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDICRCC, 0xfc00001d00000000, 0x7800000500000000, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDIMI, 0xfc00001d00000000, 0x7800000c00000000, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {RLDIMICC, 0xfc00001d00000000, 0x7800000d00000000, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+       {SC, 0xfc00000200000000, 0x4400000200000000, 0x3fff01d00000000, // System Call SC-form (sc LEV)
+               [6]*argField{ap_ImmUnsigned_20_26}},
+       {SLBIA, 0xfc0007fe00000000, 0x7c0003e400000000, 0x31ff80100000000, // SLB Invalidate All X-form (slbia IH)
+               [6]*argField{ap_ImmUnsigned_8_10}},
+       {SLBIE, 0xfc0007fe00000000, 0x7c00036400000000, 0x3ff000100000000, // SLB Invalidate Entry X-form (slbie RB)
+               [6]*argField{ap_Reg_16_20}},
+       {SLD, 0xfc0007ff00000000, 0x7c00003600000000, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SLDCC, 0xfc0007ff00000000, 0x7c00003700000000, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRAD, 0xfc0007ff00000000, 0x7c00063400000000, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRADCC, 0xfc0007ff00000000, 0x7c00063500000000, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRADI, 0xfc0007fd00000000, 0x7c00067400000000, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+       {SRADICC, 0xfc0007fd00000000, 0x7c00067500000000, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+       {SRD, 0xfc0007ff00000000, 0x7c00043600000000, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRDCC, 0xfc0007ff00000000, 0x7c00043700000000, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {STD, 0xfc00000300000000, 0xf800000000000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {STDCXCC, 0xfc0007ff00000000, 0x7c0001ad00000000, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STDU, 0xfc00000300000000, 0xf800000100000000, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+       {STDUX, 0xfc0007fe00000000, 0x7c00016a00000000, 0x100000000, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STDX, 0xfc0007fe00000000, 0x7c00012a00000000, 0x100000000, // Store Doubleword Indexed X-form (stdx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STFIWX, 0xfc0007fe00000000, 0x7c0007ae00000000, 0x100000000, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STWCXCC, 0xfc0007ff00000000, 0x7c00012d00000000, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBF, 0xfc0007ff00000000, 0x7c00005000000000, 0x0, // Subtract From XO-form (subf RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFCC, 0xfc0007ff00000000, 0x7c00005100000000, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFO, 0xfc0007ff00000000, 0x7c00045000000000, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFOCC, 0xfc0007ff00000000, 0x7c00045100000000, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {TD, 0xfc0007fe00000000, 0x7c00008800000000, 0x100000000, // Trap Doubleword X-form (td TO,RA,RB)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {TDI, 0xfc00000000000000, 0x800000000000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {TLBSYNC, 0xfc0007fe00000000, 0x7c00046c00000000, 0x3fff80100000000, // TLB Synchronize X-form (tlbsync)
+               [6]*argField{}},
+       {FCTIW, 0xfc0007ff00000000, 0xfc00001c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWCC, 0xfc0007ff00000000, 0xfc00001d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWZ, 0xfc0007ff00000000, 0xfc00001e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FCTIWZCC, 0xfc0007ff00000000, 0xfc00001f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FSQRT, 0xfc00003f00000000, 0xfc00002c00000000, 0x1f07c000000000, // Floating Square Root A-form (fsqrt FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FSQRTCC, 0xfc00003f00000000, 0xfc00002d00000000, 0x1f07c000000000, // Floating Square Root A-form (fsqrt. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {ADD, 0xfc0007ff00000000, 0x7c00021400000000, 0x0, // Add XO-form (add RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDCC, 0xfc0007ff00000000, 0x7c00021500000000, 0x0, // Add XO-form (add. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDO, 0xfc0007ff00000000, 0x7c00061400000000, 0x0, // Add XO-form (addo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDOCC, 0xfc0007ff00000000, 0x7c00061500000000, 0x0, // Add XO-form (addo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDC, 0xfc0007ff00000000, 0x7c00001400000000, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDCCC, 0xfc0007ff00000000, 0x7c00001500000000, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDCO, 0xfc0007ff00000000, 0x7c00041400000000, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDCOCC, 0xfc0007ff00000000, 0x7c00041500000000, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDE, 0xfc0007ff00000000, 0x7c00011400000000, 0x0, // Add Extended XO-form (adde RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDECC, 0xfc0007ff00000000, 0x7c00011500000000, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDEO, 0xfc0007ff00000000, 0x7c00051400000000, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {ADDEOCC, 0xfc0007ff00000000, 0x7c00051500000000, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LI, 0xfc1f000000000000, 0x3800000000000000, 0x0, // Add Immediate D-form (li RT,SI)
+               [6]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
+       {ADDI, 0xfc00000000000000, 0x3800000000000000, 0x0, // Add Immediate D-form (addi RT,RA,SI)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {ADDIC, 0xfc00000000000000, 0x3000000000000000, 0x0, // Add Immediate Carrying D-formy (addic RT,RA,SI)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {ADDICCC, 0xfc00000000000000, 0x3400000000000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {LIS, 0xfc1f000000000000, 0x3c00000000000000, 0x0, // Add Immediate Shifted D-form (lis RT,SI)
+               [6]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
+       {ADDIS, 0xfc00000000000000, 0x3c00000000000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {ADDME, 0xfc0007ff00000000, 0x7c0001d400000000, 0xf80000000000, // Add to Minus One Extended XO-form (addme RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDMECC, 0xfc0007ff00000000, 0x7c0001d500000000, 0xf80000000000, // Add to Minus One Extended XO-form (addme. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDMEO, 0xfc0007ff00000000, 0x7c0005d400000000, 0xf80000000000, // Add to Minus One Extended XO-form (addmeo RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDMEOCC, 0xfc0007ff00000000, 0x7c0005d500000000, 0xf80000000000, // Add to Minus One Extended XO-form (addmeo. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDZE, 0xfc0007ff00000000, 0x7c00019400000000, 0xf80000000000, // Add to Zero Extended XO-form (addze RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDZECC, 0xfc0007ff00000000, 0x7c00019500000000, 0xf80000000000, // Add to Zero Extended XO-form (addze. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDZEO, 0xfc0007ff00000000, 0x7c00059400000000, 0xf80000000000, // Add to Zero Extended XO-form (addzeo RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {ADDZEOCC, 0xfc0007ff00000000, 0x7c00059500000000, 0xf80000000000, // Add to Zero Extended XO-form (addzeo. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {AND, 0xfc0007ff00000000, 0x7c00003800000000, 0x0, // AND X-form (and RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ANDCC, 0xfc0007ff00000000, 0x7c00003900000000, 0x0, // AND X-form (and. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ANDC, 0xfc0007ff00000000, 0x7c00007800000000, 0x0, // AND with Complement X-form (andc RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ANDCCC, 0xfc0007ff00000000, 0x7c00007900000000, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ANDICC, 0xfc00000000000000, 0x7000000000000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+       {ANDISCC, 0xfc00000000000000, 0x7400000000000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+       {B, 0xfc00000300000000, 0x4800000000000000, 0x0, // Branch I-form (b target_addr)
+               [6]*argField{ap_PCRel_6_29_shift2}},
+       {BA, 0xfc00000300000000, 0x4800000200000000, 0x0, // Branch I-form (ba target_addr)
+               [6]*argField{ap_Label_6_29_shift2}},
+       {BL, 0xfc00000300000000, 0x4800000100000000, 0x0, // Branch I-form (bl target_addr)
+               [6]*argField{ap_PCRel_6_29_shift2}},
+       {BLA, 0xfc00000300000000, 0x4800000300000000, 0x0, // Branch I-form (bla target_addr)
+               [6]*argField{ap_Label_6_29_shift2}},
+       {BC, 0xfc00000300000000, 0x4000000000000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
+       {BCA, 0xfc00000300000000, 0x4000000200000000, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
+       {BCL, 0xfc00000300000000, 0x4000000100000000, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
+       {BCLA, 0xfc00000300000000, 0x4000000300000000, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
+       {BCCTR, 0xfc0007ff00000000, 0x4c00042000000000, 0xe00000000000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+       {BCCTRL, 0xfc0007ff00000000, 0x4c00042100000000, 0xe00000000000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+       {BCLR, 0xfc0007ff00000000, 0x4c00002000000000, 0xe00000000000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+       {BCLRL, 0xfc0007ff00000000, 0x4c00002100000000, 0xe00000000000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+       {CMPW, 0xfc2007fe00000000, 0x7c00000000000000, 0x40000100000000, // Compare X-form (cmpw BF,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPD, 0xfc2007fe00000000, 0x7c20000000000000, 0x40000100000000, // Compare X-form (cmpd BF,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMP, 0xfc0007fe00000000, 0x7c00000000000000, 0x40000100000000, // Compare X-form (cmp BF,L,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPWI, 0xfc20000000000000, 0x2c00000000000000, 0x40000000000000, // Compare Immediate D-form (cmpwi BF,RA,SI)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {CMPDI, 0xfc20000000000000, 0x2c20000000000000, 0x40000000000000, // Compare Immediate D-form (cmpdi BF,RA,SI)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {CMPI, 0xfc00000000000000, 0x2c00000000000000, 0x40000000000000, // Compare Immediate D-form (cmpi BF,L,RA,SI)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {CMPLW, 0xfc2007fe00000000, 0x7c00004000000000, 0x40000100000000, // Compare Logical X-form (cmplw BF,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPLD, 0xfc2007fe00000000, 0x7c20004000000000, 0x40000100000000, // Compare Logical X-form (cmpld BF,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPL, 0xfc0007fe00000000, 0x7c00004000000000, 0x40000100000000, // Compare Logical X-form (cmpl BF,L,RA,RB)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {CMPLWI, 0xfc20000000000000, 0x2800000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
+       {CMPLDI, 0xfc20000000000000, 0x2820000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI)
+               [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
+       {CMPLI, 0xfc00000000000000, 0x2800000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmpli BF,L,RA,UI)
+               [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
+       {CNTLZW, 0xfc0007ff00000000, 0x7c00003400000000, 0xf80000000000, // Count Leading Zeros Word X-form (cntlzw RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CNTLZWCC, 0xfc0007ff00000000, 0x7c00003500000000, 0xf80000000000, // Count Leading Zeros Word X-form (cntlzw. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {CRAND, 0xfc0007fe00000000, 0x4c00020200000000, 0x100000000, // Condition Register AND XL-form (crand BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CRANDC, 0xfc0007fe00000000, 0x4c00010200000000, 0x100000000, // Condition Register AND with Complement XL-form (crandc BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CREQV, 0xfc0007fe00000000, 0x4c00024200000000, 0x100000000, // Condition Register Equivalent XL-form (creqv BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CRNAND, 0xfc0007fe00000000, 0x4c0001c200000000, 0x100000000, // Condition Register NAND XL-form (crnand BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CRNOR, 0xfc0007fe00000000, 0x4c00004200000000, 0x100000000, // Condition Register NOR XL-form (crnor BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CROR, 0xfc0007fe00000000, 0x4c00038200000000, 0x100000000, // Condition Register OR XL-form (cror BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CRORC, 0xfc0007fe00000000, 0x4c00034200000000, 0x100000000, // Condition Register OR with Complement XL-form (crorc BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {CRXOR, 0xfc0007fe00000000, 0x4c00018200000000, 0x100000000, // Condition Register XOR XL-form (crxor BT,BA,BB)
+               [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+       {DCBZ, 0xfc0007fe00000000, 0x7c0007ec00000000, 0x3e0000100000000, // Data Cache Block set to Zero X-form (dcbz RA,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+       {EQV, 0xfc0007ff00000000, 0x7c00023800000000, 0x0, // Equivalent X-form (eqv RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {EQVCC, 0xfc0007ff00000000, 0x7c00023900000000, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {EXTSH, 0xfc0007ff00000000, 0x7c00073400000000, 0xf80000000000, // Extend Sign Halfword X-form (extsh RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {EXTSHCC, 0xfc0007ff00000000, 0x7c00073500000000, 0xf80000000000, // Extend Sign Halfword X-form (extsh. RA,RS)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+       {FABS, 0xfc0007ff00000000, 0xfc00021000000000, 0x1f000000000000, // Floating Absolute Value X-form (fabs FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FABSCC, 0xfc0007ff00000000, 0xfc00021100000000, 0x1f000000000000, // Floating Absolute Value X-form (fabs. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FADD, 0xfc00003f00000000, 0xfc00002a00000000, 0x7c000000000, // Floating Add A-form (fadd FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FADDCC, 0xfc00003f00000000, 0xfc00002b00000000, 0x7c000000000, // Floating Add A-form (fadd. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FCMPO, 0xfc0007fe00000000, 0xfc00004000000000, 0x60000100000000, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FCMPU, 0xfc0007fe00000000, 0xfc00000000000000, 0x60000100000000, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
+               [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FDIV, 0xfc00003f00000000, 0xfc00002400000000, 0x7c000000000, // Floating Divide A-form (fdiv FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FDIVCC, 0xfc00003f00000000, 0xfc00002500000000, 0x7c000000000, // Floating Divide A-form (fdiv. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FMADD, 0xfc00003f00000000, 0xfc00003a00000000, 0x0, // Floating Multiply-Add A-form (fmadd FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMADDCC, 0xfc00003f00000000, 0xfc00003b00000000, 0x0, // Floating Multiply-Add A-form (fmadd. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMR, 0xfc0007ff00000000, 0xfc00009000000000, 0x1f000000000000, // Floating Move Register X-form (fmr FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FMRCC, 0xfc0007ff00000000, 0xfc00009100000000, 0x1f000000000000, // Floating Move Register X-form (fmr. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FMSUB, 0xfc00003f00000000, 0xfc00003800000000, 0x0, // Floating Multiply-Subtract A-form (fmsub FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMSUBCC, 0xfc00003f00000000, 0xfc00003900000000, 0x0, // Floating Multiply-Subtract A-form (fmsub. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FMUL, 0xfc00003f00000000, 0xfc00003200000000, 0xf80000000000, // Floating Multiply A-form (fmul FRT,FRA,FRC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+       {FMULCC, 0xfc00003f00000000, 0xfc00003300000000, 0xf80000000000, // Floating Multiply A-form (fmul. FRT,FRA,FRC)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+       {FNABS, 0xfc0007ff00000000, 0xfc00011000000000, 0x1f000000000000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FNABSCC, 0xfc0007ff00000000, 0xfc00011100000000, 0x1f000000000000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FNEG, 0xfc0007ff00000000, 0xfc00005000000000, 0x1f000000000000, // Floating Negate X-form (fneg FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FNEGCC, 0xfc0007ff00000000, 0xfc00005100000000, 0x1f000000000000, // Floating Negate X-form (fneg. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FNMADD, 0xfc00003f00000000, 0xfc00003e00000000, 0x0, // Floating Negative Multiply-Add A-form (fnmadd FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FNMADDCC, 0xfc00003f00000000, 0xfc00003f00000000, 0x0, // Floating Negative Multiply-Add A-form (fnmadd. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FNMSUB, 0xfc00003f00000000, 0xfc00003c00000000, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FNMSUBCC, 0xfc00003f00000000, 0xfc00003d00000000, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub. FRT,FRA,FRC,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+       {FRSP, 0xfc0007ff00000000, 0xfc00001800000000, 0x1f000000000000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FRSPCC, 0xfc0007ff00000000, 0xfc00001900000000, 0x1f000000000000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+       {FSUB, 0xfc00003f00000000, 0xfc00002800000000, 0x7c000000000, // Floating Subtract A-form (fsub FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {FSUBCC, 0xfc00003f00000000, 0xfc00002900000000, 0x7c000000000, // Floating Subtract A-form (fsub. FRT,FRA,FRB)
+               [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+       {ISYNC, 0xfc0007fe00000000, 0x4c00012c00000000, 0x3fff80100000000, // Instruction Synchronize XL-form (isync)
+               [6]*argField{}},
+       {LBZ, 0xfc00000000000000, 0x8800000000000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LBZU, 0xfc00000000000000, 0x8c00000000000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LBZUX, 0xfc0007fe00000000, 0x7c0000ee00000000, 0x100000000, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LBZX, 0xfc0007fe00000000, 0x7c0000ae00000000, 0x100000000, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFD, 0xfc00000000000000, 0xc800000000000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LFDU, 0xfc00000000000000, 0xcc00000000000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LFDUX, 0xfc0007fe00000000, 0x7c0004ee00000000, 0x100000000, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFDX, 0xfc0007fe00000000, 0x7c0004ae00000000, 0x100000000, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFS, 0xfc00000000000000, 0xc000000000000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LFSU, 0xfc00000000000000, 0xc400000000000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LFSUX, 0xfc0007fe00000000, 0x7c00046e00000000, 0x100000000, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LFSX, 0xfc0007fe00000000, 0x7c00042e00000000, 0x100000000, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHA, 0xfc00000000000000, 0xa800000000000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LHAU, 0xfc00000000000000, 0xac00000000000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LHAUX, 0xfc0007fe00000000, 0x7c0002ee00000000, 0x100000000, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHAX, 0xfc0007fe00000000, 0x7c0002ae00000000, 0x100000000, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHBRX, 0xfc0007fe00000000, 0x7c00062c00000000, 0x100000000, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHZ, 0xfc00000000000000, 0xa000000000000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LHZU, 0xfc00000000000000, 0xa400000000000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LHZUX, 0xfc0007fe00000000, 0x7c00026e00000000, 0x100000000, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LHZX, 0xfc0007fe00000000, 0x7c00022e00000000, 0x100000000, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LMW, 0xfc00000000000000, 0xb800000000000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LSWI, 0xfc0007fe00000000, 0x7c0004aa00000000, 0x100000000, // Load String Word Immediate X-form (lswi RT,RA,NB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+       {LSWX, 0xfc0007fe00000000, 0x7c00042a00000000, 0x100000000, // Load String Word Indexed X-form (lswx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LWBRX, 0xfc0007fe00000000, 0x7c00042c00000000, 0x100000000, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LWZ, 0xfc00000000000000, 0x8000000000000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LWZU, 0xfc00000000000000, 0x8400000000000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {LWZUX, 0xfc0007fe00000000, 0x7c00006e00000000, 0x100000000, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {LWZX, 0xfc0007fe00000000, 0x7c00002e00000000, 0x100000000, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MCRF, 0xfc0007fe00000000, 0x4c00000000000000, 0x63f80100000000, // Move Condition Register Field XL-form (mcrf BF,BFA)
+               [6]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
+       {MCRFS, 0xfc0007fe00000000, 0xfc00008000000000, 0x63f80100000000, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
+               [6]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
+       {MFCR, 0xfc1007fe00000000, 0x7c00002600000000, 0xff80100000000, // Move From Condition Register XFX-form (mfcr RT)
+               [6]*argField{ap_Reg_6_10}},
+       {MFFS, 0xfc1f07ff00000000, 0xfc00048e00000000, 0xf80000000000, // Move From FPSCR X-form (mffs FRT)
+               [6]*argField{ap_FPReg_6_10}},
+       {MFFSCC, 0xfc1f07ff00000000, 0xfc00048f00000000, 0xf80000000000, // Move From FPSCR X-form (mffs. FRT)
+               [6]*argField{ap_FPReg_6_10}},
+       {MFMSR, 0xfc0007fe00000000, 0x7c0000a600000000, 0x1ff80100000000, // Move From MSR X-form (mfmsr RT)
+               [6]*argField{ap_Reg_6_10}},
+       {MFSPR, 0xfc0007fe00000000, 0x7c0002a600000000, 0x100000000, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
+               [6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+       {MTCRF, 0xfc1007fe00000000, 0x7c00012000000000, 0x80100000000, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
+               [6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
+       {MTFSB0, 0xfc0007ff00000000, 0xfc00008c00000000, 0x1ff80000000000, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
+               [6]*argField{ap_ImmUnsigned_6_10}},
+       {MTFSB0CC, 0xfc0007ff00000000, 0xfc00008d00000000, 0x1ff80000000000, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
+               [6]*argField{ap_ImmUnsigned_6_10}},
+       {MTFSB1, 0xfc0007ff00000000, 0xfc00004c00000000, 0x1ff80000000000, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
+               [6]*argField{ap_ImmUnsigned_6_10}},
+       {MTFSB1CC, 0xfc0007ff00000000, 0xfc00004d00000000, 0x1ff80000000000, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
+               [6]*argField{ap_ImmUnsigned_6_10}},
+       {MTFSF, 0xfc0007ff00000000, 0xfc00058e00000000, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
+               [6]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
+       {MTFSFCC, 0xfc0007ff00000000, 0xfc00058f00000000, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
+               [6]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
+       {MTFSFI, 0xfc0007ff00000000, 0xfc00010c00000000, 0x7e080000000000, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
+               [6]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
+       {MTFSFICC, 0xfc0007ff00000000, 0xfc00010d00000000, 0x7e080000000000, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
+               [6]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
+       {MTMSR, 0xfc0007fe00000000, 0x7c00012400000000, 0x1ef80100000000, // Move To MSR X-form (mtmsr RS,L)
+               [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
+       {MTSPR, 0xfc0007fe00000000, 0x7c0003a600000000, 0x100000000, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
+               [6]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
+       {MULLI, 0xfc00000000000000, 0x1c00000000000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {MULLW, 0xfc0007ff00000000, 0x7c0001d600000000, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLWCC, 0xfc0007ff00000000, 0x7c0001d700000000, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLWO, 0xfc0007ff00000000, 0x7c0005d600000000, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {MULLWOCC, 0xfc0007ff00000000, 0x7c0005d700000000, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {NAND, 0xfc0007ff00000000, 0x7c0003b800000000, 0x0, // NAND X-form (nand RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {NANDCC, 0xfc0007ff00000000, 0x7c0003b900000000, 0x0, // NAND X-form (nand. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {NEG, 0xfc0007ff00000000, 0x7c0000d000000000, 0xf80000000000, // Negate XO-form (neg RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {NEGCC, 0xfc0007ff00000000, 0x7c0000d100000000, 0xf80000000000, // Negate XO-form (neg. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {NEGO, 0xfc0007ff00000000, 0x7c0004d000000000, 0xf80000000000, // Negate XO-form (nego RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {NEGOCC, 0xfc0007ff00000000, 0x7c0004d100000000, 0xf80000000000, // Negate XO-form (nego. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {NOR, 0xfc0007ff00000000, 0x7c0000f800000000, 0x0, // NOR X-form (nor RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {NORCC, 0xfc0007ff00000000, 0x7c0000f900000000, 0x0, // NOR X-form (nor. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {OR, 0xfc0007ff00000000, 0x7c00037800000000, 0x0, // OR X-form (or RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ORCC, 0xfc0007ff00000000, 0x7c00037900000000, 0x0, // OR X-form (or. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ORC, 0xfc0007ff00000000, 0x7c00033800000000, 0x0, // OR with Complement X-form (orc RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {ORCCC, 0xfc0007ff00000000, 0x7c00033900000000, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {NOP, 0xffffffff00000000, 0x6000000000000000, 0x0, // OR Immediate D-form (nop)
+               [6]*argField{}},
+       {ORI, 0xfc00000000000000, 0x6000000000000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+       {ORIS, 0xfc00000000000000, 0x6400000000000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+       {RLWIMI, 0xfc00000100000000, 0x5000000000000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+       {RLWIMICC, 0xfc00000100000000, 0x5000000100000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+       {RLWINM, 0xfc00000100000000, 0x5400000000000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+       {RLWINMCC, 0xfc00000100000000, 0x5400000100000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+       {RLWNM, 0xfc00000100000000, 0x5c00000000000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+       {RLWNMCC, 0xfc00000100000000, 0x5c00000100000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+       {SLW, 0xfc0007ff00000000, 0x7c00003000000000, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SLWCC, 0xfc0007ff00000000, 0x7c00003100000000, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRAW, 0xfc0007ff00000000, 0x7c00063000000000, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRAWCC, 0xfc0007ff00000000, 0x7c00063100000000, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRAWI, 0xfc0007ff00000000, 0x7c00067000000000, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
+       {SRAWICC, 0xfc0007ff00000000, 0x7c00067100000000, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
+       {SRW, 0xfc0007ff00000000, 0x7c00043000000000, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {SRWCC, 0xfc0007ff00000000, 0x7c00043100000000, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {STB, 0xfc00000000000000, 0x9800000000000000, 0x0, // Store Byte D-form (stb RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STBU, 0xfc00000000000000, 0x9c00000000000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STBUX, 0xfc0007fe00000000, 0x7c0001ee00000000, 0x100000000, // Store Byte with Update Indexed X-form (stbux RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STBX, 0xfc0007fe00000000, 0x7c0001ae00000000, 0x100000000, // Store Byte Indexed X-form (stbx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STFD, 0xfc00000000000000, 0xd800000000000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STFDU, 0xfc00000000000000, 0xdc00000000000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STFDUX, 0xfc0007fe00000000, 0x7c0005ee00000000, 0x100000000, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STFDX, 0xfc0007fe00000000, 0x7c0005ae00000000, 0x100000000, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STFS, 0xfc00000000000000, 0xd000000000000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STFSU, 0xfc00000000000000, 0xd400000000000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA))
+               [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STFSUX, 0xfc0007fe00000000, 0x7c00056e00000000, 0x100000000, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STFSX, 0xfc0007fe00000000, 0x7c00052e00000000, 0x100000000, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB)
+               [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STH, 0xfc00000000000000, 0xb000000000000000, 0x0, // Store Halfword D-form (sth RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STHBRX, 0xfc0007fe00000000, 0x7c00072c00000000, 0x100000000, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STHU, 0xfc00000000000000, 0xb400000000000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STHUX, 0xfc0007fe00000000, 0x7c00036e00000000, 0x100000000, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STHX, 0xfc0007fe00000000, 0x7c00032e00000000, 0x100000000, // Store Halfword Indexed X-form (sthx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STMW, 0xfc00000000000000, 0xbc00000000000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STSWI, 0xfc0007fe00000000, 0x7c0005aa00000000, 0x100000000, // Store String Word Immediate X-form (stswi RS,RA,NB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+       {STSWX, 0xfc0007fe00000000, 0x7c00052a00000000, 0x100000000, // Store String Word Indexed X-form (stswx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STW, 0xfc00000000000000, 0x9000000000000000, 0x0, // Store Word D-form (stw RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STWBRX, 0xfc0007fe00000000, 0x7c00052c00000000, 0x100000000, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STWU, 0xfc00000000000000, 0x9400000000000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA))
+               [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+       {STWUX, 0xfc0007fe00000000, 0x7c00016e00000000, 0x100000000, // Store Word with Update Indexed X-form (stwux RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {STWX, 0xfc0007fe00000000, 0x7c00012e00000000, 0x100000000, // Store Word Indexed X-form (stwx RS,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFC, 0xfc0007ff00000000, 0x7c00001000000000, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFCCC, 0xfc0007ff00000000, 0x7c00001100000000, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFCO, 0xfc0007ff00000000, 0x7c00041000000000, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFCOCC, 0xfc0007ff00000000, 0x7c00041100000000, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFE, 0xfc0007ff00000000, 0x7c00011000000000, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFECC, 0xfc0007ff00000000, 0x7c00011100000000, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFEO, 0xfc0007ff00000000, 0x7c00051000000000, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFEOCC, 0xfc0007ff00000000, 0x7c00051100000000, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {SUBFIC, 0xfc00000000000000, 0x2000000000000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {SUBFME, 0xfc0007ff00000000, 0x7c0001d000000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfme RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFMECC, 0xfc0007ff00000000, 0x7c0001d100000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFMEO, 0xfc0007ff00000000, 0x7c0005d000000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFMEOCC, 0xfc0007ff00000000, 0x7c0005d100000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFZE, 0xfc0007ff00000000, 0x7c00019000000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfze RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFZECC, 0xfc0007ff00000000, 0x7c00019100000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfze. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFZEO, 0xfc0007ff00000000, 0x7c00059000000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SUBFZEOCC, 0xfc0007ff00000000, 0x7c00059100000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
+               [6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+       {SYNC, 0xfc0007fe00000000, 0x7c0004ac00000000, 0x31cf80100000000, // Synchronize X-form (sync L,SC)
+               [6]*argField{ap_ImmUnsigned_8_10, ap_ImmUnsigned_14_15}},
+       {TLBIE, 0xfc0007fe00000000, 0x7c00026400000000, 0x10000100000000, // TLB Invalidate Entry X-form (tlbie RB,RS,RIC,PRS,R)
+               [6]*argField{ap_Reg_16_20, ap_Reg_6_10, ap_ImmUnsigned_12_13, ap_ImmUnsigned_14_14, ap_ImmUnsigned_15_15}},
+       {TW, 0xfc0007fe00000000, 0x7c00000800000000, 0x100000000, // Trap Word X-form (tw TO,RA,RB)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+       {TWI, 0xfc00000000000000, 0xc00000000000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI)
+               [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+       {XOR, 0xfc0007ff00000000, 0x7c00027800000000, 0x0, // XOR X-form (xor RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {XORCC, 0xfc0007ff00000000, 0x7c00027900000000, 0x0, // XOR X-form (xor. RA,RS,RB)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+       {XORI, 0xfc00000000000000, 0x6800000000000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+       {XORIS, 0xfc00000000000000, 0x6c00000000000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI)
+               [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
 }

diff --git a/src/cmd/vendor/modules.txt b/src/cmd/vendor/modules.txt
index 69d10d074a70dbc3d3ec040bc31550916189b731..93d30db3358152dcf5b5ee8a25ce24890d241eb5 100644 (file)
--- a/src/cmd/vendor/modules.txt
+++ b/src/cmd/vendor/modules.txt
@@ -18,8 +18,8 @@ github.com/google/pprof/third_party/svgpan
 # github.com/ianlancetaylor/demangle v0.0.0-20200824232613-28f6c0f3b639
 ## explicit
 github.com/ianlancetaylor/demangle
-# golang.org/x/arch v0.0.0-20210308155006-05f8f0431f72
-## explicit; go 1.11
+# golang.org/x/arch v0.0.0-20210502124803-cbf565b21d1e
+## explicit; go 1.17
 golang.org/x/arch/arm/armasm
 golang.org/x/arch/arm64/arm64asm
 golang.org/x/arch/ppc64/ppc64asm