case ACMN:
case AADD:
case ASUB:
+ case ASBC:
case ARSB:
case ASLL:
case ASRL:
case AADC:
case AORR:
case ASUB:
- case ARSB:
case ASBC:
+ case ARSB:
case ARSC:
if(p1->reg == n || (p1->reg == NREG && p1->to.type == D_REG && p1->to.reg == n)) {
if(p1->from.type != D_REG)
case AADD: /* read, read, write */
case ASUB:
+ case ASBC:
case ARSB:
case ASLL:
case ASRL:
* funny
*/
case ABL:
- for(z=0; z<BITS; z++)
- addrs.b[z] |= bit.b[z];
+ setaddrs(bit);
break;
}
if(firstr == R)
return;
+ for(i=0; i<nvar; i++) {
+ Var *v = var+i;
+ if(v->addr) {
+ bit = blsh(i);
+ for(z=0; z<BITS; z++)
+ addrs.b[z] |= bit.b[z];
+ }
+
+// print("bit=%2d addr=%d et=%-6E w=%-2d s=%S + %lld\n",
+// i, v->addr, v->etype, v->width, v->sym, v->offset);
+ }
+
/*
* pass 2
* turn branch references to pointers
t = a->type;
n = D_NONE;
+ flag = 0;
+// if(a->pun)
+// flag = 1;
+
switch(t) {
default:
print("type %d %d %D\n", t, a->name, a);
case D_BRANCH:
break;
+ case D_CONST:
+ flag = 1;
+ goto onereg;
+
case D_REGREG:
if(a->offset != NREG)
r->regu |= RtoB(a->offset);
- // fallthrough
+ goto onereg;
- case D_CONST:
case D_REG:
case D_SHIFT:
case D_OREG:
+ onereg:
if(a->reg != NREG)
r->regu |= RtoB(a->reg);
break;
break;
}
- flag = 0;
-// if(a->pun)
-// flag = 1;
-
s = a->sym;
if(s == S)
goto none;
if(debug['R'])
print("bit=%2d et=%E pun=%d %D\n", i, et, flag, a);
-out:
bit = blsh(i);
if(n == D_EXTERN || n == D_STATIC)
for(z=0; z<BITS; z++)
if(n == D_PARAM)
for(z=0; z<BITS; z++)
params.b[z] |= bit.b[z];
- if(t == D_CONST)
- setaddrs(bit);
return bit;