cmd/compile: remove residual register GC map code

We used to generate register GC maps as an experimental approach
for asynchronous preemption, which later we chose not to take.
Most of the register GC map code are already removed. One
exception is that the ssa.Register type still contains a field
for the register map index. Remove it.

Change-Id: Ib177ebce9548aa5ffbcaedd4b507240ea7df8afe
Reviewed-on: https://go-review.googlesource.com/c/go/+/651076
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

diff --git a/src/cmd/compile/internal/ssa/_gen/main.go b/src/cmd/compile/internal/ssa/_gen/main.go
index c2d4ca26655381ba2ec3a6ef99b64accd8db21e9..cbed2f1cd0a2ea421f071ebf183f770c7dcab425 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/main.go
+++ b/src/cmd/compile/internal/ssa/_gen/main.go
@@ -426,7 +426,6 @@ func genOp() {
                        continue
                }
                fmt.Fprintf(w, "var registers%s = [...]Register {\n", a.name)
-               var gcRegN int
                num := map[string]int8{}
                for i, r := range a.regnames {
                        num[r] = int8(i)
@@ -443,14 +442,7 @@ func genOp() {
                        default:
                                objname = pkg + ".REG_" + r
                        }
-                       // Assign a GC register map index to registers
-                       // that may contain pointers.
-                       gcRegIdx := -1
-                       if a.gpregmask&(1<<uint(i)) != 0 {
-                               gcRegIdx = gcRegN
-                               gcRegN++
-                       }
-                       fmt.Fprintf(w, "  {%d, %s, %d, \"%s\"},\n", i, objname, gcRegIdx, r)
+                       fmt.Fprintf(w, "  {%d, %s, \"%s\"},\n", i, objname, r)
                }
                parameterRegisterList := func(paramNamesString string) []int8 {
                        paramNamesString = strings.TrimSpace(paramNamesString)
@@ -477,10 +469,6 @@ func genOp() {
                paramIntRegs := parameterRegisterList(a.ParamIntRegNames)
                paramFloatRegs := parameterRegisterList(a.ParamFloatRegNames)
 
-               if gcRegN > 32 {
-                       // Won't fit in a uint32 mask.
-                       log.Fatalf("too many GC registers (%d > 32) on %s", gcRegN, a.name)
-               }
                fmt.Fprintln(w, "}")
                fmt.Fprintf(w, "var paramIntReg%s = %#v\n", a.name, paramIntRegs)
                fmt.Fprintf(w, "var paramFloatReg%s = %#v\n", a.name, paramFloatRegs)

diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go
index d674cca0099f291b86c2a083d5af3b185bd57f78..ed3795285eb87e7ec0b1766581b6d6866cf5966f 100644 (file)
--- a/src/cmd/compile/internal/ssa/config.go
+++ b/src/cmd/compile/internal/ssa/config.go
@@ -37,24 +37,23 @@ type Config struct {
        floatParamRegs []int8         // register numbers of floating param (in/out) registers
        ABI1           *abi.ABIConfig // "ABIInternal" under development // TODO change comment when this becomes current
        ABI0           *abi.ABIConfig
-       GCRegMap       []*Register // garbage collector register map, by GC register index
-       FPReg          int8        // register number of frame pointer, -1 if not used
-       LinkReg        int8        // register number of link register if it is a general purpose register, -1 if not used
-       hasGReg        bool        // has hardware g register
-       ctxt           *obj.Link   // Generic arch information
-       optimize       bool        // Do optimization
-       noDuffDevice   bool        // Don't use Duff's device
-       useSSE         bool        // Use SSE for non-float operations
-       useAvg         bool        // Use optimizations that need Avg* operations
-       useHmul        bool        // Use optimizations that need Hmul* operations
-       SoftFloat      bool        //
-       Race           bool        // race detector enabled
-       BigEndian      bool        //
-       UseFMA         bool        // Use hardware FMA operation
-       unalignedOK    bool        // Unaligned loads/stores are ok
-       haveBswap64    bool        // architecture implements Bswap64
-       haveBswap32    bool        // architecture implements Bswap32
-       haveBswap16    bool        // architecture implements Bswap16
+       FPReg          int8      // register number of frame pointer, -1 if not used
+       LinkReg        int8      // register number of link register if it is a general purpose register, -1 if not used
+       hasGReg        bool      // has hardware g register
+       ctxt           *obj.Link // Generic arch information
+       optimize       bool      // Do optimization
+       noDuffDevice   bool      // Don't use Duff's device
+       useSSE         bool      // Use SSE for non-float operations
+       useAvg         bool      // Use optimizations that need Avg* operations
+       useHmul        bool      // Use optimizations that need Hmul* operations
+       SoftFloat      bool      //
+       Race           bool      // race detector enabled
+       BigEndian      bool      //
+       UseFMA         bool      // Use hardware FMA operation
+       unalignedOK    bool      // Unaligned loads/stores are ok
+       haveBswap64    bool      // architecture implements Bswap64
+       haveBswap32    bool      // architecture implements Bswap32
+       haveBswap16    bool      // architecture implements Bswap16
 }
 
 type (
@@ -385,21 +384,6 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo
                opcodeTable[Op386LoweredWB].reg.clobbers |= 1 << 3 // BX
        }
 
-       // Create the GC register map index.
-       // TODO: This is only used for debug printing. Maybe export config.registers?
-       gcRegMapSize := int16(0)
-       for _, r := range c.registers {
-               if r.gcNum+1 > gcRegMapSize {
-                       gcRegMapSize = r.gcNum + 1
-               }
-       }
-       c.GCRegMap = make([]*Register, gcRegMapSize)
-       for i, r := range c.registers {
-               if r.gcNum != -1 {
-                       c.GCRegMap[r.gcNum] = &c.registers[i]
-               }
-       }
-
        return c
 }
 

diff --git a/src/cmd/compile/internal/ssa/location.go b/src/cmd/compile/internal/ssa/location.go
index 00aea879363d6bda91faee38f188dada7d712a2e..24c5633deae2b112aa2bab276ca87ef03008337d 100644 (file)
--- a/src/cmd/compile/internal/ssa/location.go
+++ b/src/cmd/compile/internal/ssa/location.go
@@ -20,7 +20,6 @@ type Location interface {
 type Register struct {
        num    int32 // dense numbering
        objNum int16 // register number from cmd/internal/obj/$ARCH
-       gcNum  int16 // GC register map number (dense numbering of registers that can contain pointers)
        name   string
 }
 
@@ -34,12 +33,6 @@ func (r *Register) ObjNum() int16 {
        return r.objNum
 }
 
-// GCNum returns the runtime GC register index of r, or -1 if this
-// register can't contain pointers.
-func (r *Register) GCNum() int16 {
-       return r.gcNum
-}
-
 // A LocalSlot is a location in the stack frame, which identifies and stores
 // part or all of a PPARAM, PPARAMOUT, or PAUTO ONAME node.
 // It can represent a whole variable, part of a larger stack slot, or part of a

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 718f4c93821dcf5720976c887e891d2622bb54cf..8b51015ed8ad06881c4bbf660e1c6103def055a3 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -42539,23 +42539,23 @@ func (o Op) UnsafePoint() bool    { return opcodeTable[o].unsafePoint }
 func (o Op) ResultInArg0() bool   { return opcodeTable[o].resultInArg0 }
 
 var registers386 = [...]Register{
-       {0, x86.REG_AX, 0, "AX"},
-       {1, x86.REG_CX, 1, "CX"},
-       {2, x86.REG_DX, 2, "DX"},
-       {3, x86.REG_BX, 3, "BX"},
-       {4, x86.REGSP, -1, "SP"},
-       {5, x86.REG_BP, 4, "BP"},
-       {6, x86.REG_SI, 5, "SI"},
-       {7, x86.REG_DI, 6, "DI"},
-       {8, x86.REG_X0, -1, "X0"},
-       {9, x86.REG_X1, -1, "X1"},
-       {10, x86.REG_X2, -1, "X2"},
-       {11, x86.REG_X3, -1, "X3"},
-       {12, x86.REG_X4, -1, "X4"},
-       {13, x86.REG_X5, -1, "X5"},
-       {14, x86.REG_X6, -1, "X6"},
-       {15, x86.REG_X7, -1, "X7"},
-       {16, 0, -1, "SB"},
+       {0, x86.REG_AX, "AX"},
+       {1, x86.REG_CX, "CX"},
+       {2, x86.REG_DX, "DX"},
+       {3, x86.REG_BX, "BX"},
+       {4, x86.REGSP, "SP"},
+       {5, x86.REG_BP, "BP"},
+       {6, x86.REG_SI, "SI"},
+       {7, x86.REG_DI, "DI"},
+       {8, x86.REG_X0, "X0"},
+       {9, x86.REG_X1, "X1"},
+       {10, x86.REG_X2, "X2"},
+       {11, x86.REG_X3, "X3"},
+       {12, x86.REG_X4, "X4"},
+       {13, x86.REG_X5, "X5"},
+       {14, x86.REG_X6, "X6"},
+       {15, x86.REG_X7, "X7"},
+       {16, 0, "SB"},
 }
 var paramIntReg386 = []int8(nil)
 var paramFloatReg386 = []int8(nil)
@@ -42565,39 +42565,39 @@ var specialRegMask386 = regMask(0)
 var framepointerReg386 = int8(5)
 var linkReg386 = int8(-1)
 var registersAMD64 = [...]Register{
-       {0, x86.REG_AX, 0, "AX"},
-       {1, x86.REG_CX, 1, "CX"},
-       {2, x86.REG_DX, 2, "DX"},
-       {3, x86.REG_BX, 3, "BX"},
-       {4, x86.REGSP, -1, "SP"},
-       {5, x86.REG_BP, 4, "BP"},
-       {6, x86.REG_SI, 5, "SI"},
-       {7, x86.REG_DI, 6, "DI"},
-       {8, x86.REG_R8, 7, "R8"},
-       {9, x86.REG_R9, 8, "R9"},
-       {10, x86.REG_R10, 9, "R10"},
-       {11, x86.REG_R11, 10, "R11"},
-       {12, x86.REG_R12, 11, "R12"},
-       {13, x86.REG_R13, 12, "R13"},
-       {14, x86.REGG, -1, "g"},
-       {15, x86.REG_R15, 13, "R15"},
-       {16, x86.REG_X0, -1, "X0"},
-       {17, x86.REG_X1, -1, "X1"},
-       {18, x86.REG_X2, -1, "X2"},
-       {19, x86.REG_X3, -1, "X3"},
-       {20, x86.REG_X4, -1, "X4"},
-       {21, x86.REG_X5, -1, "X5"},
-       {22, x86.REG_X6, -1, "X6"},
-       {23, x86.REG_X7, -1, "X7"},
-       {24, x86.REG_X8, -1, "X8"},
-       {25, x86.REG_X9, -1, "X9"},
-       {26, x86.REG_X10, -1, "X10"},
-       {27, x86.REG_X11, -1, "X11"},
-       {28, x86.REG_X12, -1, "X12"},
-       {29, x86.REG_X13, -1, "X13"},
-       {30, x86.REG_X14, -1, "X14"},
-       {31, x86.REG_X15, -1, "X15"},
-       {32, 0, -1, "SB"},
+       {0, x86.REG_AX, "AX"},
+       {1, x86.REG_CX, "CX"},
+       {2, x86.REG_DX, "DX"},
+       {3, x86.REG_BX, "BX"},
+       {4, x86.REGSP, "SP"},
+       {5, x86.REG_BP, "BP"},
+       {6, x86.REG_SI, "SI"},
+       {7, x86.REG_DI, "DI"},
+       {8, x86.REG_R8, "R8"},
+       {9, x86.REG_R9, "R9"},
+       {10, x86.REG_R10, "R10"},
+       {11, x86.REG_R11, "R11"},
+       {12, x86.REG_R12, "R12"},
+       {13, x86.REG_R13, "R13"},
+       {14, x86.REGG, "g"},
+       {15, x86.REG_R15, "R15"},
+       {16, x86.REG_X0, "X0"},
+       {17, x86.REG_X1, "X1"},
+       {18, x86.REG_X2, "X2"},
+       {19, x86.REG_X3, "X3"},
+       {20, x86.REG_X4, "X4"},
+       {21, x86.REG_X5, "X5"},
+       {22, x86.REG_X6, "X6"},
+       {23, x86.REG_X7, "X7"},
+       {24, x86.REG_X8, "X8"},
+       {25, x86.REG_X9, "X9"},
+       {26, x86.REG_X10, "X10"},
+       {27, x86.REG_X11, "X11"},
+       {28, x86.REG_X12, "X12"},
+       {29, x86.REG_X13, "X13"},
+       {30, x86.REG_X14, "X14"},
+       {31, x86.REG_X15, "X15"},
+       {32, 0, "SB"},
 }
 var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11}
 var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30}
@@ -42607,39 +42607,39 @@ var specialRegMaskAMD64 = regMask(2147483648)
 var framepointerRegAMD64 = int8(5)
 var linkRegAMD64 = int8(-1)
 var registersARM = [...]Register{
-       {0, arm.REG_R0, 0, "R0"},
-       {1, arm.REG_R1, 1, "R1"},
-       {2, arm.REG_R2, 2, "R2"},
-       {3, arm.REG_R3, 3, "R3"},
-       {4, arm.REG_R4, 4, "R4"},
-       {5, arm.REG_R5, 5, "R5"},
-       {6, arm.REG_R6, 6, "R6"},
-       {7, arm.REG_R7, 7, "R7"},
-       {8, arm.REG_R8, 8, "R8"},
-       {9, arm.REG_R9, 9, "R9"},
-       {10, arm.REGG, -1, "g"},
-       {11, arm.REG_R11, -1, "R11"},
-       {12, arm.REG_R12, 10, "R12"},
-       {13, arm.REGSP, -1, "SP"},
-       {14, arm.REG_R14, 11, "R14"},
-       {15, arm.REG_R15, -1, "R15"},
-       {16, arm.REG_F0, -1, "F0"},
-       {17, arm.REG_F1, -1, "F1"},
-       {18, arm.REG_F2, -1, "F2"},
-       {19, arm.REG_F3, -1, "F3"},
-       {20, arm.REG_F4, -1, "F4"},
-       {21, arm.REG_F5, -1, "F5"},
-       {22, arm.REG_F6, -1, "F6"},
-       {23, arm.REG_F7, -1, "F7"},
-       {24, arm.REG_F8, -1, "F8"},
-       {25, arm.REG_F9, -1, "F9"},
-       {26, arm.REG_F10, -1, "F10"},
-       {27, arm.REG_F11, -1, "F11"},
-       {28, arm.REG_F12, -1, "F12"},
-       {29, arm.REG_F13, -1, "F13"},
-       {30, arm.REG_F14, -1, "F14"},
-       {31, arm.REG_F15, -1, "F15"},
-       {32, 0, -1, "SB"},
+       {0, arm.REG_R0, "R0"},
+       {1, arm.REG_R1, "R1"},
+       {2, arm.REG_R2, "R2"},
+       {3, arm.REG_R3, "R3"},
+       {4, arm.REG_R4, "R4"},
+       {5, arm.REG_R5, "R5"},
+       {6, arm.REG_R6, "R6"},
+       {7, arm.REG_R7, "R7"},
+       {8, arm.REG_R8, "R8"},
+       {9, arm.REG_R9, "R9"},
+       {10, arm.REGG, "g"},
+       {11, arm.REG_R11, "R11"},
+       {12, arm.REG_R12, "R12"},
+       {13, arm.REGSP, "SP"},
+       {14, arm.REG_R14, "R14"},
+       {15, arm.REG_R15, "R15"},
+       {16, arm.REG_F0, "F0"},
+       {17, arm.REG_F1, "F1"},
+       {18, arm.REG_F2, "F2"},
+       {19, arm.REG_F3, "F3"},
+       {20, arm.REG_F4, "F4"},
+       {21, arm.REG_F5, "F5"},
+       {22, arm.REG_F6, "F6"},
+       {23, arm.REG_F7, "F7"},
+       {24, arm.REG_F8, "F8"},
+       {25, arm.REG_F9, "F9"},
+       {26, arm.REG_F10, "F10"},
+       {27, arm.REG_F11, "F11"},
+       {28, arm.REG_F12, "F12"},
+       {29, arm.REG_F13, "F13"},
+       {30, arm.REG_F14, "F14"},
+       {31, arm.REG_F15, "F15"},
+       {32, 0, "SB"},
 }
 var paramIntRegARM = []int8(nil)
 var paramFloatRegARM = []int8(nil)
@@ -42649,70 +42649,70 @@ var specialRegMaskARM = regMask(0)
 var framepointerRegARM = int8(-1)
 var linkRegARM = int8(14)
 var registersARM64 = [...]Register{
-       {0, arm64.REG_R0, 0, "R0"},
-       {1, arm64.REG_R1, 1, "R1"},
-       {2, arm64.REG_R2, 2, "R2"},
-       {3, arm64.REG_R3, 3, "R3"},
-       {4, arm64.REG_R4, 4, "R4"},
-       {5, arm64.REG_R5, 5, "R5"},
-       {6, arm64.REG_R6, 6, "R6"},
-       {7, arm64.REG_R7, 7, "R7"},
-       {8, arm64.REG_R8, 8, "R8"},
-       {9, arm64.REG_R9, 9, "R9"},
-       {10, arm64.REG_R10, 10, "R10"},
-       {11, arm64.REG_R11, 11, "R11"},
-       {12, arm64.REG_R12, 12, "R12"},
-       {13, arm64.REG_R13, 13, "R13"},
-       {14, arm64.REG_R14, 14, "R14"},
-       {15, arm64.REG_R15, 15, "R15"},
-       {16, arm64.REG_R16, 16, "R16"},
-       {17, arm64.REG_R17, 17, "R17"},
-       {18, arm64.REG_R18, -1, "R18"},
-       {19, arm64.REG_R19, 18, "R19"},
-       {20, arm64.REG_R20, 19, "R20"},
-       {21, arm64.REG_R21, 20, "R21"},
-       {22, arm64.REG_R22, 21, "R22"},
-       {23, arm64.REG_R23, 22, "R23"},
-       {24, arm64.REG_R24, 23, "R24"},
-       {25, arm64.REG_R25, 24, "R25"},
-       {26, arm64.REG_R26, 25, "R26"},
-       {27, arm64.REGG, -1, "g"},
-       {28, arm64.REG_R29, -1, "R29"},
-       {29, arm64.REG_R30, 26, "R30"},
-       {30, arm64.REGSP, -1, "SP"},
-       {31, arm64.REG_F0, -1, "F0"},
-       {32, arm64.REG_F1, -1, "F1"},
-       {33, arm64.REG_F2, -1, "F2"},
-       {34, arm64.REG_F3, -1, "F3"},
-       {35, arm64.REG_F4, -1, "F4"},
-       {36, arm64.REG_F5, -1, "F5"},
-       {37, arm64.REG_F6, -1, "F6"},
-       {38, arm64.REG_F7, -1, "F7"},
-       {39, arm64.REG_F8, -1, "F8"},
-       {40, arm64.REG_F9, -1, "F9"},
-       {41, arm64.REG_F10, -1, "F10"},
-       {42, arm64.REG_F11, -1, "F11"},
-       {43, arm64.REG_F12, -1, "F12"},
-       {44, arm64.REG_F13, -1, "F13"},
-       {45, arm64.REG_F14, -1, "F14"},
-       {46, arm64.REG_F15, -1, "F15"},
-       {47, arm64.REG_F16, -1, "F16"},
-       {48, arm64.REG_F17, -1, "F17"},
-       {49, arm64.REG_F18, -1, "F18"},
-       {50, arm64.REG_F19, -1, "F19"},
-       {51, arm64.REG_F20, -1, "F20"},
-       {52, arm64.REG_F21, -1, "F21"},
-       {53, arm64.REG_F22, -1, "F22"},
-       {54, arm64.REG_F23, -1, "F23"},
-       {55, arm64.REG_F24, -1, "F24"},
-       {56, arm64.REG_F25, -1, "F25"},
-       {57, arm64.REG_F26, -1, "F26"},
-       {58, arm64.REG_F27, -1, "F27"},
-       {59, arm64.REG_F28, -1, "F28"},
-       {60, arm64.REG_F29, -1, "F29"},
-       {61, arm64.REG_F30, -1, "F30"},
-       {62, arm64.REG_F31, -1, "F31"},
-       {63, 0, -1, "SB"},
+       {0, arm64.REG_R0, "R0"},
+       {1, arm64.REG_R1, "R1"},
+       {2, arm64.REG_R2, "R2"},
+       {3, arm64.REG_R3, "R3"},
+       {4, arm64.REG_R4, "R4"},
+       {5, arm64.REG_R5, "R5"},
+       {6, arm64.REG_R6, "R6"},
+       {7, arm64.REG_R7, "R7"},
+       {8, arm64.REG_R8, "R8"},
+       {9, arm64.REG_R9, "R9"},
+       {10, arm64.REG_R10, "R10"},
+       {11, arm64.REG_R11, "R11"},
+       {12, arm64.REG_R12, "R12"},
+       {13, arm64.REG_R13, "R13"},
+       {14, arm64.REG_R14, "R14"},
+       {15, arm64.REG_R15, "R15"},
+       {16, arm64.REG_R16, "R16"},
+       {17, arm64.REG_R17, "R17"},
+       {18, arm64.REG_R18, "R18"},
+       {19, arm64.REG_R19, "R19"},
+       {20, arm64.REG_R20, "R20"},
+       {21, arm64.REG_R21, "R21"},
+       {22, arm64.REG_R22, "R22"},
+       {23, arm64.REG_R23, "R23"},
+       {24, arm64.REG_R24, "R24"},
+       {25, arm64.REG_R25, "R25"},
+       {26, arm64.REG_R26, "R26"},
+       {27, arm64.REGG, "g"},
+       {28, arm64.REG_R29, "R29"},
+       {29, arm64.REG_R30, "R30"},
+       {30, arm64.REGSP, "SP"},
+       {31, arm64.REG_F0, "F0"},
+       {32, arm64.REG_F1, "F1"},
+       {33, arm64.REG_F2, "F2"},
+       {34, arm64.REG_F3, "F3"},
+       {35, arm64.REG_F4, "F4"},
+       {36, arm64.REG_F5, "F5"},
+       {37, arm64.REG_F6, "F6"},
+       {38, arm64.REG_F7, "F7"},
+       {39, arm64.REG_F8, "F8"},
+       {40, arm64.REG_F9, "F9"},
+       {41, arm64.REG_F10, "F10"},
+       {42, arm64.REG_F11, "F11"},
+       {43, arm64.REG_F12, "F12"},
+       {44, arm64.REG_F13, "F13"},
+       {45, arm64.REG_F14, "F14"},
+       {46, arm64.REG_F15, "F15"},
+       {47, arm64.REG_F16, "F16"},
+       {48, arm64.REG_F17, "F17"},
+       {49, arm64.REG_F18, "F18"},
+       {50, arm64.REG_F19, "F19"},
+       {51, arm64.REG_F20, "F20"},
+       {52, arm64.REG_F21, "F21"},
+       {53, arm64.REG_F22, "F22"},
+       {54, arm64.REG_F23, "F23"},
+       {55, arm64.REG_F24, "F24"},
+       {56, arm64.REG_F25, "F25"},
+       {57, arm64.REG_F26, "F26"},
+       {58, arm64.REG_F27, "F27"},
+       {59, arm64.REG_F28, "F28"},
+       {60, arm64.REG_F29, "F29"},
+       {61, arm64.REG_F30, "F30"},
+       {62, arm64.REG_F31, "F31"},
+       {63, 0, "SB"},
 }
 var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
 var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46}
@@ -42722,69 +42722,69 @@ var specialRegMaskARM64 = regMask(0)
 var framepointerRegARM64 = int8(-1)
 var linkRegARM64 = int8(29)
 var registersLOONG64 = [...]Register{
-       {0, loong64.REG_R0, -1, "R0"},
-       {1, loong64.REG_R1, -1, "R1"},
-       {2, loong64.REGSP, -1, "SP"},
-       {3, loong64.REG_R4, 0, "R4"},
-       {4, loong64.REG_R5, 1, "R5"},
-       {5, loong64.REG_R6, 2, "R6"},
-       {6, loong64.REG_R7, 3, "R7"},
-       {7, loong64.REG_R8, 4, "R8"},
-       {8, loong64.REG_R9, 5, "R9"},
-       {9, loong64.REG_R10, 6, "R10"},
-       {10, loong64.REG_R11, 7, "R11"},
-       {11, loong64.REG_R12, 8, "R12"},
-       {12, loong64.REG_R13, 9, "R13"},
-       {13, loong64.REG_R14, 10, "R14"},
-       {14, loong64.REG_R15, 11, "R15"},
-       {15, loong64.REG_R16, 12, "R16"},
-       {16, loong64.REG_R17, 13, "R17"},
-       {17, loong64.REG_R18, 14, "R18"},
-       {18, loong64.REG_R19, 15, "R19"},
-       {19, loong64.REG_R20, 16, "R20"},
-       {20, loong64.REG_R21, 17, "R21"},
-       {21, loong64.REGG, -1, "g"},
-       {22, loong64.REG_R23, 18, "R23"},
-       {23, loong64.REG_R24, 19, "R24"},
-       {24, loong64.REG_R25, 20, "R25"},
-       {25, loong64.REG_R26, 21, "R26"},
-       {26, loong64.REG_R27, 22, "R27"},
-       {27, loong64.REG_R28, 23, "R28"},
-       {28, loong64.REG_R29, 24, "R29"},
-       {29, loong64.REG_R31, 25, "R31"},
-       {30, loong64.REG_F0, -1, "F0"},
-       {31, loong64.REG_F1, -1, "F1"},
-       {32, loong64.REG_F2, -1, "F2"},
-       {33, loong64.REG_F3, -1, "F3"},
-       {34, loong64.REG_F4, -1, "F4"},
-       {35, loong64.REG_F5, -1, "F5"},
-       {36, loong64.REG_F6, -1, "F6"},
-       {37, loong64.REG_F7, -1, "F7"},
-       {38, loong64.REG_F8, -1, "F8"},
-       {39, loong64.REG_F9, -1, "F9"},
-       {40, loong64.REG_F10, -1, "F10"},
-       {41, loong64.REG_F11, -1, "F11"},
-       {42, loong64.REG_F12, -1, "F12"},
-       {43, loong64.REG_F13, -1, "F13"},
-       {44, loong64.REG_F14, -1, "F14"},
-       {45, loong64.REG_F15, -1, "F15"},
-       {46, loong64.REG_F16, -1, "F16"},
-       {47, loong64.REG_F17, -1, "F17"},
-       {48, loong64.REG_F18, -1, "F18"},
-       {49, loong64.REG_F19, -1, "F19"},
-       {50, loong64.REG_F20, -1, "F20"},
-       {51, loong64.REG_F21, -1, "F21"},
-       {52, loong64.REG_F22, -1, "F22"},
-       {53, loong64.REG_F23, -1, "F23"},
-       {54, loong64.REG_F24, -1, "F24"},
-       {55, loong64.REG_F25, -1, "F25"},
-       {56, loong64.REG_F26, -1, "F26"},
-       {57, loong64.REG_F27, -1, "F27"},
-       {58, loong64.REG_F28, -1, "F28"},
-       {59, loong64.REG_F29, -1, "F29"},
-       {60, loong64.REG_F30, -1, "F30"},
-       {61, loong64.REG_F31, -1, "F31"},
-       {62, 0, -1, "SB"},
+       {0, loong64.REG_R0, "R0"},
+       {1, loong64.REG_R1, "R1"},
+       {2, loong64.REGSP, "SP"},
+       {3, loong64.REG_R4, "R4"},
+       {4, loong64.REG_R5, "R5"},
+       {5, loong64.REG_R6, "R6"},
+       {6, loong64.REG_R7, "R7"},
+       {7, loong64.REG_R8, "R8"},
+       {8, loong64.REG_R9, "R9"},
+       {9, loong64.REG_R10, "R10"},
+       {10, loong64.REG_R11, "R11"},
+       {11, loong64.REG_R12, "R12"},
+       {12, loong64.REG_R13, "R13"},
+       {13, loong64.REG_R14, "R14"},
+       {14, loong64.REG_R15, "R15"},
+       {15, loong64.REG_R16, "R16"},
+       {16, loong64.REG_R17, "R17"},
+       {17, loong64.REG_R18, "R18"},
+       {18, loong64.REG_R19, "R19"},
+       {19, loong64.REG_R20, "R20"},
+       {20, loong64.REG_R21, "R21"},
+       {21, loong64.REGG, "g"},
+       {22, loong64.REG_R23, "R23"},
+       {23, loong64.REG_R24, "R24"},
+       {24, loong64.REG_R25, "R25"},
+       {25, loong64.REG_R26, "R26"},
+       {26, loong64.REG_R27, "R27"},
+       {27, loong64.REG_R28, "R28"},
+       {28, loong64.REG_R29, "R29"},
+       {29, loong64.REG_R31, "R31"},
+       {30, loong64.REG_F0, "F0"},
+       {31, loong64.REG_F1, "F1"},
+       {32, loong64.REG_F2, "F2"},
+       {33, loong64.REG_F3, "F3"},
+       {34, loong64.REG_F4, "F4"},
+       {35, loong64.REG_F5, "F5"},
+       {36, loong64.REG_F6, "F6"},
+       {37, loong64.REG_F7, "F7"},
+       {38, loong64.REG_F8, "F8"},
+       {39, loong64.REG_F9, "F9"},
+       {40, loong64.REG_F10, "F10"},
+       {41, loong64.REG_F11, "F11"},
+       {42, loong64.REG_F12, "F12"},
+       {43, loong64.REG_F13, "F13"},
+       {44, loong64.REG_F14, "F14"},
+       {45, loong64.REG_F15, "F15"},
+       {46, loong64.REG_F16, "F16"},
+       {47, loong64.REG_F17, "F17"},
+       {48, loong64.REG_F18, "F18"},
+       {49, loong64.REG_F19, "F19"},
+       {50, loong64.REG_F20, "F20"},
+       {51, loong64.REG_F21, "F21"},
+       {52, loong64.REG_F22, "F22"},
+       {53, loong64.REG_F23, "F23"},
+       {54, loong64.REG_F24, "F24"},
+       {55, loong64.REG_F25, "F25"},
+       {56, loong64.REG_F26, "F26"},
+       {57, loong64.REG_F27, "F27"},
+       {58, loong64.REG_F28, "F28"},
+       {59, loong64.REG_F29, "F29"},
+       {60, loong64.REG_F30, "F30"},
+       {61, loong64.REG_F31, "F31"},
+       {62, 0, "SB"},
 }
 var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18}
 var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45}
@@ -42794,54 +42794,54 @@ var specialRegMaskLOONG64 = regMask(0)
 var framepointerRegLOONG64 = int8(-1)
 var linkRegLOONG64 = int8(1)
 var registersMIPS = [...]Register{
-       {0, mips.REG_R0, -1, "R0"},
-       {1, mips.REG_R1, 0, "R1"},
-       {2, mips.REG_R2, 1, "R2"},
-       {3, mips.REG_R3, 2, "R3"},
-       {4, mips.REG_R4, 3, "R4"},
-       {5, mips.REG_R5, 4, "R5"},
-       {6, mips.REG_R6, 5, "R6"},
-       {7, mips.REG_R7, 6, "R7"},
-       {8, mips.REG_R8, 7, "R8"},
-       {9, mips.REG_R9, 8, "R9"},
-       {10, mips.REG_R10, 9, "R10"},
-       {11, mips.REG_R11, 10, "R11"},
-       {12, mips.REG_R12, 11, "R12"},
-       {13, mips.REG_R13, 12, "R13"},
-       {14, mips.REG_R14, 13, "R14"},
-       {15, mips.REG_R15, 14, "R15"},
-       {16, mips.REG_R16, 15, "R16"},
-       {17, mips.REG_R17, 16, "R17"},
-       {18, mips.REG_R18, 17, "R18"},
-       {19, mips.REG_R19, 18, "R19"},
-       {20, mips.REG_R20, 19, "R20"},
-       {21, mips.REG_R21, 20, "R21"},
-       {22, mips.REG_R22, 21, "R22"},
-       {23, mips.REG_R24, 22, "R24"},
-       {24, mips.REG_R25, 23, "R25"},
-       {25, mips.REG_R28, 24, "R28"},
-       {26, mips.REGSP, -1, "SP"},
-       {27, mips.REGG, -1, "g"},
-       {28, mips.REG_R31, 25, "R31"},
-       {29, mips.REG_F0, -1, "F0"},
-       {30, mips.REG_F2, -1, "F2"},
-       {31, mips.REG_F4, -1, "F4"},
-       {32, mips.REG_F6, -1, "F6"},
-       {33, mips.REG_F8, -1, "F8"},
-       {34, mips.REG_F10, -1, "F10"},
-       {35, mips.REG_F12, -1, "F12"},
-       {36, mips.REG_F14, -1, "F14"},
-       {37, mips.REG_F16, -1, "F16"},
-       {38, mips.REG_F18, -1, "F18"},
-       {39, mips.REG_F20, -1, "F20"},
-       {40, mips.REG_F22, -1, "F22"},
-       {41, mips.REG_F24, -1, "F24"},
-       {42, mips.REG_F26, -1, "F26"},
-       {43, mips.REG_F28, -1, "F28"},
-       {44, mips.REG_F30, -1, "F30"},
-       {45, mips.REG_HI, -1, "HI"},
-       {46, mips.REG_LO, -1, "LO"},
-       {47, 0, -1, "SB"},
+       {0, mips.REG_R0, "R0"},
+       {1, mips.REG_R1, "R1"},
+       {2, mips.REG_R2, "R2"},
+       {3, mips.REG_R3, "R3"},
+       {4, mips.REG_R4, "R4"},
+       {5, mips.REG_R5, "R5"},
+       {6, mips.REG_R6, "R6"},
+       {7, mips.REG_R7, "R7"},
+       {8, mips.REG_R8, "R8"},
+       {9, mips.REG_R9, "R9"},
+       {10, mips.REG_R10, "R10"},
+       {11, mips.REG_R11, "R11"},
+       {12, mips.REG_R12, "R12"},
+       {13, mips.REG_R13, "R13"},
+       {14, mips.REG_R14, "R14"},
+       {15, mips.REG_R15, "R15"},
+       {16, mips.REG_R16, "R16"},
+       {17, mips.REG_R17, "R17"},
+       {18, mips.REG_R18, "R18"},
+       {19, mips.REG_R19, "R19"},
+       {20, mips.REG_R20, "R20"},
+       {21, mips.REG_R21, "R21"},
+       {22, mips.REG_R22, "R22"},
+       {23, mips.REG_R24, "R24"},
+       {24, mips.REG_R25, "R25"},
+       {25, mips.REG_R28, "R28"},
+       {26, mips.REGSP, "SP"},
+       {27, mips.REGG, "g"},
+       {28, mips.REG_R31, "R31"},
+       {29, mips.REG_F0, "F0"},
+       {30, mips.REG_F2, "F2"},
+       {31, mips.REG_F4, "F4"},
+       {32, mips.REG_F6, "F6"},
+       {33, mips.REG_F8, "F8"},
+       {34, mips.REG_F10, "F10"},
+       {35, mips.REG_F12, "F12"},
+       {36, mips.REG_F14, "F14"},
+       {37, mips.REG_F16, "F16"},
+       {38, mips.REG_F18, "F18"},
+       {39, mips.REG_F20, "F20"},
+       {40, mips.REG_F22, "F22"},
+       {41, mips.REG_F24, "F24"},
+       {42, mips.REG_F26, "F26"},
+       {43, mips.REG_F28, "F28"},
+       {44, mips.REG_F30, "F30"},
+       {45, mips.REG_HI, "HI"},
+       {46, mips.REG_LO, "LO"},
+       {47, 0, "SB"},
 }
 var paramIntRegMIPS = []int8(nil)
 var paramFloatRegMIPS = []int8(nil)
@@ -42851,69 +42851,69 @@ var specialRegMaskMIPS = regMask(105553116266496)
 var framepointerRegMIPS = int8(-1)
 var linkRegMIPS = int8(28)
 var registersMIPS64 = [...]Register{
-       {0, mips.REG_R0, -1, "R0"},
-       {1, mips.REG_R1, 0, "R1"},
-       {2, mips.REG_R2, 1, "R2"},
-       {3, mips.REG_R3, 2, "R3"},
-       {4, mips.REG_R4, 3, "R4"},
-       {5, mips.REG_R5, 4, "R5"},
-       {6, mips.REG_R6, 5, "R6"},
-       {7, mips.REG_R7, 6, "R7"},
-       {8, mips.REG_R8, 7, "R8"},
-       {9, mips.REG_R9, 8, "R9"},
-       {10, mips.REG_R10, 9, "R10"},
-       {11, mips.REG_R11, 10, "R11"},
-       {12, mips.REG_R12, 11, "R12"},
-       {13, mips.REG_R13, 12, "R13"},
-       {14, mips.REG_R14, 13, "R14"},
-       {15, mips.REG_R15, 14, "R15"},
-       {16, mips.REG_R16, 15, "R16"},
-       {17, mips.REG_R17, 16, "R17"},
-       {18, mips.REG_R18, 17, "R18"},
-       {19, mips.REG_R19, 18, "R19"},
-       {20, mips.REG_R20, 19, "R20"},
-       {21, mips.REG_R21, 20, "R21"},
-       {22, mips.REG_R22, 21, "R22"},
-       {23, mips.REG_R24, 22, "R24"},
-       {24, mips.REG_R25, 23, "R25"},
-       {25, mips.REGSP, -1, "SP"},
-       {26, mips.REGG, -1, "g"},
-       {27, mips.REG_R31, 24, "R31"},
-       {28, mips.REG_F0, -1, "F0"},
-       {29, mips.REG_F1, -1, "F1"},
-       {30, mips.REG_F2, -1, "F2"},
-       {31, mips.REG_F3, -1, "F3"},
-       {32, mips.REG_F4, -1, "F4"},
-       {33, mips.REG_F5, -1, "F5"},
-       {34, mips.REG_F6, -1, "F6"},
-       {35, mips.REG_F7, -1, "F7"},
-       {36, mips.REG_F8, -1, "F8"},
-       {37, mips.REG_F9, -1, "F9"},
-       {38, mips.REG_F10, -1, "F10"},
-       {39, mips.REG_F11, -1, "F11"},
-       {40, mips.REG_F12, -1, "F12"},
-       {41, mips.REG_F13, -1, "F13"},
-       {42, mips.REG_F14, -1, "F14"},
-       {43, mips.REG_F15, -1, "F15"},
-       {44, mips.REG_F16, -1, "F16"},
-       {45, mips.REG_F17, -1, "F17"},
-       {46, mips.REG_F18, -1, "F18"},
-       {47, mips.REG_F19, -1, "F19"},
-       {48, mips.REG_F20, -1, "F20"},
-       {49, mips.REG_F21, -1, "F21"},
-       {50, mips.REG_F22, -1, "F22"},
-       {51, mips.REG_F23, -1, "F23"},
-       {52, mips.REG_F24, -1, "F24"},
-       {53, mips.REG_F25, -1, "F25"},
-       {54, mips.REG_F26, -1, "F26"},
-       {55, mips.REG_F27, -1, "F27"},
-       {56, mips.REG_F28, -1, "F28"},
-       {57, mips.REG_F29, -1, "F29"},
-       {58, mips.REG_F30, -1, "F30"},
-       {59, mips.REG_F31, -1, "F31"},
-       {60, mips.REG_HI, -1, "HI"},
-       {61, mips.REG_LO, -1, "LO"},
-       {62, 0, -1, "SB"},
+       {0, mips.REG_R0, "R0"},
+       {1, mips.REG_R1, "R1"},
+       {2, mips.REG_R2, "R2"},
+       {3, mips.REG_R3, "R3"},
+       {4, mips.REG_R4, "R4"},
+       {5, mips.REG_R5, "R5"},
+       {6, mips.REG_R6, "R6"},
+       {7, mips.REG_R7, "R7"},
+       {8, mips.REG_R8, "R8"},
+       {9, mips.REG_R9, "R9"},
+       {10, mips.REG_R10, "R10"},
+       {11, mips.REG_R11, "R11"},
+       {12, mips.REG_R12, "R12"},
+       {13, mips.REG_R13, "R13"},
+       {14, mips.REG_R14, "R14"},
+       {15, mips.REG_R15, "R15"},
+       {16, mips.REG_R16, "R16"},
+       {17, mips.REG_R17, "R17"},
+       {18, mips.REG_R18, "R18"},
+       {19, mips.REG_R19, "R19"},
+       {20, mips.REG_R20, "R20"},
+       {21, mips.REG_R21, "R21"},
+       {22, mips.REG_R22, "R22"},
+       {23, mips.REG_R24, "R24"},
+       {24, mips.REG_R25, "R25"},
+       {25, mips.REGSP, "SP"},
+       {26, mips.REGG, "g"},
+       {27, mips.REG_R31, "R31"},
+       {28, mips.REG_F0, "F0"},
+       {29, mips.REG_F1, "F1"},
+       {30, mips.REG_F2, "F2"},
+       {31, mips.REG_F3, "F3"},
+       {32, mips.REG_F4, "F4"},
+       {33, mips.REG_F5, "F5"},
+       {34, mips.REG_F6, "F6"},
+       {35, mips.REG_F7, "F7"},
+       {36, mips.REG_F8, "F8"},
+       {37, mips.REG_F9, "F9"},
+       {38, mips.REG_F10, "F10"},
+       {39, mips.REG_F11, "F11"},
+       {40, mips.REG_F12, "F12"},
+       {41, mips.REG_F13, "F13"},
+       {42, mips.REG_F14, "F14"},
+       {43, mips.REG_F15, "F15"},
+       {44, mips.REG_F16, "F16"},
+       {45, mips.REG_F17, "F17"},
+       {46, mips.REG_F18, "F18"},
+       {47, mips.REG_F19, "F19"},
+       {48, mips.REG_F20, "F20"},
+       {49, mips.REG_F21, "F21"},
+       {50, mips.REG_F22, "F22"},
+       {51, mips.REG_F23, "F23"},
+       {52, mips.REG_F24, "F24"},
+       {53, mips.REG_F25, "F25"},
+       {54, mips.REG_F26, "F26"},
+       {55, mips.REG_F27, "F27"},
+       {56, mips.REG_F28, "F28"},
+       {57, mips.REG_F29, "F29"},
+       {58, mips.REG_F30, "F30"},
+       {59, mips.REG_F31, "F31"},
+       {60, mips.REG_HI, "HI"},
+       {61, mips.REG_LO, "LO"},
+       {62, 0, "SB"},
 }
 var paramIntRegMIPS64 = []int8(nil)
 var paramFloatRegMIPS64 = []int8(nil)
@@ -42923,70 +42923,70 @@ var specialRegMaskMIPS64 = regMask(3458764513820540928)
 var framepointerRegMIPS64 = int8(-1)
 var linkRegMIPS64 = int8(27)
 var registersPPC64 = [...]Register{
-       {0, ppc64.REG_R0, -1, "R0"},
-       {1, ppc64.REGSP, -1, "SP"},
-       {2, 0, -1, "SB"},
-       {3, ppc64.REG_R3, 0, "R3"},
-       {4, ppc64.REG_R4, 1, "R4"},
-       {5, ppc64.REG_R5, 2, "R5"},
-       {6, ppc64.REG_R6, 3, "R6"},
-       {7, ppc64.REG_R7, 4, "R7"},
-       {8, ppc64.REG_R8, 5, "R8"},
-       {9, ppc64.REG_R9, 6, "R9"},
-       {10, ppc64.REG_R10, 7, "R10"},
-       {11, ppc64.REG_R11, 8, "R11"},
-       {12, ppc64.REG_R12, 9, "R12"},
-       {13, ppc64.REG_R13, -1, "R13"},
-       {14, ppc64.REG_R14, 10, "R14"},
-       {15, ppc64.REG_R15, 11, "R15"},
-       {16, ppc64.REG_R16, 12, "R16"},
-       {17, ppc64.REG_R17, 13, "R17"},
-       {18, ppc64.REG_R18, 14, "R18"},
-       {19, ppc64.REG_R19, 15, "R19"},
-       {20, ppc64.REG_R20, 16, "R20"},
-       {21, ppc64.REG_R21, 17, "R21"},
-       {22, ppc64.REG_R22, 18, "R22"},
-       {23, ppc64.REG_R23, 19, "R23"},
-       {24, ppc64.REG_R24, 20, "R24"},
-       {25, ppc64.REG_R25, 21, "R25"},
-       {26, ppc64.REG_R26, 22, "R26"},
-       {27, ppc64.REG_R27, 23, "R27"},
-       {28, ppc64.REG_R28, 24, "R28"},
-       {29, ppc64.REG_R29, 25, "R29"},
-       {30, ppc64.REGG, -1, "g"},
-       {31, ppc64.REG_R31, -1, "R31"},
-       {32, ppc64.REG_F0, -1, "F0"},
-       {33, ppc64.REG_F1, -1, "F1"},
-       {34, ppc64.REG_F2, -1, "F2"},
-       {35, ppc64.REG_F3, -1, "F3"},
-       {36, ppc64.REG_F4, -1, "F4"},
-       {37, ppc64.REG_F5, -1, "F5"},
-       {38, ppc64.REG_F6, -1, "F6"},
-       {39, ppc64.REG_F7, -1, "F7"},
-       {40, ppc64.REG_F8, -1, "F8"},
-       {41, ppc64.REG_F9, -1, "F9"},
-       {42, ppc64.REG_F10, -1, "F10"},
-       {43, ppc64.REG_F11, -1, "F11"},
-       {44, ppc64.REG_F12, -1, "F12"},
-       {45, ppc64.REG_F13, -1, "F13"},
-       {46, ppc64.REG_F14, -1, "F14"},
-       {47, ppc64.REG_F15, -1, "F15"},
-       {48, ppc64.REG_F16, -1, "F16"},
-       {49, ppc64.REG_F17, -1, "F17"},
-       {50, ppc64.REG_F18, -1, "F18"},
-       {51, ppc64.REG_F19, -1, "F19"},
-       {52, ppc64.REG_F20, -1, "F20"},
-       {53, ppc64.REG_F21, -1, "F21"},
-       {54, ppc64.REG_F22, -1, "F22"},
-       {55, ppc64.REG_F23, -1, "F23"},
-       {56, ppc64.REG_F24, -1, "F24"},
-       {57, ppc64.REG_F25, -1, "F25"},
-       {58, ppc64.REG_F26, -1, "F26"},
-       {59, ppc64.REG_F27, -1, "F27"},
-       {60, ppc64.REG_F28, -1, "F28"},
-       {61, ppc64.REG_F29, -1, "F29"},
-       {62, ppc64.REG_F30, -1, "F30"},
-       {63, ppc64.REG_XER, -1, "XER"},
+       {0, ppc64.REG_R0, "R0"},
+       {1, ppc64.REGSP, "SP"},
+       {2, 0, "SB"},
+       {3, ppc64.REG_R3, "R3"},
+       {4, ppc64.REG_R4, "R4"},
+       {5, ppc64.REG_R5, "R5"},
+       {6, ppc64.REG_R6, "R6"},
+       {7, ppc64.REG_R7, "R7"},
+       {8, ppc64.REG_R8, "R8"},
+       {9, ppc64.REG_R9, "R9"},
+       {10, ppc64.REG_R10, "R10"},
+       {11, ppc64.REG_R11, "R11"},
+       {12, ppc64.REG_R12, "R12"},
+       {13, ppc64.REG_R13, "R13"},
+       {14, ppc64.REG_R14, "R14"},
+       {15, ppc64.REG_R15, "R15"},
+       {16, ppc64.REG_R16, "R16"},
+       {17, ppc64.REG_R17, "R17"},
+       {18, ppc64.REG_R18, "R18"},
+       {19, ppc64.REG_R19, "R19"},
+       {20, ppc64.REG_R20, "R20"},
+       {21, ppc64.REG_R21, "R21"},
+       {22, ppc64.REG_R22, "R22"},
+       {23, ppc64.REG_R23, "R23"},
+       {24, ppc64.REG_R24, "R24"},
+       {25, ppc64.REG_R25, "R25"},
+       {26, ppc64.REG_R26, "R26"},
+       {27, ppc64.REG_R27, "R27"},
+       {28, ppc64.REG_R28, "R28"},
+       {29, ppc64.REG_R29, "R29"},
+       {30, ppc64.REGG, "g"},
+       {31, ppc64.REG_R31, "R31"},
+       {32, ppc64.REG_F0, "F0"},
+       {33, ppc64.REG_F1, "F1"},
+       {34, ppc64.REG_F2, "F2"},
+       {35, ppc64.REG_F3, "F3"},
+       {36, ppc64.REG_F4, "F4"},
+       {37, ppc64.REG_F5, "F5"},
+       {38, ppc64.REG_F6, "F6"},
+       {39, ppc64.REG_F7, "F7"},
+       {40, ppc64.REG_F8, "F8"},
+       {41, ppc64.REG_F9, "F9"},
+       {42, ppc64.REG_F10, "F10"},
+       {43, ppc64.REG_F11, "F11"},
+       {44, ppc64.REG_F12, "F12"},
+       {45, ppc64.REG_F13, "F13"},
+       {46, ppc64.REG_F14, "F14"},
+       {47, ppc64.REG_F15, "F15"},
+       {48, ppc64.REG_F16, "F16"},
+       {49, ppc64.REG_F17, "F17"},
+       {50, ppc64.REG_F18, "F18"},
+       {51, ppc64.REG_F19, "F19"},
+       {52, ppc64.REG_F20, "F20"},
+       {53, ppc64.REG_F21, "F21"},
+       {54, ppc64.REG_F22, "F22"},
+       {55, ppc64.REG_F23, "F23"},
+       {56, ppc64.REG_F24, "F24"},
+       {57, ppc64.REG_F25, "F25"},
+       {58, ppc64.REG_F26, "F26"},
+       {59, ppc64.REG_F27, "F27"},
+       {60, ppc64.REG_F28, "F28"},
+       {61, ppc64.REG_F29, "F29"},
+       {62, ppc64.REG_F30, "F30"},
+       {63, ppc64.REG_XER, "XER"},
 }
 var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17}
 var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44}
@@ -42996,70 +42996,70 @@ var specialRegMaskPPC64 = regMask(9223372036854775808)
 var framepointerRegPPC64 = int8(-1)
 var linkRegPPC64 = int8(-1)
 var registersRISCV64 = [...]Register{
-       {0, riscv.REG_X0, -1, "X0"},
-       {1, riscv.REGSP, -1, "SP"},
-       {2, riscv.REG_X3, -1, "X3"},
-       {3, riscv.REG_X4, -1, "X4"},
-       {4, riscv.REG_X5, 0, "X5"},
-       {5, riscv.REG_X6, 1, "X6"},
-       {6, riscv.REG_X7, 2, "X7"},
-       {7, riscv.REG_X8, 3, "X8"},
-       {8, riscv.REG_X9, 4, "X9"},
-       {9, riscv.REG_X10, 5, "X10"},
-       {10, riscv.REG_X11, 6, "X11"},
-       {11, riscv.REG_X12, 7, "X12"},
-       {12, riscv.REG_X13, 8, "X13"},
-       {13, riscv.REG_X14, 9, "X14"},
-       {14, riscv.REG_X15, 10, "X15"},
-       {15, riscv.REG_X16, 11, "X16"},
-       {16, riscv.REG_X17, 12, "X17"},
-       {17, riscv.REG_X18, 13, "X18"},
-       {18, riscv.REG_X19, 14, "X19"},
-       {19, riscv.REG_X20, 15, "X20"},
-       {20, riscv.REG_X21, 16, "X21"},
-       {21, riscv.REG_X22, 17, "X22"},
-       {22, riscv.REG_X23, 18, "X23"},
-       {23, riscv.REG_X24, 19, "X24"},
-       {24, riscv.REG_X25, 20, "X25"},
-       {25, riscv.REG_X26, 21, "X26"},
-       {26, riscv.REGG, -1, "g"},
-       {27, riscv.REG_X28, 22, "X28"},
-       {28, riscv.REG_X29, 23, "X29"},
-       {29, riscv.REG_X30, 24, "X30"},
-       {30, riscv.REG_X31, -1, "X31"},
-       {31, riscv.REG_F0, -1, "F0"},
-       {32, riscv.REG_F1, -1, "F1"},
-       {33, riscv.REG_F2, -1, "F2"},
-       {34, riscv.REG_F3, -1, "F3"},
-       {35, riscv.REG_F4, -1, "F4"},
-       {36, riscv.REG_F5, -1, "F5"},
-       {37, riscv.REG_F6, -1, "F6"},
-       {38, riscv.REG_F7, -1, "F7"},
-       {39, riscv.REG_F8, -1, "F8"},
-       {40, riscv.REG_F9, -1, "F9"},
-       {41, riscv.REG_F10, -1, "F10"},
-       {42, riscv.REG_F11, -1, "F11"},
-       {43, riscv.REG_F12, -1, "F12"},
-       {44, riscv.REG_F13, -1, "F13"},
-       {45, riscv.REG_F14, -1, "F14"},
-       {46, riscv.REG_F15, -1, "F15"},
-       {47, riscv.REG_F16, -1, "F16"},
-       {48, riscv.REG_F17, -1, "F17"},
-       {49, riscv.REG_F18, -1, "F18"},
-       {50, riscv.REG_F19, -1, "F19"},
-       {51, riscv.REG_F20, -1, "F20"},
-       {52, riscv.REG_F21, -1, "F21"},
-       {53, riscv.REG_F22, -1, "F22"},
-       {54, riscv.REG_F23, -1, "F23"},
-       {55, riscv.REG_F24, -1, "F24"},
-       {56, riscv.REG_F25, -1, "F25"},
-       {57, riscv.REG_F26, -1, "F26"},
-       {58, riscv.REG_F27, -1, "F27"},
-       {59, riscv.REG_F28, -1, "F28"},
-       {60, riscv.REG_F29, -1, "F29"},
-       {61, riscv.REG_F30, -1, "F30"},
-       {62, riscv.REG_F31, -1, "F31"},
-       {63, 0, -1, "SB"},
+       {0, riscv.REG_X0, "X0"},
+       {1, riscv.REGSP, "SP"},
+       {2, riscv.REG_X3, "X3"},
+       {3, riscv.REG_X4, "X4"},
+       {4, riscv.REG_X5, "X5"},
+       {5, riscv.REG_X6, "X6"},
+       {6, riscv.REG_X7, "X7"},
+       {7, riscv.REG_X8, "X8"},
+       {8, riscv.REG_X9, "X9"},
+       {9, riscv.REG_X10, "X10"},
+       {10, riscv.REG_X11, "X11"},
+       {11, riscv.REG_X12, "X12"},
+       {12, riscv.REG_X13, "X13"},
+       {13, riscv.REG_X14, "X14"},
+       {14, riscv.REG_X15, "X15"},
+       {15, riscv.REG_X16, "X16"},
+       {16, riscv.REG_X17, "X17"},
+       {17, riscv.REG_X18, "X18"},
+       {18, riscv.REG_X19, "X19"},
+       {19, riscv.REG_X20, "X20"},
+       {20, riscv.REG_X21, "X21"},
+       {21, riscv.REG_X22, "X22"},
+       {22, riscv.REG_X23, "X23"},
+       {23, riscv.REG_X24, "X24"},
+       {24, riscv.REG_X25, "X25"},
+       {25, riscv.REG_X26, "X26"},
+       {26, riscv.REGG, "g"},
+       {27, riscv.REG_X28, "X28"},
+       {28, riscv.REG_X29, "X29"},
+       {29, riscv.REG_X30, "X30"},
+       {30, riscv.REG_X31, "X31"},
+       {31, riscv.REG_F0, "F0"},
+       {32, riscv.REG_F1, "F1"},
+       {33, riscv.REG_F2, "F2"},
+       {34, riscv.REG_F3, "F3"},
+       {35, riscv.REG_F4, "F4"},
+       {36, riscv.REG_F5, "F5"},
+       {37, riscv.REG_F6, "F6"},
+       {38, riscv.REG_F7, "F7"},
+       {39, riscv.REG_F8, "F8"},
+       {40, riscv.REG_F9, "F9"},
+       {41, riscv.REG_F10, "F10"},
+       {42, riscv.REG_F11, "F11"},
+       {43, riscv.REG_F12, "F12"},
+       {44, riscv.REG_F13, "F13"},
+       {45, riscv.REG_F14, "F14"},
+       {46, riscv.REG_F15, "F15"},
+       {47, riscv.REG_F16, "F16"},
+       {48, riscv.REG_F17, "F17"},
+       {49, riscv.REG_F18, "F18"},
+       {50, riscv.REG_F19, "F19"},
+       {51, riscv.REG_F20, "F20"},
+       {52, riscv.REG_F21, "F21"},
+       {53, riscv.REG_F22, "F22"},
+       {54, riscv.REG_F23, "F23"},
+       {55, riscv.REG_F24, "F24"},
+       {56, riscv.REG_F25, "F25"},
+       {57, riscv.REG_F26, "F26"},
+       {58, riscv.REG_F27, "F27"},
+       {59, riscv.REG_F28, "F28"},
+       {60, riscv.REG_F29, "F29"},
+       {61, riscv.REG_F30, "F30"},
+       {62, riscv.REG_F31, "F31"},
+       {63, 0, "SB"},
 }
 var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22}
 var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54}
@@ -43069,39 +43069,39 @@ var specialRegMaskRISCV64 = regMask(0)
 var framepointerRegRISCV64 = int8(-1)
 var linkRegRISCV64 = int8(0)
 var registersS390X = [...]Register{
-       {0, s390x.REG_R0, 0, "R0"},
-       {1, s390x.REG_R1, 1, "R1"},
-       {2, s390x.REG_R2, 2, "R2"},
-       {3, s390x.REG_R3, 3, "R3"},
-       {4, s390x.REG_R4, 4, "R4"},
-       {5, s390x.REG_R5, 5, "R5"},
-       {6, s390x.REG_R6, 6, "R6"},
-       {7, s390x.REG_R7, 7, "R7"},
-       {8, s390x.REG_R8, 8, "R8"},
-       {9, s390x.REG_R9, 9, "R9"},
-       {10, s390x.REG_R10, -1, "R10"},
-       {11, s390x.REG_R11, 10, "R11"},
-       {12, s390x.REG_R12, 11, "R12"},
-       {13, s390x.REGG, -1, "g"},
-       {14, s390x.REG_R14, 12, "R14"},
-       {15, s390x.REGSP, -1, "SP"},
-       {16, s390x.REG_F0, -1, "F0"},
-       {17, s390x.REG_F1, -1, "F1"},
-       {18, s390x.REG_F2, -1, "F2"},
-       {19, s390x.REG_F3, -1, "F3"},
-       {20, s390x.REG_F4, -1, "F4"},
-       {21, s390x.REG_F5, -1, "F5"},
-       {22, s390x.REG_F6, -1, "F6"},
-       {23, s390x.REG_F7, -1, "F7"},
-       {24, s390x.REG_F8, -1, "F8"},
-       {25, s390x.REG_F9, -1, "F9"},
-       {26, s390x.REG_F10, -1, "F10"},
-       {27, s390x.REG_F11, -1, "F11"},
-       {28, s390x.REG_F12, -1, "F12"},
-       {29, s390x.REG_F13, -1, "F13"},
-       {30, s390x.REG_F14, -1, "F14"},
-       {31, s390x.REG_F15, -1, "F15"},
-       {32, 0, -1, "SB"},
+       {0, s390x.REG_R0, "R0"},
+       {1, s390x.REG_R1, "R1"},
+       {2, s390x.REG_R2, "R2"},
+       {3, s390x.REG_R3, "R3"},
+       {4, s390x.REG_R4, "R4"},
+       {5, s390x.REG_R5, "R5"},
+       {6, s390x.REG_R6, "R6"},
+       {7, s390x.REG_R7, "R7"},
+       {8, s390x.REG_R8, "R8"},
+       {9, s390x.REG_R9, "R9"},
+       {10, s390x.REG_R10, "R10"},
+       {11, s390x.REG_R11, "R11"},
+       {12, s390x.REG_R12, "R12"},
+       {13, s390x.REGG, "g"},
+       {14, s390x.REG_R14, "R14"},
+       {15, s390x.REGSP, "SP"},
+       {16, s390x.REG_F0, "F0"},
+       {17, s390x.REG_F1, "F1"},
+       {18, s390x.REG_F2, "F2"},
+       {19, s390x.REG_F3, "F3"},
+       {20, s390x.REG_F4, "F4"},
+       {21, s390x.REG_F5, "F5"},
+       {22, s390x.REG_F6, "F6"},
+       {23, s390x.REG_F7, "F7"},
+       {24, s390x.REG_F8, "F8"},
+       {25, s390x.REG_F9, "F9"},
+       {26, s390x.REG_F10, "F10"},
+       {27, s390x.REG_F11, "F11"},
+       {28, s390x.REG_F12, "F12"},
+       {29, s390x.REG_F13, "F13"},
+       {30, s390x.REG_F14, "F14"},
+       {31, s390x.REG_F15, "F15"},
+       {32, 0, "SB"},
 }
 var paramIntRegS390X = []int8(nil)
 var paramFloatRegS390X = []int8(nil)
@@ -43111,57 +43111,57 @@ var specialRegMaskS390X = regMask(0)
 var framepointerRegS390X = int8(-1)
 var linkRegS390X = int8(14)
 var registersWasm = [...]Register{
-       {0, wasm.REG_R0, 0, "R0"},
-       {1, wasm.REG_R1, 1, "R1"},
-       {2, wasm.REG_R2, 2, "R2"},
-       {3, wasm.REG_R3, 3, "R3"},
-       {4, wasm.REG_R4, 4, "R4"},
-       {5, wasm.REG_R5, 5, "R5"},
-       {6, wasm.REG_R6, 6, "R6"},
-       {7, wasm.REG_R7, 7, "R7"},
-       {8, wasm.REG_R8, 8, "R8"},
-       {9, wasm.REG_R9, 9, "R9"},
-       {10, wasm.REG_R10, 10, "R10"},
-       {11, wasm.REG_R11, 11, "R11"},
-       {12, wasm.REG_R12, 12, "R12"},
-       {13, wasm.REG_R13, 13, "R13"},
-       {14, wasm.REG_R14, 14, "R14"},
-       {15, wasm.REG_R15, 15, "R15"},
-       {16, wasm.REG_F0, -1, "F0"},
-       {17, wasm.REG_F1, -1, "F1"},
-       {18, wasm.REG_F2, -1, "F2"},
-       {19, wasm.REG_F3, -1, "F3"},
-       {20, wasm.REG_F4, -1, "F4"},
-       {21, wasm.REG_F5, -1, "F5"},
-       {22, wasm.REG_F6, -1, "F6"},
-       {23, wasm.REG_F7, -1, "F7"},
-       {24, wasm.REG_F8, -1, "F8"},
-       {25, wasm.REG_F9, -1, "F9"},
-       {26, wasm.REG_F10, -1, "F10"},
-       {27, wasm.REG_F11, -1, "F11"},
-       {28, wasm.REG_F12, -1, "F12"},
-       {29, wasm.REG_F13, -1, "F13"},
-       {30, wasm.REG_F14, -1, "F14"},
-       {31, wasm.REG_F15, -1, "F15"},
-       {32, wasm.REG_F16, -1, "F16"},
-       {33, wasm.REG_F17, -1, "F17"},
-       {34, wasm.REG_F18, -1, "F18"},
-       {35, wasm.REG_F19, -1, "F19"},
-       {36, wasm.REG_F20, -1, "F20"},
-       {37, wasm.REG_F21, -1, "F21"},
-       {38, wasm.REG_F22, -1, "F22"},
-       {39, wasm.REG_F23, -1, "F23"},
-       {40, wasm.REG_F24, -1, "F24"},
-       {41, wasm.REG_F25, -1, "F25"},
-       {42, wasm.REG_F26, -1, "F26"},
-       {43, wasm.REG_F27, -1, "F27"},
-       {44, wasm.REG_F28, -1, "F28"},
-       {45, wasm.REG_F29, -1, "F29"},
-       {46, wasm.REG_F30, -1, "F30"},
-       {47, wasm.REG_F31, -1, "F31"},
-       {48, wasm.REGSP, -1, "SP"},
-       {49, wasm.REGG, -1, "g"},
-       {50, 0, -1, "SB"},
+       {0, wasm.REG_R0, "R0"},
+       {1, wasm.REG_R1, "R1"},
+       {2, wasm.REG_R2, "R2"},
+       {3, wasm.REG_R3, "R3"},
+       {4, wasm.REG_R4, "R4"},
+       {5, wasm.REG_R5, "R5"},
+       {6, wasm.REG_R6, "R6"},
+       {7, wasm.REG_R7, "R7"},
+       {8, wasm.REG_R8, "R8"},
+       {9, wasm.REG_R9, "R9"},
+       {10, wasm.REG_R10, "R10"},
+       {11, wasm.REG_R11, "R11"},
+       {12, wasm.REG_R12, "R12"},
+       {13, wasm.REG_R13, "R13"},
+       {14, wasm.REG_R14, "R14"},
+       {15, wasm.REG_R15, "R15"},
+       {16, wasm.REG_F0, "F0"},
+       {17, wasm.REG_F1, "F1"},
+       {18, wasm.REG_F2, "F2"},
+       {19, wasm.REG_F3, "F3"},
+       {20, wasm.REG_F4, "F4"},
+       {21, wasm.REG_F5, "F5"},
+       {22, wasm.REG_F6, "F6"},
+       {23, wasm.REG_F7, "F7"},
+       {24, wasm.REG_F8, "F8"},
+       {25, wasm.REG_F9, "F9"},
+       {26, wasm.REG_F10, "F10"},
+       {27, wasm.REG_F11, "F11"},
+       {28, wasm.REG_F12, "F12"},
+       {29, wasm.REG_F13, "F13"},
+       {30, wasm.REG_F14, "F14"},
+       {31, wasm.REG_F15, "F15"},
+       {32, wasm.REG_F16, "F16"},
+       {33, wasm.REG_F17, "F17"},
+       {34, wasm.REG_F18, "F18"},
+       {35, wasm.REG_F19, "F19"},
+       {36, wasm.REG_F20, "F20"},
+       {37, wasm.REG_F21, "F21"},
+       {38, wasm.REG_F22, "F22"},
+       {39, wasm.REG_F23, "F23"},
+       {40, wasm.REG_F24, "F24"},
+       {41, wasm.REG_F25, "F25"},
+       {42, wasm.REG_F26, "F26"},
+       {43, wasm.REG_F27, "F27"},
+       {44, wasm.REG_F28, "F28"},
+       {45, wasm.REG_F29, "F29"},
+       {46, wasm.REG_F30, "F30"},
+       {47, wasm.REG_F31, "F31"},
+       {48, wasm.REGSP, "SP"},
+       {49, wasm.REGG, "g"},
+       {50, 0, "SB"},
 }
 var paramIntRegWasm = []int8(nil)
 var paramFloatRegWasm = []int8(nil)