cmd/compile: better implementation of Slicemask

Use (-x)>>63 instead of ((x-1)>>63)^-1 to get a mask that
is 0 when x is 0 and all ones when x is positive.

Saves one instruction when slicing.

Change-Id: Ib46d53d3aac6530ac481fa2f265a6eadf3df0567
Reviewed-on: https://go-review.googlesource.com/35641
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>

diff --git a/src/cmd/compile/internal/ssa/gen/386.rules b/src/cmd/compile/internal/ssa/gen/386.rules
index cd4bf9cf8a71180fa15319433c8794e63eb16a33..173f40bc8e2ff71ecd518e52e75a6c6fc491807a 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/386.rules
+++ b/src/cmd/compile/internal/ssa/gen/386.rules
@@ -102,7 +102,7 @@
 
 (Signmask x) -> (SARLconst x [31])
 (Zeromask <t> x) -> (XORLconst [-1] (SBBLcarrymask <t> (CMPLconst x [1])))
-(Slicemask <t> x) -> (XORLconst [-1] (SARLconst <t> (SUBLconst <t> x [1]) [31]))
+(Slicemask <t> x) -> (SARLconst (NEGL <t> x) [31])
 
 // Lowering truncation
 // Because we ignore high parts of registers, truncates are just copies.

diff --git a/src/cmd/compile/internal/ssa/gen/AMD64.rules b/src/cmd/compile/internal/ssa/gen/AMD64.rules
index 8636118669fc0009f6db47be7b7cc5af7435d5cb..a8d31717f2979b9e399c88ac62f3190e7e3f72fe 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/AMD64.rules
+++ b/src/cmd/compile/internal/ssa/gen/AMD64.rules
@@ -125,7 +125,7 @@
 (ZeroExt16to64 x) -> (MOVWQZX x)
 (ZeroExt32to64 x) -> (MOVLQZX x)
 
-(Slicemask <t> x) -> (XORQconst [-1] (SARQconst <t> (SUBQconst <t> x [1]) [63]))
+(Slicemask <t> x) -> (SARQconst (NEGQ <t> x) [63])
 
 // Lowering truncation
 // Because we ignore high parts of registers, truncates are just copies.

diff --git a/src/cmd/compile/internal/ssa/gen/ARM.rules b/src/cmd/compile/internal/ssa/gen/ARM.rules
index 28f074fc204bb724b8c9fcf9b3dcbd0a15faf808..a81f060ef3c306a27ba4219b7c5d7239610a5dec 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/ARM.rules
+++ b/src/cmd/compile/internal/ssa/gen/ARM.rules
@@ -203,7 +203,7 @@
 
 (Signmask x) -> (SRAconst x [31])
 (Zeromask x) -> (SRAconst (RSBshiftRL <config.fe.TypeInt32()> x x [1]) [31]) // sign bit of uint32(x)>>1 - x
-(Slicemask <t> x) -> (MVN (SRAconst <t> (SUBconst <t> x [1]) [31]))
+(Slicemask <t> x) -> (SRAconst (RSBconst <t> [0] x) [31])
 
 // float <-> int conversion
 (Cvt32to32F x) -> (MOVWF x)

diff --git a/src/cmd/compile/internal/ssa/gen/ARM64.rules b/src/cmd/compile/internal/ssa/gen/ARM64.rules
index 53b364a12b55868be1d49cef707cd0c8e5eff249..58ad1ac3691c42d3dde4e5b4e8ddff3243e6133c 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/ARM64.rules
+++ b/src/cmd/compile/internal/ssa/gen/ARM64.rules
@@ -202,7 +202,7 @@
 (ConstNil) -> (MOVDconst [0])
 (ConstBool [b]) -> (MOVDconst [b])
 
-(Slicemask <t> x) -> (MVN (SRAconst <t> (SUBconst <t> x [1]) [63]))
+(Slicemask <t> x) -> (SRAconst (NEG <t> x) [63])
 
 // truncations
 // Because we ignore high parts of registers, truncates are just copies.

diff --git a/src/cmd/compile/internal/ssa/gen/MIPS.rules b/src/cmd/compile/internal/ssa/gen/MIPS.rules
index 008f1b1df13a930e0bff09ba9b51648899f9af45..e4aba36b4308467c5d555f3a9f4e8a34f7d0db62 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/MIPS.rules
+++ b/src/cmd/compile/internal/ssa/gen/MIPS.rules
@@ -181,7 +181,7 @@
 
 (Signmask x) -> (SRAconst x [31])
 (Zeromask x) -> (NEG (SGTU x (MOVWconst [0])))
-(Slicemask x) -> (NEG (SGT x (MOVWconst [0])))
+(Slicemask <t> x) -> (SRAconst (NEG <t> x) [31])
 
 // float <-> int conversion
 (Cvt32to32F x) -> (MOVWF x)

diff --git a/src/cmd/compile/internal/ssa/gen/MIPS64.rules b/src/cmd/compile/internal/ssa/gen/MIPS64.rules
index 7a496be0d81651431087c2c436d190f873258785..efa14ef3e27f9091a3b7577a3f697165c7010370 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/MIPS64.rules
+++ b/src/cmd/compile/internal/ssa/gen/MIPS64.rules
@@ -164,7 +164,7 @@
 (ConstNil) -> (MOVVconst [0])
 (ConstBool [b]) -> (MOVVconst [b])
 
-(Slicemask <t> x) -> (NORconst [0] (SRAVconst <t> (SUBVconst <t> x [1]) [63]))
+(Slicemask <t> x) -> (SRAVconst (NEGV <t> x) [63])
 
 // truncations
 // Because we ignore high parts of registers, truncates are just copies.

diff --git a/src/cmd/compile/internal/ssa/gen/PPC64.rules b/src/cmd/compile/internal/ssa/gen/PPC64.rules
index cad753e591d8c995feece7eedea7a471a890940d..8cca3205897df3d78c7ef4c31e473bb89d63b890 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/PPC64.rules
+++ b/src/cmd/compile/internal/ssa/gen/PPC64.rules
@@ -790,7 +790,7 @@
 (Trunc64to16 x) -> (MOVHreg x)
 (Trunc64to32 x) -> (MOVWreg x)
 
-(Slicemask <t> x) -> (XORconst [-1] (SRADconst <t> (ADDconst <t> x [-1]) [63]))
+(Slicemask <t> x) -> (SRADconst (NEG <t> x) [63])
 
 // Note that MOV??reg returns a 64-bit int, x is not necessarily that wide
 // This may interact with other patterns in the future. (Compare with arm64)

diff --git a/src/cmd/compile/internal/ssa/gen/S390X.rules b/src/cmd/compile/internal/ssa/gen/S390X.rules
index c609d0d8b11296e43389a6eaaa46a79d7f37788f..ef5cf6e1900d08c6b076f968665d1d49b5a9ebad 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/S390X.rules
+++ b/src/cmd/compile/internal/ssa/gen/S390X.rules
@@ -152,7 +152,7 @@
 (ZeroExt16to64 x) -> (MOVHZreg x)
 (ZeroExt32to64 x) -> (MOVWZreg x)
 
-(Slicemask <t> x) -> (XOR (MOVDconst [-1]) (SRADconst <t> (SUBconst <t> x [1]) [63]))
+(Slicemask <t> x) -> (SRADconst (NEG <t> x) [63])
 
 // Lowering truncation
 // Because we ignore high parts of registers, truncates are just copies.

diff --git a/src/cmd/compile/internal/ssa/rewrite386.go b/src/cmd/compile/internal/ssa/rewrite386.go
index e05810bb1d471ea3f7c601e84f62104c9e9d9a94..4a369b2897b15133bac5cc95a57eeb24a9baa97a 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewrite386.go
+++ b/src/cmd/compile/internal/ssa/rewrite386.go
@@ -12932,18 +12932,14 @@ func rewriteValue386_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (XORLconst [-1] (SARLconst <t> (SUBLconst <t> x [1]) [31]))
+       // result: (SARLconst (NEGL <t> x) [31])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(Op386XORLconst)
-               v.AuxInt = -1
-               v0 := b.NewValue0(v.Pos, Op386SARLconst, t)
-               v0.AuxInt = 31
-               v1 := b.NewValue0(v.Pos, Op386SUBLconst, t)
-               v1.AuxInt = 1
-               v1.AddArg(x)
-               v0.AddArg(v1)
+               v.reset(Op386SARLconst)
+               v.AuxInt = 31
+               v0 := b.NewValue0(v.Pos, Op386NEGL, t)
+               v0.AddArg(x)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index 680f212bb7659319e9ffe1a6a52f780888db8234..ff65ad5d19aaacc24b8083c66f73be789ba164aa 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -20168,18 +20168,14 @@ func rewriteValueAMD64_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (XORQconst [-1] (SARQconst <t> (SUBQconst <t> x [1]) [63]))
+       // result: (SARQconst (NEGQ <t> x) [63])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(OpAMD64XORQconst)
-               v.AuxInt = -1
-               v0 := b.NewValue0(v.Pos, OpAMD64SARQconst, t)
-               v0.AuxInt = 63
-               v1 := b.NewValue0(v.Pos, OpAMD64SUBQconst, t)
-               v1.AuxInt = 1
-               v1.AddArg(x)
-               v0.AddArg(v1)
+               v.reset(OpAMD64SARQconst)
+               v.AuxInt = 63
+               v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
+               v0.AddArg(x)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewriteARM.go b/src/cmd/compile/internal/ssa/rewriteARM.go
index f1cd0d5f5d45c3d588b6f8bf4ce0dae238d7c9d9..f76299e8d3207886ddea938a990e5b2e1a141bec 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteARM.go
+++ b/src/cmd/compile/internal/ssa/rewriteARM.go
@@ -16598,17 +16598,15 @@ func rewriteValueARM_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (MVN (SRAconst <t> (SUBconst <t> x [1]) [31]))
+       // result: (SRAconst (RSBconst <t> [0] x) [31])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(OpARMMVN)
-               v0 := b.NewValue0(v.Pos, OpARMSRAconst, t)
-               v0.AuxInt = 31
-               v1 := b.NewValue0(v.Pos, OpARMSUBconst, t)
-               v1.AuxInt = 1
-               v1.AddArg(x)
-               v0.AddArg(v1)
+               v.reset(OpARMSRAconst)
+               v.AuxInt = 31
+               v0 := b.NewValue0(v.Pos, OpARMRSBconst, t)
+               v0.AuxInt = 0
+               v0.AddArg(x)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewriteARM64.go b/src/cmd/compile/internal/ssa/rewriteARM64.go
index 92664b188a46c032f3c94e87f2ad686a37ad3b65..eb1cb005096024aa958047bd2b1ebaecedd8adbb 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteARM64.go
+++ b/src/cmd/compile/internal/ssa/rewriteARM64.go
@@ -14480,17 +14480,14 @@ func rewriteValueARM64_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (MVN (SRAconst <t> (SUBconst <t> x [1]) [63]))
+       // result: (SRAconst (NEG <t> x) [63])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(OpARM64MVN)
-               v0 := b.NewValue0(v.Pos, OpARM64SRAconst, t)
-               v0.AuxInt = 63
-               v1 := b.NewValue0(v.Pos, OpARM64SUBconst, t)
-               v1.AuxInt = 1
-               v1.AddArg(x)
-               v0.AddArg(v1)
+               v.reset(OpARM64SRAconst)
+               v.AuxInt = 63
+               v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
+               v0.AddArg(x)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS.go b/src/cmd/compile/internal/ssa/rewriteMIPS.go
index 21dae76f5f9ff4b50183a5a359d004b6453c5efc..37b4d0a7c5e92b40eadd465fa44a7fcaaf46c777 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteMIPS.go
+++ b/src/cmd/compile/internal/ssa/rewriteMIPS.go
@@ -8304,17 +8304,16 @@ func rewriteValueMIPS_OpSignmask(v *Value, config *Config) bool {
 func rewriteValueMIPS_OpSlicemask(v *Value, config *Config) bool {
        b := v.Block
        _ = b
-       // match: (Slicemask x)
+       // match: (Slicemask <t> x)
        // cond:
-       // result: (NEG (SGT x (MOVWconst [0])))
+       // result: (SRAconst (NEG <t> x) [31])
        for {
+               t := v.Type
                x := v.Args[0]
-               v.reset(OpMIPSNEG)
-               v0 := b.NewValue0(v.Pos, OpMIPSSGT, config.fe.TypeBool())
+               v.reset(OpMIPSSRAconst)
+               v.AuxInt = 31
+               v0 := b.NewValue0(v.Pos, OpMIPSNEG, t)
                v0.AddArg(x)
-               v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, config.fe.TypeUInt32())
-               v1.AuxInt = 0
-               v0.AddArg(v1)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS64.go b/src/cmd/compile/internal/ssa/rewriteMIPS64.go
index 5821337c2f9d242957c887815d4029b94c3ba64e..0748013d4f8edca0a5f3547ac9801e74fcda9fd3 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteMIPS64.go
+++ b/src/cmd/compile/internal/ssa/rewriteMIPS64.go
@@ -8815,18 +8815,14 @@ func rewriteValueMIPS64_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (NORconst [0] (SRAVconst <t> (SUBVconst <t> x [1]) [63]))
+       // result: (SRAVconst (NEGV <t> x) [63])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(OpMIPS64NORconst)
-               v.AuxInt = 0
-               v0 := b.NewValue0(v.Pos, OpMIPS64SRAVconst, t)
-               v0.AuxInt = 63
-               v1 := b.NewValue0(v.Pos, OpMIPS64SUBVconst, t)
-               v1.AuxInt = 1
-               v1.AddArg(x)
-               v0.AddArg(v1)
+               v.reset(OpMIPS64SRAVconst)
+               v.AuxInt = 63
+               v0 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
+               v0.AddArg(x)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewritePPC64.go b/src/cmd/compile/internal/ssa/rewritePPC64.go
index c78971f801ccd0e9e46dec65bdfa2f51d96ea272..95608e1058ef893f7db197a2c2c5a154c392cd21 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewritePPC64.go
+++ b/src/cmd/compile/internal/ssa/rewritePPC64.go
@@ -9084,18 +9084,14 @@ func rewriteValuePPC64_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (XORconst [-1] (SRADconst <t> (ADDconst <t> x [-1]) [63]))
+       // result: (SRADconst (NEG <t> x) [63])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(OpPPC64XORconst)
-               v.AuxInt = -1
-               v0 := b.NewValue0(v.Pos, OpPPC64SRADconst, t)
-               v0.AuxInt = 63
-               v1 := b.NewValue0(v.Pos, OpPPC64ADDconst, t)
-               v1.AuxInt = -1
-               v1.AddArg(x)
-               v0.AddArg(v1)
+               v.reset(OpPPC64SRADconst)
+               v.AuxInt = 63
+               v0 := b.NewValue0(v.Pos, OpPPC64NEG, t)
+               v0.AddArg(x)
                v.AddArg(v0)
                return true
        }

diff --git a/src/cmd/compile/internal/ssa/rewriteS390X.go b/src/cmd/compile/internal/ssa/rewriteS390X.go
index f689d70161d4cddf4fc84ca3baf8592ae5206775..04e1fe8ec9951d679360ee6a1d00ae81464206e0 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteS390X.go
+++ b/src/cmd/compile/internal/ssa/rewriteS390X.go
@@ -17290,21 +17290,15 @@ func rewriteValueS390X_OpSlicemask(v *Value, config *Config) bool {
        _ = b
        // match: (Slicemask <t> x)
        // cond:
-       // result: (XOR (MOVDconst [-1]) (SRADconst <t> (SUBconst <t> x [1]) [63]))
+       // result: (SRADconst (NEG <t> x) [63])
        for {
                t := v.Type
                x := v.Args[0]
-               v.reset(OpS390XXOR)
-               v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, config.fe.TypeUInt64())
-               v0.AuxInt = -1
+               v.reset(OpS390XSRADconst)
+               v.AuxInt = 63
+               v0 := b.NewValue0(v.Pos, OpS390XNEG, t)
+               v0.AddArg(x)
                v.AddArg(v0)
-               v1 := b.NewValue0(v.Pos, OpS390XSRADconst, t)
-               v1.AuxInt = 63
-               v2 := b.NewValue0(v.Pos, OpS390XSUBconst, t)
-               v2.AuxInt = 1
-               v2.AddArg(x)
-               v1.AddArg(v2)
-               v.AddArg(v1)
                return true
        }
 }