cmd/asm: remove the incorrect check of LDADDx-like instructions

According to the ARM Architecture Reference Manual, LDADDx-like
instructions can take rt as zr when the encode A bit is 0. They
are used by the alias STADDx-like instructions. The current
assembler adds incorrect constraints for them, which is rt can't
be zr when field.enc A is 0. This patch removes it.

Add test cases.

Reported by Matt Horsnell <matt.horsnell@arm.com>

The reference:
https://developer.arm.com/documentation/ddi0602/2022-12/Base-Instructions

Change-Id: Ia2487a5e3900e32994fc14edaf03deeb245e70c6
Reviewed-on: https://go-review.googlesource.com/c/go/+/462295
Reviewed-by: Matt Horsnell <matthew.horsnell@gmail.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index a1493a7ad3a0b03da7bd47d8de3ee9051f779e21..534a0b3e41814ff04bedf29622756d62f8b3eb52 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -819,6 +819,38 @@ again:
        LDEORLH R5, (RSP), R7                        // e7236578
        LDEORLB R5, (R6), R7                         // c7206538
        LDEORLB R5, (RSP), R7                        // e7236538
+       LDADDD  R5, (R6), ZR                         // df0025f8
+       LDADDW  R5, (R6), ZR                         // df0025b8
+       LDADDH  R5, (R6), ZR                         // df002578
+       LDADDB  R5, (R6), ZR                         // df002538
+       LDADDLD R5, (R6), ZR                         // df0065f8
+       LDADDLW R5, (R6), ZR                         // df0065b8
+       LDADDLH R5, (R6), ZR                         // df006578
+       LDADDLB R5, (R6), ZR                         // df006538
+       LDCLRD  R5, (R6), ZR                         // df1025f8
+       LDCLRW  R5, (R6), ZR                         // df1025b8
+       LDCLRH  R5, (R6), ZR                         // df102578
+       LDCLRB  R5, (R6), ZR                         // df102538
+       LDCLRLD R5, (R6), ZR                         // df1065f8
+       LDCLRLW R5, (R6), ZR                         // df1065b8
+       LDCLRLH R5, (R6), ZR                         // df106578
+       LDCLRLB R5, (R6), ZR                         // df106538
+       LDEORD  R5, (R6), ZR                         // df2025f8
+       LDEORW  R5, (R6), ZR                         // df2025b8
+       LDEORH  R5, (R6), ZR                         // df202578
+       LDEORB  R5, (R6), ZR                         // df202538
+       LDEORLD R5, (R6), ZR                         // df2065f8
+       LDEORLW R5, (R6), ZR                         // df2065b8
+       LDEORLH R5, (R6), ZR                         // df206578
+       LDEORLB R5, (R6), ZR                         // df206538
+       LDORD   R5, (R6), ZR                         // df3025f8
+       LDORW   R5, (R6), ZR                         // df3025b8
+       LDORH   R5, (R6), ZR                         // df302578
+       LDORB   R5, (R6), ZR                         // df302538
+       LDORLD  R5, (R6), ZR                         // df3065f8
+       LDORLW  R5, (R6), ZR                         // df3065b8
+       LDORLH  R5, (R6), ZR                         // df306578
+       LDORLB  R5, (R6), ZR                         // df306538
        LDORAD  R5, (R6), R7                         // c730a5f8
        LDORAD  R5, (RSP), R7                        // e733a5f8
        LDORAW  R5, (R6), R7                         // c730a5b8

diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s
index 52f01e16a612ae04255aec8b37ce33b1d9d31eff..fa5ec8e89cc053d6a5dab3ffb5b007eb0c9a68c0 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/arm64error.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64error.s
@@ -166,38 +166,6 @@ TEXT errors(SB),$0
        FSTPD   (R1, R2), (R0)                                   // ERROR "invalid register pair"
        FMOVS   (F2), F0                                         // ERROR "illegal combination"
        FMOVD   F0, (F1)                                         // ERROR "illegal combination"
-       LDADDD  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDW  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDH  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDB  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDLD R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDLW R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDLH R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDADDLB R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRD  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRW  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRH  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRB  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRLD R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRLW R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRLH R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDCLRLB R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORD  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORW  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORH  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORB  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORLD R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORLW R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORLH R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDEORLB R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORD   R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORW   R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORH   R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORB   R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORLD  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORLW  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORLH  R5, (R6), ZR                                     // ERROR "illegal destination register"
-       LDORLB  R5, (R6), ZR                                     // ERROR "illegal destination register"
        LDADDAD R5, (R6), RSP                                    // ERROR "illegal destination register"
        LDADDAW R5, (R6), RSP                                    // ERROR "illegal destination register"
        LDADDAH R5, (R6), RSP                                    // ERROR "illegal destination register"

diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index c8fb7425579b4339b0d4fca5b1d7b7a6e2d3c9dc..08c658bce5e62ea843b060b5b40d6740cfa5d632 100644 (file)
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -4229,17 +4229,8 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                if rt == REG_RSP {
                        c.ctxt.Diag("illegal destination register: %v\n", p)
                }
-               if enc, ok := atomicLDADD[p.As]; ok {
-                       // for LDADDx-like instructions, rt can't be r31 when field.enc A is 0, A bit is the 23rd bit.
-                       if (rt == REGZERO) && (enc&(1<<23) == 0) {
-                               c.ctxt.Diag("illegal destination register: %v\n", p)
-                       }
-                       o1 |= enc
-               } else if enc, ok := atomicSWP[p.As]; ok {
-                       o1 |= enc
-               } else {
-                       c.ctxt.Diag("invalid atomic instructions: %v\n", p)
-               }
+
+               o1 = atomicLDADD[p.As] | atomicSWP[p.As]
                o1 |= uint32(rs&31)<<16 | uint32(rb&31)<<5 | uint32(rt&31)
 
        case 48: /* ADD $C_ADDCON2, Rm, Rd */