cmd/internal/obj/loong64: add new instructions ALSL{W/WU/V} for loong64

Go asm syntax:
	ALSL{W/WU/V}	$3, R4, R5, R6

Equivalent platform assembler syntax:
	alsl.{w/wu/d}	$r6, $r4, $r5, 3

Change-Id: Ic8364dfe2753bcea7de6cffe656ca0dde6875766
Reviewed-on: https://go-review.googlesource.com/c/go/+/692136
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Mark Freeman <markfreeman@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>

diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
index 8363996683cad9eb1f30ea8da80e62f4cca63134..845c1b16be2f18949b139d13ec660a748d236960 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
@@ -1095,3 +1095,8 @@ lable2:
        XVBITREVH       $15, X2, X1     // 417c1877
        XVBITREVW       $31, X2, X1     // 41fc1877
        XVBITREVV       $63, X2, X1     // 41fc1977
+
+       // ALSL{W/WU/D}
+       ALSLW           $3, R4, R5, R6  // 86940500
+       ALSLWU          $3, R4, R5, R6  // 86940700
+       ALSLV           $3, R4, R5, R6  // 86942d00

diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go
index 162e36be8cb6a2f343468a4066221cf9fea579ff..46bb0b5b91171a83dc09362b55ece0888766d56c 100644 (file)
--- a/src/cmd/internal/obj/loong64/a.out.go
+++ b/src/cmd/internal/obj/loong64/a.out.go
@@ -567,6 +567,11 @@ const (
        AMOVVF
        AMOVVD
 
+       // 2.2.1.3
+       AALSLW
+       AALSLWU
+       AALSLV
+
        // 2.2.1.8
        AORN
        AANDN

diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go
index d9ff3b7bc94521857ff7f8c9a1852b4e33b4ec5a..02c392be76919025fa34bf55deacff7e3fac081c 100644 (file)
--- a/src/cmd/internal/obj/loong64/anames.go
+++ b/src/cmd/internal/obj/loong64/anames.go
@@ -125,6 +125,9 @@ var Anames = []string{
        "MOVDV",
        "MOVVF",
        "MOVVD",
+       "ALSLW",
+       "ALSLWU",
+       "ALSLV",
        "ORN",
        "ANDN",
        "AMSWAPB",

diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go
index 0d1b202e80037d0ade232f6672810fc79dde5aca..4e66ddd6cd9109e19a7bbec2df53d42b1c7fab59 100644 (file)
--- a/src/cmd/internal/obj/loong64/asm.go
+++ b/src/cmd/internal/obj/loong64/asm.go
@@ -422,6 +422,8 @@ var optab = []Optab{
        {APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
        {APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
 
+       {AALSLV, C_U2CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
+
        {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
        {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
        {obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
@@ -1492,6 +1494,10 @@ func buildop(ctxt *obj.Link) {
                case ABFPT:
                        opset(ABFPF, r0)
 
+               case AALSLV:
+                       opset(AALSLW, r0)
+                       opset(AALSLWU, r0)
+
                case AMOVW,
                        AMOVD,
                        AMOVF,
@@ -1948,6 +1954,10 @@ func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
        return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
 }
 
+func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
+       return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
+}
+
 func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
        return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
 }
@@ -2717,6 +2727,10 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
        case 62: // rdtimex rd, rj
                o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
 
+       case 64: // alsl rd, rj, rk, sa2
+               r := p.GetFrom3().Reg
+               o1 = OP_2IRRR(c.opirrr(p.As), uint32(p.From.Offset), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
+
        case 65: // mov sym@GOT, r ==> pcalau12i + ld.d
                o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
                c.cursym.AddRel(c.ctxt, obj.Reloc{
@@ -4244,6 +4258,19 @@ func (c *ctxt0) opirr(a obj.As) uint32 {
        return 0
 }
 
+func (c *ctxt0) opirrr(a obj.As) uint32 {
+       switch a {
+       case AALSLW:
+               return 0x2 << 17 // alsl.w
+       case AALSLWU:
+               return 0x3 << 17 // alsl.wu
+       case AALSLV:
+               return 0x16 << 17 // alsl.d
+       }
+
+       return 0
+}
+
 func (c *ctxt0) opirir(a obj.As) uint32 {
        switch a {
        case ABSTRINSW: