(EON x (MOVDconst [c])) => (XORconst [^c] x)
(ORN x (MOVDconst [c])) => (ORconst [^c] x)
-(SLL x (MOVDconst [c])) => (SLLconst x [c&63]) // Note: I don't think we ever generate bad constant shifts (i.e. c>=64)
+(SLL x (MOVDconst [c])) => (SLLconst x [c&63])
(SRL x (MOVDconst [c])) => (SRLconst x [c&63])
(SRA x (MOVDconst [c])) => (SRAconst x [c&63])
+(SLL x (ANDconst [63] y)) => (SLL x y)
+(SRL x (ANDconst [63] y)) => (SRL x y)
+(SRA x (ANDconst [63] y)) => (SRA x y)
(CMP x (MOVDconst [c])) => (CMPconst [c] x)
(CMP (MOVDconst [c]) x) => (InvertFlags (CMPconst [c] x))
v.AddArg(x)
return true
}
+ // match: (SLL x (ANDconst [63] y))
+ // result: (SLL x y)
+ for {
+ x := v_0
+ if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 {
+ break
+ }
+ y := v_1.Args[0]
+ v.reset(OpARM64SLL)
+ v.AddArg2(x, y)
+ return true
+ }
return false
}
func rewriteValueARM64_OpARM64SLLconst(v *Value) bool {
v.AddArg(x)
return true
}
+ // match: (SRA x (ANDconst [63] y))
+ // result: (SRA x y)
+ for {
+ x := v_0
+ if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 {
+ break
+ }
+ y := v_1.Args[0]
+ v.reset(OpARM64SRA)
+ v.AddArg2(x, y)
+ return true
+ }
return false
}
func rewriteValueARM64_OpARM64SRAconst(v *Value) bool {
v.AddArg(x)
return true
}
+ // match: (SRL x (ANDconst [63] y))
+ // result: (SRL x y)
+ for {
+ x := v_0
+ if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 {
+ break
+ }
+ y := v_1.Args[0]
+ v.reset(OpARM64SRL)
+ v.AddArg2(x, y)
+ return true
+ }
return false
}
func rewriteValueARM64_OpARM64SRLconst(v *Value) bool {
// ppc64le:"ANDCC",-"ORN",-"ISEL"
// riscv64:"SLL",-"AND\t",-"SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"LSL",-"AND"
return v << (s & 63)
}
// ppc64le:"ANDCC",-"ORN",-"ISEL"
// riscv64:"SRL",-"AND\t",-"SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"LSR",-"AND"
return v >> (s & 63)
}
// ppc64le:"ANDCC",-ORN",-"ISEL"
// riscv64:"SRA",-"OR",-"SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"ASR",-"AND"
return v >> (s & 63)
}
// ppc64le:"ISEL",-"ORN"
// riscv64:"SLL","AND","SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"LSL",-"AND"
return v << (s & 63)
}
// ppc64le:"ISEL",-"ORN"
// riscv64:"SRL","AND","SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"LSR",-"AND"
return v >> (s & 63)
}
// ppc64le:"ISEL",-"ORN"
// riscv64:"SRA","OR","SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"ASR",-"AND"
return v >> (s & 63)
}
// ppc64le:"ANDCC",-"ORN"
// riscv64:"SLL",-"AND\t",-"SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"LSL",-"AND"
return v << (s & 63)
}
// ppc64le:"ANDCC",-"ORN"
// riscv64:"SRL",-"AND\t",-"SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"LSR",-"AND"
return v >> (s & 63)
}
// ppc64le:"ANDCC",-"ORN",-"ISEL"
// riscv64:"SRA",-"OR",-"SLTIU"
// s390x:-"RISBGZ",-"AND",-"LOCGR"
+ // arm64:"ASR",-"AND"
return v >> (s & 63)
}