(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
// Lowering stores
-// These more-specific FP versions of Store pattern should come first.
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVSDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVSSstore ptr val mem)
-
-(Store {t} ptr val mem) && t.Size() == 4 => (MOVLstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
// Lowering stores
-// These more-specific FP versions of Store pattern should come first.
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVSDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVSSstore ptr val mem)
-
-(Store {t} ptr val mem) && t.Size() == 8 => (MOVQstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 => (MOVLstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
// stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zero instructions
(Zero [0] _ mem) => mem
// stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (FMOVSstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
// zeroing
(Zero [0] _ mem) => mem
// stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVVstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zeroing
(Zero [0] _ mem) => mem
// stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zero instructions
(Zero [0] _ mem) => mem
// stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVVstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zeroing
(Zero [0] _ mem) => mem
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (FMOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is32BitFloat(val.Type) => (FMOVDstore ptr val mem) // glitch from (Cvt32Fto64F x) => x -- type is wrong
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (FMOVSstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitInt(val.Type) => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
// Stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (FMOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
// We need to fold MOVaddr into the LD/MOVDstore ops so that the live variable analysis
// knows what variables are being read/written by the ops.
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
// Lowering stores
-// These more-specific FP versions of Store pattern should come first.
-(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (FMOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (FMOVSstore ptr val mem)
-
-(Store {t} ptr val mem) && t.Size() == 8 => (MOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 => (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (MOVSDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(Op386MOVSDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (MOVSSstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(Op386MOVSSstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVLstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(Op386MOVLstore)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (MOVSDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpAMD64MOVSDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (MOVSSstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpAMD64MOVSSstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVQstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpAMD64MOVQstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVLstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpAMD64MOVLstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && !is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && !is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpARMMOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (MOVFstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpARMMOVFstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpARMMOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && !is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && !is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpARM64MOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && !is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && !is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpARM64MOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (FMOVSstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpARM64FMOVSstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (FMOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpARM64FMOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && !is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && !is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpLOONG64MOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && !is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVVstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && !is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpLOONG64MOVVstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (MOVFstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpLOONG64MOVFstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpLOONG64MOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && !is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && !is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpMIPSMOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (MOVFstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpMIPSMOVFstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpMIPSMOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && !is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && !is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpMIPS64MOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && !is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVVstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && !is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpMIPS64MOVVstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (MOVFstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpMIPS64MOVFstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpMIPS64MOVDstore)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (FMOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpPPC64FMOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is32BitFloat(val.Type)
- // result: (FMOVDstore ptr val mem)
- for {
- t := auxToType(v.Aux)
- ptr := v_0
- val := v_1
- mem := v_2
- if !(t.Size() == 8 && is32BitFloat(val.Type)) {
- break
- }
- v.reset(OpPPC64FMOVDstore)
- v.AddArg3(ptr, val, mem)
- return true
- }
- // match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (FMOVSstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpPPC64FMOVSstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && !is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && !is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpPPC64MOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitInt(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitInt(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpPPC64MOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && !is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && !is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpRISCV64MOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && !is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && !is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpRISCV64MOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (FMOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpRISCV64FMOVWstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (FMOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpRISCV64FMOVDstore)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8 && is64BitFloat(val.Type)
+ // cond: t.Size() == 8 && t.IsFloat()
// result: (FMOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8 && is64BitFloat(val.Type)) {
+ if !(t.Size() == 8 && t.IsFloat()) {
break
}
v.reset(OpS390XFMOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4 && is32BitFloat(val.Type)
+ // cond: t.Size() == 4 && t.IsFloat()
// result: (FMOVSstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4 && is32BitFloat(val.Type)) {
+ if !(t.Size() == 4 && t.IsFloat()) {
break
}
v.reset(OpS390XFMOVSstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 8
+ // cond: t.Size() == 8 && !t.IsFloat()
// result: (MOVDstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 8) {
+ if !(t.Size() == 8 && !t.IsFloat()) {
break
}
v.reset(OpS390XMOVDstore)
return true
}
// match: (Store {t} ptr val mem)
- // cond: t.Size() == 4
+ // cond: t.Size() == 4 && !t.IsFloat()
// result: (MOVWstore ptr val mem)
for {
t := auxToType(v.Aux)
ptr := v_0
val := v_1
mem := v_2
- if !(t.Size() == 4) {
+ if !(t.Size() == 4 && !t.IsFloat()) {
break
}
v.reset(OpS390XMOVWstore)