// Same, mutatis mutandis, for UGE and SETAE, and CC and SETCC.
((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) && !config.nacl -> ((ULT|UGE) (BTL x y))
((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) && !config.nacl -> ((ULT|UGE) (BTQ x y))
-((NE|EQ) (TESTLconst [c] x)) && isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- -> ((ULT|UGE) (BTLconst [log2(c)] x))
-((NE|EQ) (TESTQconst [c] x)) && isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+((NE|EQ) (TESTLconst [c] x)) && isUint32PowerOfTwo(c) && !config.nacl
+ -> ((ULT|UGE) (BTLconst [log2uint32(c)] x))
+((NE|EQ) (TESTQconst [c] x)) && isUint64PowerOfTwo(c) && !config.nacl
-> ((ULT|UGE) (BTQconst [log2(c)] x))
-((NE|EQ) (TESTQ (MOVQconst [c]) x)) && isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+((NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUint64PowerOfTwo(c) && !config.nacl
-> ((ULT|UGE) (BTQconst [log2(c)] x))
(SET(NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) && !config.nacl -> (SET(B|AE) (BTL x y))
(SET(NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) && !config.nacl -> (SET(B|AE) (BTQ x y))
-(SET(NE|EQ) (TESTLconst [c] x)) && isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- -> (SET(B|AE) (BTLconst [log2(c)] x))
-(SET(NE|EQ) (TESTQconst [c] x)) && isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+(SET(NE|EQ) (TESTLconst [c] x)) && isUint32PowerOfTwo(c) && !config.nacl
+ -> (SET(B|AE) (BTLconst [log2uint32(c)] x))
+(SET(NE|EQ) (TESTQconst [c] x)) && isUint64PowerOfTwo(c) && !config.nacl
-> (SET(B|AE) (BTQconst [log2(c)] x))
-(SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+(SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUint64PowerOfTwo(c) && !config.nacl
-> (SET(B|AE) (BTQconst [log2(c)] x))
// SET..mem variant
(SET(NE|EQ)mem [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) && !config.nacl
-> (SET(B|AE)mem [off] {sym} ptr (BTL x y) mem)
(SET(NE|EQ)mem [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) && !config.nacl
-> (SET(B|AE)mem [off] {sym} ptr (BTQ x y) mem)
-(SET(NE|EQ)mem [off] {sym} ptr (TESTLconst [c] x) mem) && isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- -> (SET(B|AE)mem [off] {sym} ptr (BTLconst [log2(c)] x) mem)
-(SET(NE|EQ)mem [off] {sym} ptr (TESTQconst [c] x) mem) && isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+(SET(NE|EQ)mem [off] {sym} ptr (TESTLconst [c] x) mem) && isUint32PowerOfTwo(c) && !config.nacl
+ -> (SET(B|AE)mem [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem)
+(SET(NE|EQ)mem [off] {sym} ptr (TESTQconst [c] x) mem) && isUint64PowerOfTwo(c) && !config.nacl
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
-(SET(NE|EQ)mem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+(SET(NE|EQ)mem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isUint64PowerOfTwo(c) && !config.nacl
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
// Fold boolean negation into SETcc.
return true
}
// match: (SETEQ (TESTLconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- // result: (SETAE (BTLconst [log2(c)] x))
+ // cond: isUint32PowerOfTwo(c) && !config.nacl
+ // result: (SETAE (BTLconst [log2uint32(c)] x))
for {
v_0 := v.Args[0]
if v_0.Op != OpAMD64TESTLconst {
}
c := v_0.AuxInt
x := v_0.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ if !(isUint32PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAE)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
- v0.AuxInt = log2(c)
+ v0.AuxInt = log2uint32(c)
v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (SETEQ (TESTQconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETAE (BTQconst [log2(c)] x))
for {
v_0 := v.Args[0]
}
c := v_0.AuxInt
x := v_0.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAE)
return true
}
// match: (SETEQ (TESTQ (MOVQconst [c]) x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETAE (BTQconst [log2(c)] x))
for {
v_0 := v.Args[0]
}
c := v_0_0.AuxInt
x := v_0.Args[1]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAE)
return true
}
// match: (SETEQ (TESTQ x (MOVQconst [c])))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETAE (BTQconst [log2(c)] x))
for {
v_0 := v.Args[0]
break
}
c := v_0_1.AuxInt
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAE)
return true
}
// match: (SETEQmem [off] {sym} ptr (TESTLconst [c] x) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- // result: (SETAEmem [off] {sym} ptr (BTLconst [log2(c)] x) mem)
+ // cond: isUint32PowerOfTwo(c) && !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem)
for {
off := v.AuxInt
sym := v.Aux
c := v_1.AuxInt
x := v_1.Args[0]
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ if !(isUint32PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAEmem)
v.Aux = sym
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
- v0.AuxInt = log2(c)
+ v0.AuxInt = log2uint32(c)
v0.AddArg(x)
v.AddArg(v0)
v.AddArg(mem)
return true
}
// match: (SETEQmem [off] {sym} ptr (TESTQconst [c] x) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETAEmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
for {
off := v.AuxInt
c := v_1.AuxInt
x := v_1.Args[0]
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAEmem)
return true
}
// match: (SETEQmem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETAEmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
for {
off := v.AuxInt
c := v_1_0.AuxInt
x := v_1.Args[1]
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAEmem)
return true
}
// match: (SETEQmem [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETAEmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
for {
off := v.AuxInt
}
c := v_1_1.AuxInt
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETAEmem)
return true
}
// match: (SETNE (TESTLconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- // result: (SETB (BTLconst [log2(c)] x))
+ // cond: isUint32PowerOfTwo(c) && !config.nacl
+ // result: (SETB (BTLconst [log2uint32(c)] x))
for {
v_0 := v.Args[0]
if v_0.Op != OpAMD64TESTLconst {
}
c := v_0.AuxInt
x := v_0.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ if !(isUint32PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
- v0.AuxInt = log2(c)
+ v0.AuxInt = log2uint32(c)
v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (SETNE (TESTQconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETB (BTQconst [log2(c)] x))
for {
v_0 := v.Args[0]
}
c := v_0.AuxInt
x := v_0.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETB)
return true
}
// match: (SETNE (TESTQ (MOVQconst [c]) x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETB (BTQconst [log2(c)] x))
for {
v_0 := v.Args[0]
}
c := v_0_0.AuxInt
x := v_0.Args[1]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETB)
return true
}
// match: (SETNE (TESTQ x (MOVQconst [c])))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETB (BTQconst [log2(c)] x))
for {
v_0 := v.Args[0]
break
}
c := v_0_1.AuxInt
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETB)
return true
}
// match: (SETNEmem [off] {sym} ptr (TESTLconst [c] x) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- // result: (SETBmem [off] {sym} ptr (BTLconst [log2(c)] x) mem)
+ // cond: isUint32PowerOfTwo(c) && !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem)
for {
off := v.AuxInt
sym := v.Aux
c := v_1.AuxInt
x := v_1.Args[0]
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ if !(isUint32PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETBmem)
v.Aux = sym
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
- v0.AuxInt = log2(c)
+ v0.AuxInt = log2uint32(c)
v0.AddArg(x)
v.AddArg(v0)
v.AddArg(mem)
return true
}
// match: (SETNEmem [off] {sym} ptr (TESTQconst [c] x) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETBmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
for {
off := v.AuxInt
c := v_1.AuxInt
x := v_1.Args[0]
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETBmem)
return true
}
// match: (SETNEmem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETBmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
for {
off := v.AuxInt
c := v_1_0.AuxInt
x := v_1.Args[1]
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETBmem)
return true
}
// match: (SETNEmem [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem)
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (SETBmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
for {
off := v.AuxInt
}
c := v_1_1.AuxInt
mem := v.Args[2]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
v.reset(OpAMD64SETBmem)
return true
}
// match: (EQ (TESTLconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- // result: (UGE (BTLconst [log2(c)] x))
+ // cond: isUint32PowerOfTwo(c) && !config.nacl
+ // result: (UGE (BTLconst [log2uint32(c)] x))
for {
v := b.Control
if v.Op != OpAMD64TESTLconst {
}
c := v.AuxInt
x := v.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ if !(isUint32PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64UGE
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
- v0.AuxInt = log2(c)
+ v0.AuxInt = log2uint32(c)
v0.AddArg(x)
b.SetControl(v0)
b.Aux = nil
return true
}
// match: (EQ (TESTQconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (UGE (BTQconst [log2(c)] x))
for {
v := b.Control
}
c := v.AuxInt
x := v.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64UGE
return true
}
// match: (EQ (TESTQ (MOVQconst [c]) x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (UGE (BTQconst [log2(c)] x))
for {
v := b.Control
}
c := v_0.AuxInt
x := v.Args[1]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64UGE
return true
}
// match: (EQ (TESTQ x (MOVQconst [c])))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (UGE (BTQconst [log2(c)] x))
for {
v := b.Control
break
}
c := v_1.AuxInt
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64UGE
return true
}
// match: (NE (TESTLconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
- // result: (ULT (BTLconst [log2(c)] x))
+ // cond: isUint32PowerOfTwo(c) && !config.nacl
+ // result: (ULT (BTLconst [log2uint32(c)] x))
for {
v := b.Control
if v.Op != OpAMD64TESTLconst {
}
c := v.AuxInt
x := v.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ if !(isUint32PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64ULT
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
- v0.AuxInt = log2(c)
+ v0.AuxInt = log2uint32(c)
v0.AddArg(x)
b.SetControl(v0)
b.Aux = nil
return true
}
// match: (NE (TESTQconst [c] x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (ULT (BTQconst [log2(c)] x))
for {
v := b.Control
}
c := v.AuxInt
x := v.Args[0]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64ULT
return true
}
// match: (NE (TESTQ (MOVQconst [c]) x))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (ULT (BTQconst [log2(c)] x))
for {
v := b.Control
}
c := v_0.AuxInt
x := v.Args[1]
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64ULT
return true
}
// match: (NE (TESTQ x (MOVQconst [c])))
- // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // cond: isUint64PowerOfTwo(c) && !config.nacl
// result: (ULT (BTQconst [log2(c)] x))
for {
v := b.Control
break
}
c := v_1.AuxInt
- if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ if !(isUint64PowerOfTwo(c) && !config.nacl) {
break
}
b.Kind = BlockAMD64ULT