{name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS"}, // extract unsigned <= condition from arg0
{name: "SETA", argLength: 1, reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0
{name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0
+ // Variants that store result to memory
+ {name: "SETEQmem", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETNEmem", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETLmem", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETLEmem", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETGmem", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETGEmem", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETBmem", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETBEmem", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETAmem", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem
+ {name: "SETAEmem", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem
// Need different opcodes for floating point conditions because
// any comparison involving a NaN is always FALSE and thus
// the patterns for inverting conditions cannot be used.
case OpAMD64MOVBloadidx1:
return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v)
case OpAMD64MOVBstore:
- return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v)
+ return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v)
case OpAMD64MOVBstoreconst:
return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v)
case OpAMD64MOVBstoreconstidx1:
return rewriteValueAMD64_OpAMD64SETA_0(v)
case OpAMD64SETAE:
return rewriteValueAMD64_OpAMD64SETAE_0(v)
+ case OpAMD64SETAEmem:
+ return rewriteValueAMD64_OpAMD64SETAEmem_0(v)
+ case OpAMD64SETAmem:
+ return rewriteValueAMD64_OpAMD64SETAmem_0(v)
case OpAMD64SETB:
return rewriteValueAMD64_OpAMD64SETB_0(v)
case OpAMD64SETBE:
return rewriteValueAMD64_OpAMD64SETBE_0(v)
+ case OpAMD64SETBEmem:
+ return rewriteValueAMD64_OpAMD64SETBEmem_0(v)
+ case OpAMD64SETBmem:
+ return rewriteValueAMD64_OpAMD64SETBmem_0(v)
case OpAMD64SETEQ:
return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v)
+ case OpAMD64SETEQmem:
+ return rewriteValueAMD64_OpAMD64SETEQmem_0(v)
case OpAMD64SETG:
return rewriteValueAMD64_OpAMD64SETG_0(v)
case OpAMD64SETGE:
return rewriteValueAMD64_OpAMD64SETGE_0(v)
+ case OpAMD64SETGEmem:
+ return rewriteValueAMD64_OpAMD64SETGEmem_0(v)
+ case OpAMD64SETGmem:
+ return rewriteValueAMD64_OpAMD64SETGmem_0(v)
case OpAMD64SETL:
return rewriteValueAMD64_OpAMD64SETL_0(v)
case OpAMD64SETLE:
return rewriteValueAMD64_OpAMD64SETLE_0(v)
+ case OpAMD64SETLEmem:
+ return rewriteValueAMD64_OpAMD64SETLEmem_0(v)
+ case OpAMD64SETLmem:
+ return rewriteValueAMD64_OpAMD64SETLmem_0(v)
case OpAMD64SETNE:
return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v)
+ case OpAMD64SETNEmem:
+ return rewriteValueAMD64_OpAMD64SETNEmem_0(v)
case OpAMD64SHLL:
return rewriteValueAMD64_OpAMD64SHLL_0(v)
case OpAMD64SHLLconst:
return false
}
func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool {
+ // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem)
+ // cond: y.Uses == 1
+ // result: (SETLmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETL {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem)
+ // cond: y.Uses == 1
+ // result: (SETLEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETLE {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETLEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem)
+ // cond: y.Uses == 1
+ // result: (SETGmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETG {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETGmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem)
+ // cond: y.Uses == 1
+ // result: (SETGEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETGE {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETGEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem)
+ // cond: y.Uses == 1
+ // result: (SETEQmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETEQ {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETEQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem)
+ // cond: y.Uses == 1
+ // result: (SETNEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETNE {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETNEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem)
+ // cond: y.Uses == 1
+ // result: (SETBmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETB {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem)
+ // cond: y.Uses == 1
+ // result: (SETBEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETBE {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETBEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem)
+ // cond: y.Uses == 1
+ // result: (SETAmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETA {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETAmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem)
+ // cond: y.Uses == 1
+ // result: (SETAEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ y := v.Args[1]
+ if y.Op != OpAMD64SETAE {
+ break
+ }
+ x := y.Args[0]
+ mem := v.Args[2]
+ if !(y.Uses == 1) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool {
b := v.Block
_ = b
// match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem)
}
return false
}
-func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool {
+func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool {
b := v.Block
_ = b
typ := &b.Func.Config.Types
}
return false
}
+func rewriteValueAMD64_OpAMD64SETAEmem_0(v *Value) bool {
+ // match: (SETAEmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETBEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETBEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64SETAmem_0(v *Value) bool {
+ // match: (SETAmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETBmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64SETB_0(v *Value) bool {
// match: (SETB (InvertFlags x))
// cond:
}
return false
}
+func rewriteValueAMD64_OpAMD64SETBEmem_0(v *Value) bool {
+ // match: (SETBEmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETAEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64SETBmem_0(v *Value) bool {
+ // match: (SETBmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETAmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETAmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64SETEQ_0(v *Value) bool {
b := v.Block
_ = b
}
return false
}
+func rewriteValueAMD64_OpAMD64SETEQmem_0(v *Value) bool {
+ b := v.Block
+ _ = b
+ config := b.Func.Config
+ _ = config
+ // match: (SETEQmem [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
+ // cond: !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTL x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTL {
+ break
+ }
+ _ = v_1.Args[1]
+ v_1_0 := v_1.Args[0]
+ if v_1_0.Op != OpAMD64SHLL {
+ break
+ }
+ _ = v_1_0.Args[1]
+ v_1_0_0 := v_1_0.Args[0]
+ if v_1_0_0.Op != OpAMD64MOVLconst {
+ break
+ }
+ if v_1_0_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_0.Args[1]
+ y := v_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem)
+ // cond: !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTL x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTL {
+ break
+ }
+ _ = v_1.Args[1]
+ y := v_1.Args[0]
+ v_1_1 := v_1.Args[1]
+ if v_1_1.Op != OpAMD64SHLL {
+ break
+ }
+ _ = v_1_1.Args[1]
+ v_1_1_0 := v_1_1.Args[0]
+ if v_1_1_0.Op != OpAMD64MOVLconst {
+ break
+ }
+ if v_1_1_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
+ // cond: !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTQ x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ v_1_0 := v_1.Args[0]
+ if v_1_0.Op != OpAMD64SHLQ {
+ break
+ }
+ _ = v_1_0.Args[1]
+ v_1_0_0 := v_1_0.Args[0]
+ if v_1_0_0.Op != OpAMD64MOVQconst {
+ break
+ }
+ if v_1_0_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_0.Args[1]
+ y := v_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem)
+ // cond: !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTQ x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ y := v_1.Args[0]
+ v_1_1 := v_1.Args[1]
+ if v_1_1.Op != OpAMD64SHLQ {
+ break
+ }
+ _ = v_1_1.Args[1]
+ v_1_1_0 := v_1_1.Args[0]
+ if v_1_1_0.Op != OpAMD64MOVQconst {
+ break
+ }
+ if v_1_1_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTLconst [c] x) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTLconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTLconst {
+ break
+ }
+ c := v_1.AuxInt
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTQconst [c] x) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQconst {
+ break
+ }
+ c := v_1.AuxInt
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ v_1_0 := v_1.Args[0]
+ if v_1_0.Op != OpAMD64MOVQconst {
+ break
+ }
+ c := v_1_0.AuxInt
+ x := v_1.Args[1]
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // result: (SETAEmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ x := v_1.Args[0]
+ v_1_1 := v_1.Args[1]
+ if v_1_1.Op != OpAMD64MOVQconst {
+ break
+ }
+ c := v_1_1.AuxInt
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETAEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETEQmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETEQmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETEQmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64SETG_0(v *Value) bool {
// match: (SETG (InvertFlags x))
// cond:
}
return false
}
+func rewriteValueAMD64_OpAMD64SETGEmem_0(v *Value) bool {
+ // match: (SETGEmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETLEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETLEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64SETGmem_0(v *Value) bool {
+ // match: (SETGmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETLmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETLmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64SETL_0(v *Value) bool {
// match: (SETL (InvertFlags x))
// cond:
}
return false
}
+func rewriteValueAMD64_OpAMD64SETLEmem_0(v *Value) bool {
+ // match: (SETLEmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETGEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETGEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
+func rewriteValueAMD64_OpAMD64SETLmem_0(v *Value) bool {
+ // match: (SETLmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETGmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETGmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64SETNE_0(v *Value) bool {
b := v.Block
_ = b
}
return false
}
+func rewriteValueAMD64_OpAMD64SETNEmem_0(v *Value) bool {
+ b := v.Block
+ _ = b
+ config := b.Func.Config
+ _ = config
+ // match: (SETNEmem [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
+ // cond: !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTL x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTL {
+ break
+ }
+ _ = v_1.Args[1]
+ v_1_0 := v_1.Args[0]
+ if v_1_0.Op != OpAMD64SHLL {
+ break
+ }
+ _ = v_1_0.Args[1]
+ v_1_0_0 := v_1_0.Args[0]
+ if v_1_0_0.Op != OpAMD64MOVLconst {
+ break
+ }
+ if v_1_0_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_0.Args[1]
+ y := v_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem)
+ // cond: !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTL x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTL {
+ break
+ }
+ _ = v_1.Args[1]
+ y := v_1.Args[0]
+ v_1_1 := v_1.Args[1]
+ if v_1_1.Op != OpAMD64SHLL {
+ break
+ }
+ _ = v_1_1.Args[1]
+ v_1_1_0 := v_1_1.Args[0]
+ if v_1_1_0.Op != OpAMD64MOVLconst {
+ break
+ }
+ if v_1_1_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
+ // cond: !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTQ x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ v_1_0 := v_1.Args[0]
+ if v_1_0.Op != OpAMD64SHLQ {
+ break
+ }
+ _ = v_1_0.Args[1]
+ v_1_0_0 := v_1_0.Args[0]
+ if v_1_0_0.Op != OpAMD64MOVQconst {
+ break
+ }
+ if v_1_0_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_0.Args[1]
+ y := v_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem)
+ // cond: !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTQ x y) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ y := v_1.Args[0]
+ v_1_1 := v_1.Args[1]
+ if v_1_1.Op != OpAMD64SHLQ {
+ break
+ }
+ _ = v_1_1.Args[1]
+ v_1_1_0 := v_1_1.Args[0]
+ if v_1_1_0.Op != OpAMD64MOVQconst {
+ break
+ }
+ if v_1_1_0.AuxInt != 1 {
+ break
+ }
+ x := v_1_1.Args[1]
+ mem := v.Args[2]
+ if !(!config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
+ v0.AddArg(x)
+ v0.AddArg(y)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTLconst [c] x) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 32 && !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTLconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTLconst {
+ break
+ }
+ c := v_1.AuxInt
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 32 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTQconst [c] x) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQconst {
+ break
+ }
+ c := v_1.AuxInt
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ v_1_0 := v_1.Args[0]
+ if v_1_0.Op != OpAMD64MOVQconst {
+ break
+ }
+ c := v_1_0.AuxInt
+ x := v_1.Args[1]
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem)
+ // cond: isPowerOfTwo(c) && log2(c) < 64 && !config.nacl
+ // result: (SETBmem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64TESTQ {
+ break
+ }
+ _ = v_1.Args[1]
+ x := v_1.Args[0]
+ v_1_1 := v_1.Args[1]
+ if v_1_1.Op != OpAMD64MOVQconst {
+ break
+ }
+ c := v_1_1.AuxInt
+ mem := v.Args[2]
+ if !(isPowerOfTwo(c) && log2(c) < 64 && !config.nacl) {
+ break
+ }
+ v.reset(OpAMD64SETBmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
+ v0.AuxInt = log2(c)
+ v0.AddArg(x)
+ v.AddArg(v0)
+ v.AddArg(mem)
+ return true
+ }
+ // match: (SETNEmem [off] {sym} ptr (InvertFlags x) mem)
+ // cond:
+ // result: (SETNEmem [off] {sym} ptr x mem)
+ for {
+ off := v.AuxInt
+ sym := v.Aux
+ _ = v.Args[2]
+ ptr := v.Args[0]
+ v_1 := v.Args[1]
+ if v_1.Op != OpAMD64InvertFlags {
+ break
+ }
+ x := v_1.Args[0]
+ mem := v.Args[2]
+ v.reset(OpAMD64SETNEmem)
+ v.AuxInt = off
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(x)
+ v.AddArg(mem)
+ return true
+ }
+ return false
+}
func rewriteValueAMD64_OpAMD64SHLL_0(v *Value) bool {
b := v.Block
_ = b