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cmd/compile: remove dots from register names
authorKeith Randall <khr@golang.org>
Tue, 22 Mar 2016 16:43:28 +0000 (09:43 -0700)
committerKeith Randall <khr@golang.org>
Tue, 22 Mar 2016 17:30:30 +0000 (17:30 +0000)
They are kind of useless and are cluttering up
https://go-review.googlesource.com/c/21000/

Change-Id: Iafdec75ada11c7ebdc40540d251fdc514bb00d3d
Reviewed-on: https://go-review.googlesource.com/21001
Reviewed-by: Minux Ma <minux@golang.org>
src/cmd/compile/internal/ssa/gen/AMD64Ops.go patch | blob | history
src/cmd/compile/internal/ssa/opGen.go patch | blob | history

diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index 5d9902b5cc890ca0c5daa75383a5edcea372a756..596b5c31cb05793b6da0071bd8821aea2ce6cbf0 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -8,42 +8,42 @@ import "strings"
 
 // copied from ../../amd64/reg.go
 var regNamesAMD64 = []string{
-       ".AX",
-       ".CX",
-       ".DX",
-       ".BX",
-       ".SP",
-       ".BP",
-       ".SI",
-       ".DI",
-       ".R8",
-       ".R9",
-       ".R10",
-       ".R11",
-       ".R12",
-       ".R13",
-       ".R14",
-       ".R15",
-       ".X0",
-       ".X1",
-       ".X2",
-       ".X3",
-       ".X4",
-       ".X5",
-       ".X6",
-       ".X7",
-       ".X8",
-       ".X9",
-       ".X10",
-       ".X11",
-       ".X12",
-       ".X13",
-       ".X14",
-       ".X15",
+       "AX",
+       "CX",
+       "DX",
+       "BX",
+       "SP",
+       "BP",
+       "SI",
+       "DI",
+       "R8",
+       "R9",
+       "R10",
+       "R11",
+       "R12",
+       "R13",
+       "R14",
+       "R15",
+       "X0",
+       "X1",
+       "X2",
+       "X3",
+       "X4",
+       "X5",
+       "X6",
+       "X7",
+       "X8",
+       "X9",
+       "X10",
+       "X11",
+       "X12",
+       "X13",
+       "X14",
+       "X15",
 
        // pseudo-registers
-       ".SB",
-       ".FLAGS",
+       "SB",
+       "FLAGS",
 }
 
 func init() {
@@ -53,10 +53,7 @@ func init() {
        }
        num := map[string]int{}
        for i, name := range regNamesAMD64 {
-               if name[0] != '.' {
-                       panic("register name " + name + " does not start with '.'")
-               }
-               num[name[1:]] = i
+               num[name] = i
        }
        buildReg := func(s string) regMask {
                m := regMask(0)
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 99c851d52e89a28eb5d4b3e6d4b64869b0461acb..1164b447b64774348252f1277172177b71969c69 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -598,11 +598,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -614,11 +614,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -629,12 +629,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
-                               {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       clobbers: 2147483648, // .X15
+                       clobbers: 2147483648, // X15
                        outputs: []regMask{
-                               2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
@@ -645,12 +645,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
-                               {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       clobbers: 2147483648, // .X15
+                       clobbers: 2147483648, // X15
                        outputs: []regMask{
-                               2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
@@ -662,11 +662,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AMULSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -678,11 +678,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AMULSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -693,12 +693,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ADIVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
-                               {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       clobbers: 2147483648, // .X15
+                       clobbers: 2147483648, // X15
                        outputs: []regMask{
-                               2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
@@ -709,12 +709,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ADIVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
-                               {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
-                       clobbers: 2147483648, // .X15
+                       clobbers: 2147483648, // X15
                        outputs: []regMask{
-                               2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
+                               2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
                        },
                },
        },
@@ -725,10 +725,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -739,10 +739,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -754,7 +754,7 @@ var opcodeTable = [...]opInfo{
                asm:               x86.AMOVSS,
                reg: regInfo{
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -766,7 +766,7 @@ var opcodeTable = [...]opInfo{
                asm:               x86.AMOVSD,
                reg: regInfo{
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -777,11 +777,11 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -792,11 +792,11 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -807,8 +807,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -819,8 +819,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -831,9 +831,9 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -844,9 +844,9 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -858,12 +858,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -875,12 +875,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -892,12 +892,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -909,12 +909,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -926,11 +926,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -942,11 +942,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -958,11 +958,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -974,11 +974,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AADDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -989,12 +989,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1005,12 +1005,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1021,12 +1021,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1037,12 +1037,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1054,11 +1054,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1070,11 +1070,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1086,11 +1086,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1102,11 +1102,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1118,12 +1118,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1135,12 +1135,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1152,12 +1152,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1169,12 +1169,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1186,11 +1186,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1202,11 +1202,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1218,11 +1218,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1234,11 +1234,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AIMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1248,12 +1248,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIMULQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1263,12 +1263,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIMULL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1278,12 +1278,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1293,12 +1293,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIMULB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1308,12 +1308,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMULQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1323,12 +1323,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMULL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1338,12 +1338,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMULW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1353,12 +1353,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMULB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1369,12 +1369,12 @@ var opcodeTable = [...]opInfo{
                resultInArg0: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1384,12 +1384,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIDIVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934596, // .DX .FLAGS
+                       clobbers: 8589934596, // DX FLAGS
                        outputs: []regMask{
-                               1, // .AX
+                               1, // AX
                        },
                },
        },
@@ -1399,12 +1399,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIDIVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934596, // .DX .FLAGS
+                       clobbers: 8589934596, // DX FLAGS
                        outputs: []regMask{
-                               1, // .AX
+                               1, // AX
                        },
                },
        },
@@ -1414,12 +1414,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIDIVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934596, // .DX .FLAGS
+                       clobbers: 8589934596, // DX FLAGS
                        outputs: []regMask{
-                               1, // .AX
+                               1, // AX
                        },
                },
        },
@@ -1429,12 +1429,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ADIVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934596, // .DX .FLAGS
+                       clobbers: 8589934596, // DX FLAGS
                        outputs: []regMask{
-                               1, // .AX
+                               1, // AX
                        },
                },
        },
@@ -1444,12 +1444,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ADIVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934596, // .DX .FLAGS
+                       clobbers: 8589934596, // DX FLAGS
                        outputs: []regMask{
-                               1, // .AX
+                               1, // AX
                        },
                },
        },
@@ -1459,12 +1459,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ADIVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934596, // .DX .FLAGS
+                       clobbers: 8589934596, // DX FLAGS
                        outputs: []regMask{
-                               1, // .AX
+                               1, // AX
                        },
                },
        },
@@ -1474,12 +1474,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIDIVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1489,12 +1489,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIDIVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1504,12 +1504,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AIDIVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1519,12 +1519,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ADIVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1534,12 +1534,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ADIVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1549,12 +1549,12 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ADIVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 1},     // .AX
-                               {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 1},     // AX
+                               {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -1566,12 +1566,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1583,12 +1583,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1600,12 +1600,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1617,12 +1617,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1634,11 +1634,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1650,11 +1650,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1666,11 +1666,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1682,11 +1682,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AANDL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1698,12 +1698,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1715,12 +1715,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1732,12 +1732,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1749,12 +1749,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1766,11 +1766,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1782,11 +1782,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1798,11 +1798,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1814,11 +1814,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1830,12 +1830,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1847,12 +1847,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1864,12 +1864,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1881,12 +1881,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1898,11 +1898,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1914,11 +1914,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1930,11 +1930,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1946,11 +1946,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AXORL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -1960,11 +1960,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -1974,11 +1974,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACMPL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -1988,11 +1988,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2002,11 +2002,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2017,10 +2017,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ACMPQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2031,10 +2031,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ACMPL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2045,10 +2045,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ACMPW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2059,10 +2059,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ACMPB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2072,11 +2072,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AUCOMISS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2086,11 +2086,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AUCOMISD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2100,11 +2100,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ATESTQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2114,11 +2114,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ATESTL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2128,11 +2128,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ATESTW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2142,11 +2142,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ATESTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2157,10 +2157,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ATESTQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2171,10 +2171,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ATESTL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2185,10 +2185,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ATESTW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2199,10 +2199,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.ATESTB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               8589934592, // .FLAGS
+                               8589934592, // FLAGS
                        },
                },
        },
@@ -2213,12 +2213,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2229,12 +2229,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2245,12 +2245,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2261,12 +2261,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2278,11 +2278,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2294,11 +2294,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2310,11 +2310,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2326,11 +2326,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2341,12 +2341,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2357,12 +2357,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2373,12 +2373,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2389,12 +2389,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2406,11 +2406,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2422,11 +2422,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2438,11 +2438,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2454,11 +2454,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASHRB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2469,12 +2469,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2485,12 +2485,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2501,12 +2501,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2517,12 +2517,12 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 2},     // .CX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 2},     // CX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2534,11 +2534,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2550,11 +2550,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2566,11 +2566,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2582,11 +2582,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASARB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2598,11 +2598,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AROLQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2614,11 +2614,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AROLL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2630,11 +2630,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AROLW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2646,11 +2646,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.AROLB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2661,11 +2661,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANEGQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2676,11 +2676,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANEGL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2691,11 +2691,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANEGL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2706,11 +2706,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANEGL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2721,11 +2721,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANOTQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2736,11 +2736,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANOTL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2751,11 +2751,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANOTL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2766,11 +2766,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ANOTL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2780,10 +2780,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASQRTSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -2793,10 +2793,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASBBQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2806,10 +2806,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASBBL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2819,10 +2819,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2832,10 +2832,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETNE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2845,10 +2845,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETLT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2858,10 +2858,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETLE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2871,10 +2871,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETGT,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2884,10 +2884,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETGE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2897,10 +2897,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETCS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2910,10 +2910,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETLS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2923,10 +2923,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETHI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2936,10 +2936,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2949,11 +2949,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETEQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2963,11 +2963,11 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETNE,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
-                       clobbers: 8589934593, // .AX .FLAGS
+                       clobbers: 8589934593, // AX FLAGS
                        outputs: []regMask{
-                               65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2977,10 +2977,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETPC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -2990,10 +2990,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3003,10 +3003,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETHI,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3016,10 +3016,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ASETCC,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 8589934592}, // .FLAGS
+                               {0, 8589934592}, // FLAGS
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3029,10 +3029,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVBQSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3042,10 +3042,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVBQZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3055,10 +3055,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVWQSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3068,10 +3068,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVWQZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3081,10 +3081,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVLQSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3094,10 +3094,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVLQZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3109,7 +3109,7 @@ var opcodeTable = [...]opInfo{
                asm:               x86.AMOVB,
                reg: regInfo{
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3121,7 +3121,7 @@ var opcodeTable = [...]opInfo{
                asm:               x86.AMOVW,
                reg: regInfo{
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3133,7 +3133,7 @@ var opcodeTable = [...]opInfo{
                asm:               x86.AMOVL,
                reg: regInfo{
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3145,7 +3145,7 @@ var opcodeTable = [...]opInfo{
                asm:               x86.AMOVQ,
                reg: regInfo{
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3155,10 +3155,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTTSD2SL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3168,10 +3168,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTTSD2SQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3181,10 +3181,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTTSS2SL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3194,10 +3194,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTTSS2SQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3207,10 +3207,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTSL2SS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3220,10 +3220,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTSL2SD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3233,10 +3233,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTSQ2SS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3246,10 +3246,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTSQ2SD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3259,10 +3259,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTSD2SS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3272,10 +3272,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.ACVTSS2SD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3287,11 +3287,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.APXOR,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3302,10 +3302,10 @@ var opcodeTable = [...]opInfo{
                rematerializeable: true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3315,11 +3315,11 @@ var opcodeTable = [...]opInfo{
                argLen:  2,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3329,11 +3329,11 @@ var opcodeTable = [...]opInfo{
                argLen:  2,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3343,11 +3343,11 @@ var opcodeTable = [...]opInfo{
                argLen:  2,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3357,11 +3357,11 @@ var opcodeTable = [...]opInfo{
                argLen:  2,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3372,10 +3372,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVBLZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3386,10 +3386,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVBQSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3400,10 +3400,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVBLZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3414,10 +3414,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVWLZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3428,10 +3428,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVWQSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3442,10 +3442,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVWLZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3456,10 +3456,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3470,10 +3470,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVLQSX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3484,10 +3484,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3498,10 +3498,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3512,8 +3512,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3524,8 +3524,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3536,8 +3536,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3548,8 +3548,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3560,10 +3560,10 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVUPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3574,8 +3574,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVUPS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3586,11 +3586,11 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVBLZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3601,11 +3601,11 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVWLZX,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3616,11 +3616,11 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3631,11 +3631,11 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3646,9 +3646,9 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {2, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3659,9 +3659,9 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {2, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3672,9 +3672,9 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {2, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3685,9 +3685,9 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {2, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3698,7 +3698,7 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3709,7 +3709,7 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3720,7 +3720,7 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3731,7 +3731,7 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3742,8 +3742,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVB,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3754,8 +3754,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVW,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3766,8 +3766,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVL,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3778,8 +3778,8 @@ var opcodeTable = [...]opInfo{
                asm:     x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 65535},      // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
-                               {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
+                               {1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
+                               {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
                        },
                },
        },
@@ -3789,10 +3789,10 @@ var opcodeTable = [...]opInfo{
                argLen:  3,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 128},   // .DI
-                               {1, 65536}, // .X0
+                               {0, 128},   // DI
+                               {1, 65536}, // X0
                        },
-                       clobbers: 8589934720, // .DI .FLAGS
+                       clobbers: 8589934720, // DI FLAGS
                },
        },
        {
@@ -3801,7 +3801,7 @@ var opcodeTable = [...]opInfo{
                rematerializeable: true,
                reg: regInfo{
                        outputs: []regMask{
-                               4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
+                               4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3810,11 +3810,11 @@ var opcodeTable = [...]opInfo{
                argLen: 4,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 128}, // .DI
-                               {1, 2},   // .CX
-                               {2, 1},   // .AX
+                               {0, 128}, // DI
+                               {1, 2},   // CX
+                               {2, 1},   // AX
                        },
-                       clobbers: 130, // .CX .DI
+                       clobbers: 130, // CX DI
                },
        },
        {
@@ -3822,7 +3822,7 @@ var opcodeTable = [...]opInfo{
                auxType: auxSymOff,
                argLen:  1,
                reg: regInfo{
-                       clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
+                       clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
                },
        },
        {
@@ -3831,10 +3831,10 @@ var opcodeTable = [...]opInfo{
                argLen:  3,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 4},     // .DX
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {1, 4},     // DX
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
+                       clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
                },
        },
        {
@@ -3842,7 +3842,7 @@ var opcodeTable = [...]opInfo{
                auxType: auxInt64,
                argLen:  1,
                reg: regInfo{
-                       clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
+                       clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
                },
        },
        {
@@ -3850,7 +3850,7 @@ var opcodeTable = [...]opInfo{
                auxType: auxInt64,
                argLen:  1,
                reg: regInfo{
-                       clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
+                       clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
                },
        },
        {
@@ -3859,9 +3859,9 @@ var opcodeTable = [...]opInfo{
                argLen:  2,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
+                       clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
                },
        },
        {
@@ -3870,10 +3870,10 @@ var opcodeTable = [...]opInfo{
                argLen:  3,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 128}, // .DI
-                               {1, 64},  // .SI
+                               {0, 128}, // DI
+                               {1, 64},  // SI
                        },
-                       clobbers: 8590000320, // .SI .DI .X0 .FLAGS
+                       clobbers: 8590000320, // SI DI X0 FLAGS
                },
        },
        {
@@ -3881,11 +3881,11 @@ var opcodeTable = [...]opInfo{
                argLen: 4,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 128}, // .DI
-                               {1, 64},  // .SI
-                               {2, 2},   // .CX
+                               {0, 128}, // DI
+                               {1, 64},  // SI
+                               {2, 2},   // CX
                        },
-                       clobbers: 194, // .CX .SI .DI
+                       clobbers: 194, // CX SI DI
                },
        },
        {
@@ -3898,7 +3898,7 @@ var opcodeTable = [...]opInfo{
                argLen: 1,
                reg: regInfo{
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
@@ -3907,7 +3907,7 @@ var opcodeTable = [...]opInfo{
                argLen: 0,
                reg: regInfo{
                        outputs: []regMask{
-                               4, // .DX
+                               4, // DX
                        },
                },
        },
@@ -3916,9 +3916,9 @@ var opcodeTable = [...]opInfo{
                argLen: 2,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
-                       clobbers: 8589934592, // .FLAGS
+                       clobbers: 8589934592, // FLAGS
                },
        },
        {
@@ -3927,10 +3927,10 @@ var opcodeTable = [...]opInfo{
                asm:    x86.AMOVQ,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                        outputs: []regMask{
-                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                               65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
                        },
                },
        },
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