XVBITREVV $63, X2, X1 // 41fc1977
// ALSL{W/WU/D}
- ALSLW $3, R4, R5, R6 // 86940500
- ALSLWU $3, R4, R5, R6 // 86940700
- ALSLV $3, R4, R5, R6 // 86942d00
+ ALSLW $4, R4, R5, R6 // 86940500
+ ALSLWU $4, R4, R5, R6 // 86940700
+ ALSLV $4, R4, R5, R6 // 86942d00
{APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
{APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
- {AALSLV, C_U2CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
+ {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
{obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
{obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
case 64: // alsl rd, rj, rk, sa2
+ sa := p.From.Offset - 1
+ if sa > 3 {
+ c.ctxt.Diag("The shift amount is too large.")
+ }
r := p.GetFrom3().Reg
- o1 = OP_2IRRR(c.opirrr(p.As), uint32(p.From.Offset), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
+ o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
case 65: // mov sym@GOT, r ==> pcalau12i + ld.d
o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
bits[11:1]: block size, the value range is [16, 1024], and it must be an integer multiple of 16
bits[20:12]: block num, the value range is [1, 256]
bits[36:21]: stride, the value range is [0, 0xffff]
+
+4. ShiftAdd instructions
+ Mapping between Go and platform assembly:
+ Go assembly | platform assembly
+ ALSL.W/WU/V $Imm, Rj, Rk, Rd | alsl.w/wu/d rd, rj, rk, $imm
+
+ Instruction encoding format is as follows:
+
+ | 31 ~ 17 | 16 ~ 15 | 14 ~ 10 | 9 ~ 5 | 4 ~ 0 |
+ | opcode | sa2 | rk | rj | rd |
+
+ The alsl.w/wu/v series of instructions shift the data in rj left by sa+1, add the value
+ in rk, and write the result to rd.
+
+ To allow programmers to directly write the desired shift amount in assembly code, we actually write
+ the value of sa2+1 in the assembly code and then include the value of sa2 in the instruction encoding.
+
+ For example:
+
+ Go assembly | instruction Encoding
+ ALSLV $4, r4, r5, R6 | 002d9486
*/
package loong64