if aux != "" {
rr.add(stmtf("%s.Aux = %s", v, aux))
}
- for _, arg := range args {
+ all := new(strings.Builder)
+ for i, arg := range args {
x := genResult0(rr, arch, arg, false, move, pos)
- rr.add(stmtf("%s.AddArg(%s)", v, x))
+ if i > 0 {
+ all.WriteString(", ")
+ }
+ all.WriteString(x)
+ }
+ switch len(args) {
+ case 0:
+ case 1:
+ rr.add(stmtf("%s.AddArg(%s)", v, all.String()))
+ default:
+ rr.add(stmtf("%s.AddArg%d(%s)", v, len(args), all.String()))
}
-
return v
}
f := v_2
v.reset(Op386ADCLconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(f)
+ v.AddArg2(x, f)
return true
}
break
}
y := v_1.Args[0]
v.reset(Op386LEAL8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(Op386LEAL4)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(Op386LEAL2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(Op386LEAL2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1_1
v.reset(Op386LEAL2)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
y := v_1
v.reset(Op386LEAL1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL1)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386ADDLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386ADDLloadidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(x, ptr, idx, mem)
return true
}
break
}
y := v_1.Args[0]
v.reset(Op386SUBL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
x := v_0.Args[0]
v.reset(Op386LEAL1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL [d] {s} x))
v.reset(Op386LEAL1)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
v.reset(Op386LEAL2)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
v.reset(Op386LEAL4)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
v.reset(Op386LEAL8)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] x)
v.reset(Op386ADDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386ADDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (ADDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (ADDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
return false
v.reset(Op386ADDLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386ADDLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, ptr, idx, mem)
return true
}
return false
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (ADDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (ADDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
return false
v.reset(Op386ADDLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386ADDLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ADDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ADDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ADDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386ADDSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386ADDSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386ADDSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386ADDSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386ADDSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386ADDSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386ANDLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386ANDLloadidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(x, ptr, idx, mem)
return true
}
break
v.reset(Op386ANDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386ANDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (ANDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (ANDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
return false
v.reset(Op386ANDLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386ANDLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ANDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, ptr, idx, mem)
return true
}
return false
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (ANDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (ANDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
return false
v.reset(Op386ANDLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386ANDLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ANDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ANDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ANDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(Op386InvertFlags)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(Op386CMPBload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, Op386CMPBload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
break
}
v.reset(Op386TESTB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPBconst l:(ANDLconst [c] x) [0])
}
x := v_0
v.reset(Op386TESTB)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(Op386CMPBconstload)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(Op386InvertFlags)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(Op386CMPLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, Op386CMPLload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
break
}
v.reset(Op386TESTL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPLconst l:(ANDLconst [c] x) [0])
}
x := v_0
v.reset(Op386TESTL)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(Op386CMPLconstload)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(Op386InvertFlags)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(Op386CMPWload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, Op386CMPWload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
break
}
v.reset(Op386TESTW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWconst l:(ANDLconst [c] x) [0])
}
x := v_0
v.reset(Op386TESTW)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(Op386CMPWconstload)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(Op386DIVSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(Op386DIVSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (DIVSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386DIVSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386DIVSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(Op386DIVSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (DIVSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386DIVSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386LEAL1)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y))
v.reset(Op386LEAL2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y))
v.reset(Op386LEAL4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y))
v.reset(Op386LEAL8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(Op386LEAL1)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL2)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL4)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(Op386LEAL2)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
v.reset(Op386LEAL2)
v.AuxInt = c + 2*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [c] {s} x (SHLLconst [1] y))
v.reset(Op386LEAL4)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
v.reset(Op386LEAL8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y)
v.reset(Op386LEAL2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(Op386LEAL4)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
v.reset(Op386LEAL4)
v.AuxInt = c + 4*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL4 [c] {s} x (SHLLconst [1] y))
v.reset(Op386LEAL8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y)
v.reset(Op386LEAL4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(Op386LEAL8)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
v.reset(Op386LEAL8)
v.AuxInt = c + 8*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y)
v.reset(Op386LEAL8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBLSX (ANDLconst [c] x))
v.reset(Op386MOVBLSXload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBLZX x:(MOVBloadidx1 [off] {sym} ptr idx mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBLZX (ANDLconst [c] x))
v.reset(Op386MOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386MOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVBloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBload [off] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVBloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVBloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVBloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBLZX x) mem)
v.reset(Op386MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
v.reset(Op386MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
v.reset(Op386MOVBstoreconst)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVBstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVBstore [off] {sym} (ADDL ptr idx) val mem)
v.reset(Op386MOVBstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
v.reset(Op386MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRWconst [8] w) mem))
v.reset(Op386MOVWstore)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRLconst [8] w) mem))
v.reset(Op386MOVWstore)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem))
v.reset(Op386MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
return false
v.reset(Op386MOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(Op386MOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
v.reset(Op386MOVBstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreconst [x] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVBstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
v.reset(Op386MOVWstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
// match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem))
v.reset(Op386MOVWstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(Op386MOVBstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
v.reset(Op386MOVBstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem))
v.reset(Op386MOVWstoreconstidx1)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(i)
- v.AddArg(mem)
+ v.AddArg3(p, i, mem)
return true
}
return false
v.reset(Op386MOVBstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVBstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(Op386MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(Op386MOVWstoreidx1)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(Op386MOVWstoreidx1)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(Op386MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(Op386MOVLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386MOVLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVLloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLload [off] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVLloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVLloadidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVLloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVLloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVLloadidx4)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem)
v.reset(Op386MOVLloadidx4)
v.AuxInt = int64(int32(c + 4*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVLstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem)
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386MOVLstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVLstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVLstoreidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstore [off] {sym} (ADDL ptr idx) val mem)
v.reset(Op386MOVLstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386ADDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem)
v.reset(Op386ANDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem)
v.reset(Op386ORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem)
v.reset(Op386XORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem)
v.reset(Op386ADDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(Op386SUBLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem)
v.reset(Op386ANDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(Op386ORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(Op386XORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(Op386ADDLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ANDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
v.reset(Op386ANDLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
v.reset(Op386ORLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(XORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
v.reset(Op386XORLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(Op386MOVLstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(Op386MOVLstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
v.reset(Op386MOVLstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconst [x] {sym1} (LEAL4 [off] {sym2} ptr idx) mem)
v.reset(Op386MOVLstoreconstidx4)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconst [x] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVLstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVLstoreconstidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
v.reset(Op386MOVLstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
v.reset(Op386MOVLstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVLstoreconstidx4)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDLconst [c] idx) mem)
v.reset(Op386MOVLstoreconstidx4)
v.AuxInt = ValAndOff(x).add(4 * c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVLstoreidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVLstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVLstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVLstoreidx4)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem)
v.reset(Op386MOVLstoreidx4)
v.AuxInt = int64(int32(c + 4*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLloadidx4 x [off] {sym} ptr idx mem) mem)
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLloadidx4 x [off] {sym} ptr idx mem) mem)
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLloadidx4 x [off] {sym} ptr idx mem) mem)
v.reset(Op386ORLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLloadidx4 x [off] {sym} ptr idx mem) mem)
v.reset(Op386XORLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
break
v.reset(Op386SUBLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem)
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
break
v.reset(Op386ORLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
break
v.reset(Op386XORLmodifyidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
break
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
v.reset(Op386ORLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem)
v.reset(Op386XORLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386MOVSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVSDload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVSDloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDload [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVSDloadidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDload [off] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVSDloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVSDloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
v.reset(Op386MOVSDloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVSDloadidx8)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx8 [c] {sym} ptr (ADDLconst [d] idx) mem)
v.reset(Op386MOVSDloadidx8)
v.AuxInt = int64(int32(c + 8*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVSDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386MOVSDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVSDstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVSDstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVSDstoreidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstore [off] {sym} (ADDL ptr idx) val mem)
v.reset(Op386MOVSDstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVSDstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
v.reset(Op386MOVSDstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
v.reset(Op386MOVSDstoreidx8)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem)
v.reset(Op386MOVSDstoreidx8)
v.AuxInt = int64(int32(c + 8*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
v.reset(Op386MOVSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386MOVSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVSSload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVSSloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVSSloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSload [off] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVSSloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVSSloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem)
v.reset(Op386MOVSSloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVSSloadidx4)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem)
v.reset(Op386MOVSSloadidx4)
v.AuxInt = int64(int32(c + 4*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVSSstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386MOVSSstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVSSstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVSSstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVSSstoreidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstore [off] {sym} (ADDL ptr idx) val mem)
v.reset(Op386MOVSSstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVSSstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem)
v.reset(Op386MOVSSstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
v.reset(Op386MOVSSstoreidx4)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem)
v.reset(Op386MOVSSstoreidx4)
v.AuxInt = int64(int32(c + 4*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWLSX (ANDLconst [c] x))
v.reset(Op386MOVWLSXload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWLZX x:(MOVWloadidx1 [off] {sym} ptr idx mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWLZX x:(MOVWloadidx2 [off] {sym} ptr idx mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWLZX (ANDLconst [c] x))
v.reset(Op386MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVWloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) mem)
v.reset(Op386MOVWloadidx2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVWloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVWloadidx2)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVWloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVWloadidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(Op386MOVWloadidx2)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx2 [c] {sym} ptr (ADDLconst [d] idx) mem)
v.reset(Op386MOVWloadidx2)
v.AuxInt = int64(int32(c + 2*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWLZX x) mem)
v.reset(Op386MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
v.reset(Op386MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem)
v.reset(Op386MOVWstoreconst)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVWstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) val mem)
v.reset(Op386MOVWstoreidx2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off] {sym} (ADDL ptr idx) val mem)
v.reset(Op386MOVWstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem))
v.reset(Op386MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
return false
v.reset(Op386MOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(Op386MOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem)
v.reset(Op386MOVWstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconst [x] {sym1} (LEAL2 [off] {sym2} ptr idx) mem)
v.reset(Op386MOVWstoreconstidx2)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconst [x] {sym} (ADDL ptr idx) mem)
v.reset(Op386MOVWstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem))
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
// match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem))
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(Op386MOVWstoreconstidx2)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem)
v.reset(Op386MOVWstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem)
v.reset(Op386MOVWstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem))
v.reset(Op386MOVLstoreconstidx1)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(i)
- v.AddArg(mem)
+ v.AddArg3(p, i, mem)
return true
}
return false
v.reset(Op386MOVWstoreconstidx2)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDLconst [c] idx) mem)
v.reset(Op386MOVWstoreconstidx2)
v.AuxInt = ValAndOff(x).add(2 * c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem))
v.reset(Op386MOVLstoreconstidx1)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, i.Type)
v0.AuxInt = 1
v0.AddArg(i)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
return false
v.reset(Op386MOVWstoreidx2)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVWstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVWstoreidx1)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(Op386MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(Op386MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(Op386MOVWstoreidx2)
v.AuxInt = int64(int32(c + d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx2 [c] {sym} ptr (ADDLconst [d] idx) val mem)
v.reset(Op386MOVWstoreidx2)
v.AuxInt = int64(int32(c + 2*d))
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem))
v.reset(Op386MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type)
v0.AuxInt = 1
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w, mem)
return true
}
// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem))
v.reset(Op386MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type)
v0.AuxInt = 1
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w0, mem)
return true
}
return false
v.reset(Op386MULLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386MULLloadidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(x, ptr, idx, mem)
return true
}
break
x := v_0
v.reset(Op386NEGL)
v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(Op386NEGL)
v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(Op386NEGL)
v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
}
x := v_0
v.reset(Op386LEAL2)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULLconst [5] x)
}
x := v_0
v.reset(Op386LEAL4)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULLconst [7] x)
}
x := v_0
v.reset(Op386LEAL2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [9] x)
}
x := v_0
v.reset(Op386LEAL8)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULLconst [11] x)
}
x := v_0
v.reset(Op386LEAL2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [13] x)
}
x := v_0
v.reset(Op386LEAL4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [19] x)
}
x := v_0
v.reset(Op386LEAL2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [21] x)
}
x := v_0
v.reset(Op386LEAL4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [25] x)
}
x := v_0
v.reset(Op386LEAL8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [27] x)
x := v_0
v.reset(Op386LEAL8)
v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULLconst [37] x)
}
x := v_0
v.reset(Op386LEAL4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [41] x)
}
x := v_0
v.reset(Op386LEAL8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [45] x)
x := v_0
v.reset(Op386LEAL8)
v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULLconst [73] x)
}
x := v_0
v.reset(Op386LEAL8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [81] x)
x := v_0
v.reset(Op386LEAL8)
v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
v0.AuxInt = log2(c + 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
v0.AuxInt = log2(c - 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
v0.AuxInt = log2(c - 2)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
v0.AuxInt = log2(c - 4)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type)
v0.AuxInt = log2(c - 8)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v.reset(Op386SHLLconst)
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(Op386SHLLconst)
v.AuxInt = log2(c / 5)
v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(Op386SHLLconst)
v.AuxInt = log2(c / 9)
v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(Op386MULLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386MULLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386MULLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, ptr, idx, mem)
return true
}
return false
v.reset(Op386MULLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (MULLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
v.reset(Op386MULLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (MULLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386MULLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
return false
v.reset(Op386MULSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386MULSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386MULSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386MULSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386MULSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386MULSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386ORLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386ORLloadidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(x, ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.reset(Op386ORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386ORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(Op386ORLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (ORLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
v.reset(Op386ORLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (ORLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386ORLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
return false
v.reset(Op386ORLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386ORLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ORLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386ORLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, ptr, idx, mem)
return true
}
return false
v.reset(Op386ORLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (ORLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
v.reset(Op386ORLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (ORLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386ORLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
return false
v.reset(Op386ORLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386ORLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(Op386ORLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ORLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
v.reset(Op386ORLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ORLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
v.reset(Op386ORLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (ORLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
v.reset(Op386ORLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
y := v_1.Args[0]
v.reset(Op386SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
f := v_2
v.reset(Op386SBBLconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(f)
+ v.AddArg2(x, f)
return true
}
return false
}
y := v_1.Args[0]
v.reset(Op386SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
y := v_1.Args[0]
v.reset(Op386SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(Op386SUBLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (SUBL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
v.reset(Op386SUBLloadidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(x, ptr, idx, mem)
return true
}
// match: (SUBL x x)
v.reset(Op386SUBLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386SUBLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386SUBLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, ptr, idx, mem)
return true
}
return false
v.reset(Op386SUBLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (SUBLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
v.reset(Op386SUBLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (SUBLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386SUBLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
return false
v.reset(Op386SUBLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SUBLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386SUBLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(Op386SUBLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (SUBLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
v.reset(Op386SUBLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (SUBLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
v.reset(Op386SUBLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (SUBLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = makeValAndOff(-c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386SUBSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(Op386SUBSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386SUBSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386SUBSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(Op386SUBSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386SUBSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(Op386XORLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(Op386XORLloadidx4)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(x, ptr, idx, mem)
return true
}
break
v.reset(Op386XORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (XORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
v.reset(Op386XORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(Op386XORLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (XORLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
v.reset(Op386XORLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
// match: (XORLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386XORLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(base, idx, mem)
return true
}
return false
v.reset(Op386XORLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (XORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
v.reset(Op386XORLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (XORLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
v.reset(Op386XORLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, ptr, idx, mem)
return true
}
return false
v.reset(Op386XORLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (XORLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
v.reset(Op386XORLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
// match: (XORLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
v.reset(Op386XORLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg4(val, base, idx, mem)
return true
}
return false
v.reset(Op386XORLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (XORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(Op386XORLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(Op386XORLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (XORLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
v.reset(Op386XORLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (XORLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
v.reset(Op386XORLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(base, idx, val, mem)
return true
}
// match: (XORLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
v.reset(Op386XORLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(Op386DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(Op386DIVWU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(Op386SETEQ)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETEQ)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETEQF)
v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETEQF)
v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETEQ)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETEQ)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETEQ)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGEF)
v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGEF)
v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGF)
v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGF)
v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
len := v_1
v.reset(Op386SETB)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
p := v_0
v.reset(Op386SETNE)
v0 := b.NewValue0(v.Pos, Op386TESTL, types.TypeFlags)
- v0.AddArg(p)
- v0.AddArg(p)
+ v0.AddArg2(p, p)
v.AddArg(v0)
return true
}
len := v_1
v.reset(Op386SETBE)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETLE)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETBE)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETLE)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGEF)
v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETBE)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGEF)
v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETLE)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETBE)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETL)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETB)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETL)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGF)
v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETB)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETGF)
v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETL)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETB)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
break
}
v.reset(Op386MOVLload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(Op386MOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(Op386MOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(Op386MOVSSload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(Op386MOVSDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x16 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x32 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x8 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x16 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x32 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x8 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x16 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x32 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x8 <t> x y)
}
v.reset(Op386SHLL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(Op386MODW)
v0 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(Op386MODWU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(Op386MOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(Op386MOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(Op386MOVLstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(Op386MOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, Op386MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [5] dst src mem)
mem := v_2
v.reset(Op386MOVBstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] dst src mem)
mem := v_2
v.reset(Op386MOVWstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [7] dst src mem)
mem := v_2
v.reset(Op386MOVLstore)
v.AuxInt = 3
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
v0.AuxInt = 3
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [8] dst src mem)
mem := v_2
v.reset(Op386MOVLstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, Op386ADDLconst, dst.Type)
v0.AuxInt = s % 4
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, Op386ADDLconst, src.Type)
v1.AuxInt = s % 4
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem)
- v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
- v3.AddArg(src)
- v3.AddArg(mem)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v3.AddArg2(src, mem)
+ v2.AddArg3(dst, v3, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(Op386DUFFCOPY)
v.AuxInt = 10 * (128 - s/4)
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Move [s] dst src mem)
break
}
v.reset(Op386REPMOVSL)
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32)
v0.AuxInt = s / 4
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
break
}
v.reset(Op386PXOR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386MOVSSconst, typ.Float32)
v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1)))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Neg32F x)
break
}
v.reset(Op386PXOR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386MOVSDconst, typ.Float64)
v0.AuxInt = auxFrom64F(math.Copysign(0, -1))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Neg64F x)
y := v_1
v.reset(Op386SETNE)
v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETNE)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETNEF)
v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETNEF)
v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETNE)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETNE)
v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(Op386SETNE)
v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
}
v.reset(Op386LoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(Op386LoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(Op386LoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
}
v.reset(Op386LoweredPanicExtendA)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
// match: (PanicExtend [kind] hi lo y mem)
}
v.reset(Op386LoweredPanicExtendB)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
// match: (PanicExtend [kind] hi lo y mem)
}
v.reset(Op386LoweredPanicExtendC)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux16 <t> x y)
}
v.reset(Op386SHRW)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux32 <t> x y)
}
v.reset(Op386SHRW)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux8 <t> x y)
}
v.reset(Op386SHRW)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x16 <t> x y)
break
}
v.reset(Op386SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x32 <t> x y)
break
}
v.reset(Op386SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x8 <t> x y)
break
}
v.reset(Op386SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux16 <t> x y)
}
v.reset(Op386SHRL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux32 <t> x y)
}
v.reset(Op386SHRL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux8 <t> x y)
}
v.reset(Op386SHRL)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x16 <t> x y)
break
}
v.reset(Op386SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x32 <t> x y)
break
}
v.reset(Op386SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x8 <t> x y)
break
}
v.reset(Op386SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux16 <t> x y)
}
v.reset(Op386SHRB)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux32 <t> x y)
}
v.reset(Op386SHRB)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386ANDL)
v0 := b.NewValue0(v.Pos, Op386SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux8 <t> x y)
}
v.reset(Op386SHRB)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x16 <t> x y)
break
}
v.reset(Op386SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x32 <t> x y)
break
}
v.reset(Op386SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(Op386SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, Op386ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type)
v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x8 <t> x y)
break
}
v.reset(Op386SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpSelect0)
v.Type = typ.UInt32
v0 := b.NewValue0(v.Pos, Op386MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(Op386SETO)
v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v1 := b.NewValue0(v.Pos, Op386MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
break
}
v.reset(Op386MOVSDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(Op386MOVSSstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(Op386MOVLstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(Op386MOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(Op386MOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_1
v.reset(Op386MOVBstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [2] destptr mem)
mem := v_1
v.reset(Op386MOVWstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [4] destptr mem)
mem := v_1
v.reset(Op386MOVLstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [3] destptr mem)
mem := v_1
v.reset(Op386MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 2)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVWstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [5] destptr mem)
mem := v_1
v.reset(Op386MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [6] destptr mem)
mem := v_1
v.reset(Op386MOVWstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [7] destptr mem)
mem := v_1
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 3)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] destptr mem)
v0 := b.NewValue0(v.Pos, Op386ADDLconst, typ.UInt32)
v0.AuxInt = s % 4
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(destptr, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [8] destptr mem)
mem := v_1
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [12] destptr mem)
mem := v_1
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 8)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v0.AuxInt = makeValAndOff(0, 4)
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(destptr, mem)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [16] destptr mem)
mem := v_1
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 12)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v0.AuxInt = makeValAndOff(0, 8)
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v1.AuxInt = makeValAndOff(0, 4)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem)
v2.AuxInt = 0
- v2.AddArg(destptr)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v2.AddArg2(destptr, mem)
+ v1.AddArg2(destptr, v2)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] destptr mem)
}
v.reset(Op386DUFFZERO)
v.AuxInt = 1 * (128 - s/4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [s] destptr mem)
break
}
v.reset(Op386REPSTOSL)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32)
v0.AuxInt = s / 4
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
- v.AddArg(mem)
+ v.AddArg4(destptr, v0, v1, mem)
return true
}
return false
cond := b.Controls[0]
b.Reset(Block386NE)
v0 := b.NewValue0(cond.Pos, Op386TESTB, types.TypeFlags)
- v0.AddArg(cond)
- v0.AddArg(cond)
+ v0.AddArg2(cond, cond)
b.AddControl(v0)
return true
}
v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpAMD64ADCQconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(carry)
+ v.AddArg2(x, carry)
return true
}
break
break
}
v.reset(OpAMD64ADDQcarry)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
y := v_1.Args[0]
v.reset(OpAMD64LEAL8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpAMD64LEAL4)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpAMD64LEAL2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64LEAL2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1_1
v.reset(OpAMD64LEAL2)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
y := v_1
v.reset(OpAMD64LEAL1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAL1)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpAMD64SUBL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64ADDLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
x := v_0.Args[0]
v.reset(OpAMD64LEAL1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (SHLLconst [1] x))
x := v_0.Args[0]
v.reset(OpAMD64LEAL1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (ADDLconst [c] (LEAL [d] {s} x))
v.reset(OpAMD64LEAL1)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
v.reset(OpAMD64LEAL2)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
v.reset(OpAMD64LEAL4)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
v.reset(OpAMD64LEAL8)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDLconst [c] x)
v.reset(OpAMD64ADDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ADDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64ADDLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ADDLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ADDL)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ADDLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64ADDLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
}
y := v_1.Args[0]
v.reset(OpAMD64LEAQ8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpAMD64LEAQ4)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpAMD64LEAQ2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64LEAQ2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1_1
v.reset(OpAMD64LEAQ2)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
y := v_1
v.reset(OpAMD64LEAQ1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAQ1)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpAMD64SUBQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64ADDQload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
x := v_0.Args[0]
v.reset(OpAMD64LEAQ1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDQconst [c] (SHLQconst [1] x))
x := v_0.Args[0]
v.reset(OpAMD64LEAQ1)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (ADDQconst [c] (LEAQ [d] {s} x))
v.reset(OpAMD64LEAQ1)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDQconst [c] (LEAQ2 [d] {s} x y))
v.reset(OpAMD64LEAQ2)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDQconst [c] (LEAQ4 [d] {s} x y))
v.reset(OpAMD64LEAQ4)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDQconst [c] (LEAQ8 [d] {s} x y))
v.reset(OpAMD64LEAQ8)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDQconst [0] x)
v.reset(OpAMD64ADDQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ADDQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64ADDQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ADDQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ADDQ)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ADDQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64ADDQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64ADDSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64ADDSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ADDSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ADDSD)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ADDSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64ADDSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ADDSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ADDSS)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
x := v_1
v.reset(OpAMD64BTRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64ANDLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64ANDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ANDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ANDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64ANDLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ANDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ANDLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ANDL)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ANDLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ANDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64ANDLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
}
x := v_1
v.reset(OpAMD64BTRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64ANDQload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64ANDQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ANDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ANDQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64ANDQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ANDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ANDQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ANDQ)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ANDQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ANDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64ANDQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64BTCLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (BTCLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64BTCLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64BTCLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (BTCLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64BTCLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64BTCQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (BTCQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64BTCQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64BTCQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (BTCQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64BTCQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
y := s.Args[1]
x := s.Args[0]
v.reset(OpAMD64BTQ)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (BTLconst [c] (SHRLconst [d] x))
y := s.Args[1]
x := s.Args[0]
v.reset(OpAMD64BTL)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
y := s.Args[1]
x := s.Args[0]
v.reset(OpAMD64BTQ)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
v.reset(OpAMD64BTRLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (BTRLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64BTRLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64BTRLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (BTRLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64BTRLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64BTRQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (BTRQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64BTRQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64BTRQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (BTRQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64BTRQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64BTSLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (BTSLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64BTSLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64BTSLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (BTSLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64BTSLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64BTSQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (BTSQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64BTSQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64BTSQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (BTSQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64BTSQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLLS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLCC _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLHI)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLCS y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLEQ)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLEQ _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLLE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLGE _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLLT)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLGT y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLCS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLHI y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLGE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLLE _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLCC)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLLS _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLGT)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLLT y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVLNE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVLNE y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQLS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQCC _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQHI)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQCS y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQEQ)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQEQ _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQLE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQGE _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQLT)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQGT y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQCS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQHI y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQGE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQLE _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQCC)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQLS _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQGT)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQLT y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVQNE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVQNE y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWLS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWCC _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWHI)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWCS y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWEQ)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWEQ _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWLE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWGE _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWLT)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWGT y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWCS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWHI y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWGE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWLE _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWCC)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWLS _ x (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWGT)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWLT y _ (FlagEQ))
}
cond := v_2.Args[0]
v.reset(OpAMD64CMOVWNE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cond)
+ v.AddArg3(x, y, cond)
return true
}
// match: (CMOVWNE y _ (FlagEQ))
}
v.reset(OpAMD64InvertFlags)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64CMPBload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpAMD64TESTB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPBconst (ANDLconst [c] x) [0])
}
x := v_0
v.reset(OpAMD64TESTB)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64CMPBconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64CMPBconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64CMPBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64CMPBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
v.reset(OpAMD64CMPBconstload)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpAMD64InvertFlags)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64CMPLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpAMD64TESTL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPLconst (ANDLconst [c] x) [0])
}
x := v_0
v.reset(OpAMD64TESTL)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64CMPLconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (CMPLconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64CMPLconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64CMPLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPLload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64CMPLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
v.reset(OpAMD64CMPLconstload)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpAMD64InvertFlags)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64CMPQload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPQ x l:(MOVQload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpAMD64TESTQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPQconst (ANDQconst [c] x) [0])
}
x := v_0
v.reset(OpAMD64TESTQ)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPQconst l:(MOVQload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64CMPQconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (CMPQconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64CMPQconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64CMPQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPQload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64CMPQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPQload {sym} [off] ptr (MOVQconst [c]) mem)
v.reset(OpAMD64CMPQconstload)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpAMD64InvertFlags)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64CMPWload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
v0 := b.NewValue0(l.Pos, OpAMD64CMPWload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(x)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, x, mem)
v.AddArg(v0)
return true
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpAMD64TESTW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWconst (ANDLconst [c] x) [0])
}
x := v_0
v.reset(OpAMD64TESTW)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64CMPWconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64CMPWconstload)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64CMPWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64CMPWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem)
v.reset(OpAMD64CMPWconstload)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64CMPXCHGLlock)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(old)
- v.AddArg(new_)
- v.AddArg(mem)
+ v.AddArg4(ptr, old, new_, mem)
return true
}
return false
v.reset(OpAMD64CMPXCHGQlock)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(old)
- v.AddArg(new_)
- v.AddArg(mem)
+ v.AddArg4(ptr, old, new_, mem)
return true
}
return false
v.reset(OpAMD64DIVSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpAMD64DIVSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64DIVSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
v.reset(OpAMD64DIVSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpAMD64DIVSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64DIVSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
return false
break
}
v.reset(OpAMD64HMULL)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
break
}
v.reset(OpAMD64HMULLU)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
break
}
v.reset(OpAMD64HMULQ)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
break
}
v.reset(OpAMD64HMULQU)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
v.reset(OpAMD64LEAL1)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAL1)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAL2)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAL4)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAL8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAL2)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
v.reset(OpAMD64LEAL2)
v.AuxInt = c + 2*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [c] {s} x (SHLLconst [1] y))
v.reset(OpAMD64LEAL4)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
v.reset(OpAMD64LEAL8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAL4)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
v.reset(OpAMD64LEAL4)
v.AuxInt = c + 4*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL4 [c] {s} x (SHLLconst [1] y))
v.reset(OpAMD64LEAL8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAL8)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
v.reset(OpAMD64LEAL8)
v.AuxInt = c + 8*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAQ1)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAQ1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y))
v.reset(OpAMD64LEAQ2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y))
v.reset(OpAMD64LEAQ4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y))
v.reset(OpAMD64LEAQ8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAQ1)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAQ2)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAQ4)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAQ8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64LEAQ1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
break
}
v.reset(OpAMD64ADDQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAQ2)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ2 [c] {s} x (ADDQconst [d] y))
v.reset(OpAMD64LEAQ2)
v.AuxInt = c + 2*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ2 [c] {s} x (SHLQconst [1] y))
v.reset(OpAMD64LEAQ4)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ2 [c] {s} x (SHLQconst [2] y))
v.reset(OpAMD64LEAQ8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
v.reset(OpAMD64LEAQ2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAQ4)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ4 [c] {s} x (ADDQconst [d] y))
v.reset(OpAMD64LEAQ4)
v.AuxInt = c + 4*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ4 [c] {s} x (SHLQconst [1] y))
v.reset(OpAMD64LEAQ8)
v.AuxInt = c
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
v.reset(OpAMD64LEAQ4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64LEAQ8)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ8 [c] {s} x (ADDQconst [d] y))
v.reset(OpAMD64LEAQ8)
v.AuxInt = c + 8*d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
v.reset(OpAMD64LEAQ8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQSX (ANDLconst [c] x))
v.reset(OpAMD64MOVBQSXload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBQZX x)
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBQZX (ANDLconst [c] x))
v.reset(OpAMD64MOVBatomicload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
v.reset(OpAMD64MOVBatomicload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVBloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBload [off] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVBloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem)
v.reset(OpAMD64MOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off] {sym} (SB) _)
v.reset(OpAMD64MOVBloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVBloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVBload)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
break
v.reset(OpAMD64SETLstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem)
v.reset(OpAMD64SETLEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETG x) mem)
v.reset(OpAMD64SETGstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem)
v.reset(OpAMD64SETGEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem)
v.reset(OpAMD64SETEQstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem)
v.reset(OpAMD64SETNEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETB x) mem)
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem)
v.reset(OpAMD64SETBEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETA x) mem)
v.reset(OpAMD64SETAstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem)
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem)
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVBstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem)
v.reset(OpAMD64MOVBstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type)
v0.AuxInt = 8
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem))))
v.reset(OpAMD64MOVLstore)
v.AuxInt = i - 3
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem))))))))
v.reset(OpAMD64MOVQstore)
v.AuxInt = i - 7
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem))
v.reset(OpAMD64MOVWstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16)
v0.AuxInt = j - 1
v0.Aux = s2
- v0.AddArg(p2)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(p2, mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVBstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVBstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
// match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem))
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
// match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVBstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVBstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreconstidx1)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(i)
- v.AddArg(mem)
+ v.AddArg3(p, i, mem)
return true
}
}
v.reset(OpAMD64MOVBstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVBstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, w.Type)
v0.AuxInt = 8
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, v0, mem)
return true
}
}
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 3
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, v0, mem)
return true
}
}
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = i - 7
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, v0, mem)
return true
}
}
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpAMD64MOVBstore)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
break
v.reset(OpAMD64MOVBstoreconstidx1)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVLQSX (ANDLconst [c] x))
v.reset(OpAMD64MOVLQSXload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVLQZX x)
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLQZX (ANDLconst [c] x))
v.reset(OpAMD64MOVLatomicload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
v.reset(OpAMD64MOVLatomicload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVLloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVLloadidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLload [off] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVLloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem)
v.reset(OpAMD64MOVLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _))
v.reset(OpAMD64MOVLloadidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLloadidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLload)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
break
v.reset(OpAMD64MOVLloadidx4)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVLloadidx4)
v.AuxInt = c + 4*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLloadidx4 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVLload)
v.AuxInt = i + 4*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVLloadidx8)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVLloadidx8)
v.AuxInt = c + 8*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLloadidx8 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVLload)
v.AuxInt = i + 8*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVLstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem)
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem)
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVLstoreidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVLstoreidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstore [off] {sym} (ADDQ ptr idx) val mem)
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem))
v.reset(OpAMD64MOVQstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem))
v.reset(OpAMD64MOVQstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64)
v0.AuxInt = j - 4
v0.Aux = s2
- v0.AddArg(p2)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(p2, mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64ADDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64ANDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64ORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64XORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64ADDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64SUBLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64ANDLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64ORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64XORLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64BTCLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64BTRLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore {sym} [off] ptr y:(BTSL l:(MOVLload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64BTSLmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64ADDLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64ANDLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64ORLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64XORLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(BTCLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64BTCLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(BTRLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64BTRLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr a:(BTSLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64BTSLconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem)
v.reset(OpAMD64MOVSSstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVLstoreconstidx4)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconst [x] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem))
v.reset(OpAMD64MOVQstore)
v.AuxInt = ValAndOff(a).Off()
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem))
v.reset(OpAMD64MOVQstore)
v.AuxInt = ValAndOff(a).Off()
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVLstoreconstidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = ValAndOff(a).Off()
v.Aux = s
- v.AddArg(p)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(p, i, v0, mem)
return true
}
}
v.reset(OpAMD64MOVLstoreconstidx4)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem)
v.reset(OpAMD64MOVLstoreconstidx4)
v.AuxInt = ValAndOff(x).add(4 * c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVLstoreconstidx4 [c] {s} p i x:(MOVLstoreconstidx4 [a] {s} p i mem))
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = ValAndOff(a).Off()
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type)
v0.AuxInt = 2
v0.AddArg(i)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
v1.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32
- v.AddArg(v1)
- v.AddArg(mem)
+ v.AddArg4(p, v0, v1, mem)
return true
}
return false
v.reset(OpAMD64MOVLstoreidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpAMD64MOVLstore)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpAMD64MOVLstoreidx4)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVLstoreidx4)
v.AuxInt = c + 4*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx4 [i-4] {s} p idx w mem))
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type)
v0.AuxInt = 2
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w, mem)
return true
}
// match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx4 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem))
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type)
v0.AuxInt = 2
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w0, mem)
return true
}
// match: (MOVLstoreidx4 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = i + 4*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVLstoreidx4 [off] {s} ptr idx (MOVQconst [c]) mem)
v.reset(OpAMD64MOVLstoreconstidx4)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpAMD64MOVLstoreidx8)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVLstoreidx8)
v.AuxInt = c + 8*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVLstoreidx8 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVLstore)
v.AuxInt = i + 8*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
return false
v.reset(OpAMD64MOVOload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVOload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64MOVOstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVOstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem)
v.reset(OpAMD64MOVQstore)
v.AuxInt = dstOff + 8
v.Aux = dstSym
- v.AddArg(ptr)
v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = int64(read64(srcSym, srcOff+8, config.ctxt.Arch.ByteOrder))
- v.AddArg(v0)
v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem)
v1.AuxInt = dstOff
v1.Aux = dstSym
- v1.AddArg(ptr)
v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64)
v2.AuxInt = int64(read64(srcSym, srcOff, config.ctxt.Arch.ByteOrder))
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
return false
v.reset(OpAMD64MOVQatomicload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
v.reset(OpAMD64MOVQatomicload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVQload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVQloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVQloadidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQload [off] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVQloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem)
v.reset(OpAMD64MOVQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _))
v.reset(OpAMD64MOVQloadidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQload)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
break
v.reset(OpAMD64MOVQloadidx8)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVQloadidx8)
v.AuxInt = c + 8*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQloadidx8 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVQload)
v.AuxInt = i + 8*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVQstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem)
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVQstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVQstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVQstoreidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVQstore [off] {sym} (ADDQ ptr idx) val mem)
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVQstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
v.reset(OpAMD64MOVQstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64ADDQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64ANDQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64ORQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem)
v.reset(OpAMD64XORQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64ADDQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64SUBQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64ANDQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64ORQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64XORQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
break
v.reset(OpAMD64BTCQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(BTRQ l:(MOVQload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64BTRQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore {sym} [off] ptr y:(BTSQ l:(MOVQload [off] {sym} ptr mem) x) mem)
v.reset(OpAMD64BTSQmodify)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64ADDQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64ANDQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64ORQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64XORQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(BTCQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64BTCQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64BTRQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr a:(BTSQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
v.reset(OpAMD64BTSQconstmodify)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem)
v.reset(OpAMD64MOVSDstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVQstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVQstoreconstidx8)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQstoreconst [x] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVQstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [c2] {s} p mem))
v.reset(OpAMD64MOVOstore)
v.AuxInt = ValAndOff(c2).Off()
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x.Pos, OpAMD64MOVOconst, types.TypeInt128)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVQstoreconstidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreconstidx8)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem)
v.reset(OpAMD64MOVQstoreconstidx8)
v.AuxInt = ValAndOff(x).add(8 * c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpAMD64MOVQstoreidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstore)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
break
v.reset(OpAMD64MOVQstoreconstidx1)
v.AuxInt = makeValAndOff(c, off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpAMD64MOVQstoreidx8)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVQstoreidx8)
v.AuxInt = c + 8*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVQstoreidx8 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVQstore)
v.AuxInt = i + 8*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVQstoreidx8 [off] {s} ptr idx (MOVQconst [c]) mem)
v.reset(OpAMD64MOVQstoreconstidx8)
v.AuxInt = makeValAndOff(c, off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpAMD64MOVSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVSDload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVSDloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVSDloadidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDload [off] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVSDloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVSDloadidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem)
v.reset(OpAMD64MOVSDloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVSDloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx1 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVSDload)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVSDloadidx8)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVSDloadidx8)
v.AuxInt = c + 8*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSDloadidx8 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVSDload)
v.AuxInt = i + 8*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVSDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVSDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVSDstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVSDstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVSDstoreidx8)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstore [off] {sym} (ADDQ ptr idx) val mem)
v.reset(OpAMD64MOVSDstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVQstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpAMD64MOVSDstoreidx8)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem)
v.reset(OpAMD64MOVSDstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVSDstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx1 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVSDstore)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
return false
v.reset(OpAMD64MOVSDstoreidx8)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVSDstoreidx8)
v.AuxInt = c + 8*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSDstoreidx8 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVSDstore)
v.AuxInt = i + 8*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
return false
v.reset(OpAMD64MOVSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVSSload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVSSloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVSSloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSload [off] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVSSloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVSSloadidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem)
v.reset(OpAMD64MOVSSloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVSSloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx1 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVSSload)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVSSloadidx4)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVSSloadidx4)
v.AuxInt = c + 4*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVSSloadidx4 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVSSload)
v.AuxInt = i + 4*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVSSstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVSSstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVSSstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVSSstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVSSstoreidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstore [off] {sym} (ADDQ ptr idx) val mem)
v.reset(OpAMD64MOVSSstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVLstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpAMD64MOVSSstoreidx4)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem)
v.reset(OpAMD64MOVSSstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVSSstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx1 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVSSstore)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
return false
v.reset(OpAMD64MOVSSstoreidx4)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVSSstoreidx4)
v.AuxInt = c + 4*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVSSstoreidx4 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVSSstore)
v.AuxInt = i + 4*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWQSX (ANDLconst [c] x))
v.reset(OpAMD64MOVWQSXload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVWQZX x)
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWQZX (ANDLconst [c] x))
v.reset(OpAMD64MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVWloadidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVWloadidx2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVWloadidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem)
v.reset(OpAMD64MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off] {sym} (SB) _)
v.reset(OpAMD64MOVWloadidx2)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWloadidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWload)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
break
v.reset(OpAMD64MOVWloadidx2)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem)
v.reset(OpAMD64MOVWloadidx2)
v.AuxInt = c + 2*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx2 [i] {s} p (MOVQconst [c]) mem)
v.reset(OpAMD64MOVWload)
v.AuxInt = i + 2*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpAMD64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem)
v.reset(OpAMD64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
v.reset(OpAMD64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem)
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem)
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem)
v.reset(OpAMD64MOVWstoreidx2)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off] {sym} (ADDQ ptr idx) val mem)
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem))
v.reset(OpAMD64MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem))
v.reset(OpAMD64MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem))
v.reset(OpAMD64MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem))
v.reset(OpAMD64MOVLstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32)
v0.AuxInt = j - 2
v0.Aux = s2
- v0.AddArg(p2)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(p2, mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
v.reset(OpAMD64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem)
v.reset(OpAMD64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVWstoreconstidx1)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem)
v.reset(OpAMD64MOVWstoreconstidx2)
v.AuxInt = ValAndOff(x).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconst [x] {sym} (ADDQ ptr idx) mem)
v.reset(OpAMD64MOVWstoreconstidx1)
v.AuxInt = x
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem))
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
// match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem))
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
// match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem)
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem)
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpAMD64MOVWstoreconstidx2)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreconstidx1)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(i)
- v.AddArg(mem)
+ v.AddArg3(p, i, mem)
return true
}
}
v.reset(OpAMD64MOVWstoreconstidx2)
v.AuxInt = ValAndOff(x).add(c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem)
v.reset(OpAMD64MOVWstoreconstidx2)
v.AuxInt = ValAndOff(x).add(2 * c)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem))
v.reset(OpAMD64MOVLstoreconstidx1)
v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type)
v0.AuxInt = 1
v0.AddArg(i)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
return false
v.reset(OpAMD64MOVWstoreidx2)
v.AuxInt = c
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreidx1)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpAMD64MOVWstore)
v.AuxInt = i + c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
break
v.reset(OpAMD64MOVWstoreconstidx1)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpAMD64MOVWstoreidx2)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem)
v.reset(OpAMD64MOVWstoreidx2)
v.AuxInt = c + 2*d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem))
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type)
v0.AuxInt = 1
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w, mem)
return true
}
// match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem))
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type)
v0.AuxInt = 1
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w, mem)
return true
}
// match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem))
v.reset(OpAMD64MOVLstoreidx1)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type)
v0.AuxInt = 1
v0.AddArg(idx)
- v.AddArg(v0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, v0, w0, mem)
return true
}
// match: (MOVWstoreidx2 [i] {s} p (MOVQconst [c]) w mem)
v.reset(OpAMD64MOVWstore)
v.AuxInt = i + 2*c
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVWstoreidx2 [off] {s} ptr idx (MOVLconst [c]) mem)
v.reset(OpAMD64MOVWstoreconstidx2)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
x := v_0
v.reset(OpAMD64NEGL)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpAMD64NEGL)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpAMD64NEGL)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
}
x := v_0
v.reset(OpAMD64LEAL2)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULLconst [ 5] x)
}
x := v_0
v.reset(OpAMD64LEAL4)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULLconst [ 7] x)
}
x := v_0
v.reset(OpAMD64LEAL2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [ 9] x)
}
x := v_0
v.reset(OpAMD64LEAL8)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULLconst [11] x)
}
x := v_0
v.reset(OpAMD64LEAL2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [13] x)
}
x := v_0
v.reset(OpAMD64LEAL4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [19] x)
}
x := v_0
v.reset(OpAMD64LEAL2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [21] x)
}
x := v_0
v.reset(OpAMD64LEAL4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [25] x)
}
x := v_0
v.reset(OpAMD64LEAL8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [27] x)
x := v_0
v.reset(OpAMD64LEAL8)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULLconst [37] x)
}
x := v_0
v.reset(OpAMD64LEAL4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [41] x)
}
x := v_0
v.reset(OpAMD64LEAL8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [45] x)
x := v_0
v.reset(OpAMD64LEAL8)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULLconst [73] x)
}
x := v_0
v.reset(OpAMD64LEAL8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLconst [81] x)
x := v_0
v.reset(OpAMD64LEAL8)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type)
v0.AuxInt = log2(c + 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type)
v0.AuxInt = log2(c - 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type)
v0.AuxInt = log2(c - 2)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type)
v0.AuxInt = log2(c - 4)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type)
v0.AuxInt = log2(c - 8)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLconst [c] x)
v.reset(OpAMD64SHLLconst)
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64SHLLconst)
v.AuxInt = log2(c / 5)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64SHLLconst)
v.AuxInt = log2(c / 9)
v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpAMD64NEGQ)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpAMD64NEGQ)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpAMD64NEGQ)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
}
x := v_0
v.reset(OpAMD64LEAQ2)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULQconst [ 5] x)
}
x := v_0
v.reset(OpAMD64LEAQ4)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULQconst [ 7] x)
}
x := v_0
v.reset(OpAMD64LEAQ2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [ 9] x)
}
x := v_0
v.reset(OpAMD64LEAQ8)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
// match: (MULQconst [11] x)
}
x := v_0
v.reset(OpAMD64LEAQ2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [13] x)
}
x := v_0
v.reset(OpAMD64LEAQ4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [19] x)
}
x := v_0
v.reset(OpAMD64LEAQ2)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [21] x)
}
x := v_0
v.reset(OpAMD64LEAQ4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [25] x)
}
x := v_0
v.reset(OpAMD64LEAQ8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [27] x)
x := v_0
v.reset(OpAMD64LEAQ8)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULQconst [37] x)
}
x := v_0
v.reset(OpAMD64LEAQ4)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [41] x)
}
x := v_0
v.reset(OpAMD64LEAQ8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [45] x)
x := v_0
v.reset(OpAMD64LEAQ8)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULQconst [73] x)
}
x := v_0
v.reset(OpAMD64LEAQ8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(x, v0)
return true
}
// match: (MULQconst [81] x)
x := v_0
v.reset(OpAMD64LEAQ8)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
v1 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v1.AddArg(x)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(x, x)
+ v.AddArg2(v0, v1)
return true
}
// match: (MULQconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type)
v0.AuxInt = log2(c + 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULQconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type)
v0.AuxInt = log2(c - 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULQconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type)
v0.AuxInt = log2(c - 2)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULQconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type)
v0.AuxInt = log2(c - 4)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULQconst [c] x)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type)
v0.AuxInt = log2(c - 8)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULQconst [c] x)
v.reset(OpAMD64SHLQconst)
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64SHLQconst)
v.AuxInt = log2(c / 5)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64SHLQconst)
v.AuxInt = log2(c / 9)
v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.reset(OpAMD64MULSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64MULSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MULSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64MULSD)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64MULSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64MULSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64MULSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64MULSS)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAMD64SUBL)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (NEGL (MOVLconst [c]))
break
}
v.reset(OpAMD64SUBQ)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (NEGQ (MOVQconst [c]))
}
x := v_1
v.reset(OpAMD64BTSL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64ROLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64ROLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64RORL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64RORL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64ROLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64ROLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64ROLB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64ROLB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64RORB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64RORB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(mem)
+ v2.AddArg2(p, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(idx)
- v2.AddArg(mem)
+ v2.AddArg3(p, idx, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(mem)
+ v3.AddArg2(p, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(idx)
- v3.AddArg(mem)
+ v3.AddArg3(p, idx, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.reset(OpAMD64ORLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64ORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64ORLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ORLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ORL)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ORLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64ORLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
}
x := v_1
v.reset(OpAMD64BTSQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpAMD64ROLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64ROLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64RORQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAMD64RORQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(mem)
+ v2.AddArg2(p, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(mem)
+ v2.AddArg2(p, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(idx)
- v2.AddArg(mem)
+ v2.AddArg3(p, idx, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(idx)
- v2.AddArg(mem)
+ v2.AddArg3(p, idx, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(mem)
+ v3.AddArg2(p, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(mem)
+ v3.AddArg2(p, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(idx)
- v3.AddArg(mem)
+ v3.AddArg3(p, idx, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(idx)
- v3.AddArg(mem)
+ v3.AddArg3(p, idx, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.reset(OpAMD64ORQload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64ORQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (ORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ORQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64ORQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (ORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64ORQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64ORQ)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64ORQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (ORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64ORQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
}
y := v_1.Args[0]
v.reset(OpAMD64RORB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLB x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64RORB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLB x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64RORL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLL x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64RORL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLL x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64RORQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLQ x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64RORQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLQ x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLW x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ROLW x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORB x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORB x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORL x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORL x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORQ x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORQ x (MOVQconst [c]))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORW x (NEGL y))
}
y := v_1.Args[0]
v.reset(OpAMD64ROLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RORW x (MOVQconst [c]))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARL x (NEGQ <t> (ADDQconst [c] y)))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SARL x (ANDQconst [c] y))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARL x (NEGQ <t> (ANDQconst [c] y)))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SARL x (ADDLconst [c] y))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARL x (NEGL <t> (ADDLconst [c] y)))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SARL x (ANDLconst [c] y))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARL x (NEGL <t> (ANDLconst [c] y)))
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARQ x (NEGQ <t> (ADDQconst [c] y)))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SARQ x (ANDQconst [c] y))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARQ x (NEGQ <t> (ANDQconst [c] y)))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SARQ x (ADDLconst [c] y))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARQ x (NEGL <t> (ADDLconst [c] y)))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SARQ x (ANDLconst [c] y))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SARQ x (NEGL <t> (ANDLconst [c] y)))
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
v.reset(OpAMD64SBBQconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(borrow)
+ v.AddArg2(x, borrow)
return true
}
// match: (SBBQ x y (FlagEQ))
break
}
v.reset(OpAMD64SUBQborrow)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpAMD64SETBEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETAEstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETAEstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETAEstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETAstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETAstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETAstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETBEstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETBEstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETBEstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETAstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETBstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
y := v_0_1
v.reset(OpAMD64SETAE)
v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_0_1
v.reset(OpAMD64SETAE)
v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(x, y)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(x, y)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = log2uint32(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem)
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETNEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(s)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem)
v.reset(OpAMD64SETNEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(s)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem)
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = 63
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = 31
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = 63
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETAEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = 31
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETEQstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETEQstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETEQstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETLEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETGEstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETGEstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETGEstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETLstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETGstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETGstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETGstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETGEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETLEstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETLEstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETLEstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
v.reset(OpAMD64SETGstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETLstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETLstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETLstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
y := v_0_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_0_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(x, y)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(x, y)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = log2uint32(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem)
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETEQstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(s)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem)
v.reset(OpAMD64SETEQstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(s)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem)
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = 63
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = 31
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = 63
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = 31
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
break
v.reset(OpAMD64SETNEstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem)
v.reset(OpAMD64SETNEstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SETNEstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (FlagEQ) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem)
v.reset(OpAMD64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLL x (NEGQ <t> (ADDQconst [c] y)))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHLL x (ANDQconst [c] y))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLL x (NEGQ <t> (ANDQconst [c] y)))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHLL x (ADDLconst [c] y))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLL x (NEGL <t> (ADDLconst [c] y)))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHLL x (ANDLconst [c] y))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLL x (NEGL <t> (ANDLconst [c] y)))
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLQ x (NEGQ <t> (ADDQconst [c] y)))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHLQ x (ANDQconst [c] y))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLQ x (NEGQ <t> (ANDQconst [c] y)))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHLQ x (ADDLconst [c] y))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLQ x (NEGL <t> (ADDLconst [c] y)))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHLQ x (ANDLconst [c] y))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHLQ x (NEGL <t> (ANDLconst [c] y)))
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRL x (NEGQ <t> (ADDQconst [c] y)))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHRL x (ANDQconst [c] y))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRL x (NEGQ <t> (ANDQconst [c] y)))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHRL x (ADDLconst [c] y))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRL x (NEGL <t> (ADDLconst [c] y)))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHRL x (ANDLconst [c] y))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRL x (NEGL <t> (ANDLconst [c] y)))
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRQ x (NEGQ <t> (ADDQconst [c] y)))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHRQ x (ANDQconst [c] y))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRQ x (NEGQ <t> (ANDQconst [c] y)))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHRQ x (ADDLconst [c] y))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRQ x (NEGL <t> (ADDLconst [c] y)))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SHRQ x (ANDLconst [c] y))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SHRQ x (NEGL <t> (ANDLconst [c] y)))
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64SUBLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpAMD64SUBLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64SUBLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64SUBL)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64SUBLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SUBLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64SUBQload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpAMD64SUBQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64SUBQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64SUBQ)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64SUBQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64SUBQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpAMD64SUBSDload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpAMD64SUBSDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64SUBSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64SUBSD)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64SUBSSload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpAMD64SUBSSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64SUBSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64SUBSS)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = makeValAndOff(0, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
break
break
}
v.reset(OpAMD64TESTB)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = makeValAndOff(0, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
break
break
}
v.reset(OpAMD64TESTL)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = makeValAndOff(0, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
break
break
}
v.reset(OpAMD64TESTQ)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = makeValAndOff(0, off)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
break
break
}
v.reset(OpAMD64TESTW)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
return false
v.reset(OpAMD64XADDLlock)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
return false
v.reset(OpAMD64XADDQlock)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
return false
v.reset(OpAMD64XCHGL)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
// match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem)
v.reset(OpAMD64XCHGL)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
return false
v.reset(OpAMD64XCHGQ)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
// match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem)
v.reset(OpAMD64XCHGQ)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
return false
}
x := v_1
v.reset(OpAMD64BTCL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64XORLload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64XORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (XORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64XORLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64XORLload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (XORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64XORLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64XORL)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64XORLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (XORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64XORLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
}
x := v_1
v.reset(OpAMD64BTCQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpAMD64XORQload)
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpAMD64XORQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (XORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64XORQconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpAMD64XORQload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (XORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
v.reset(OpAMD64XORQload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(val)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg3(val, base, mem)
return true
}
// match: (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
}
y := v_2.Args[1]
v.reset(OpAMD64XORQ)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpAMD64XORQmodify)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (XORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
v.reset(OpAMD64XORQmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
val := v_1
mem := v_2
v.reset(OpAMD64AddTupleFirst32)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpAMD64XADDLlock, types.NewTuple(typ.UInt32, types.TypeMem))
- v0.AddArg(val)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(val, ptr, mem)
+ v.AddArg2(val, v0)
return true
}
}
val := v_1
mem := v_2
v.reset(OpAMD64AddTupleFirst64)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpAMD64XADDQlock, types.NewTuple(typ.UInt64, types.TypeMem))
- v0.AddArg(val)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(val, ptr, mem)
+ v.AddArg2(val, v0)
return true
}
}
val := v_1
mem := v_2
v.reset(OpAMD64XCHGL)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
}
val := v_1
mem := v_2
v.reset(OpAMD64XCHGQ)
- v.AddArg(val)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(val, ptr, mem)
return true
}
}
mem := v_2
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem))
- v0.AddArg(val)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg3(val, ptr, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem))
- v0.AddArg(val)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg3(val, ptr, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem))
- v0.AddArg(val)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg3(val, ptr, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem))
- v0.AddArg(val)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg3(val, ptr, mem)
v.AddArg(v0)
return true
}
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32)
v2.AddArg(x)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v1.AuxInt = 1
v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
v3.AddArg(x)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
v.AddArg(v0)
return true
v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
v2.AddArg(x)
v1.AddArg(v2)
- v0.AddArg(v1)
v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
v3.AuxInt = -1
- v0.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v5 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
v5.AddArg(x)
v4.AddArg(v5)
- v0.AddArg(v4)
+ v0.AddArg3(v1, v3, v4)
v.AddArg(v0)
return true
}
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32)
v2.AddArg(x)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
break
}
v.reset(OpAMD64CMOVQEQ)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETNE cond))
break
}
v.reset(OpAMD64CMOVQNE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETL cond))
break
}
v.reset(OpAMD64CMOVQLT)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETG cond))
break
}
v.reset(OpAMD64CMOVQGT)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETLE cond))
break
}
v.reset(OpAMD64CMOVQLE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGE cond))
break
}
v.reset(OpAMD64CMOVQGE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETA cond))
break
}
v.reset(OpAMD64CMOVQHI)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETB cond))
break
}
v.reset(OpAMD64CMOVQCS)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETAE cond))
break
}
v.reset(OpAMD64CMOVQCC)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETBE cond))
break
}
v.reset(OpAMD64CMOVQLS)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETEQF cond))
break
}
v.reset(OpAMD64CMOVQEQF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETNEF cond))
break
}
v.reset(OpAMD64CMOVQNEF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGF cond))
break
}
v.reset(OpAMD64CMOVQGTF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGEF cond))
break
}
v.reset(OpAMD64CMOVQGEF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETEQ cond))
break
}
v.reset(OpAMD64CMOVLEQ)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETNE cond))
break
}
v.reset(OpAMD64CMOVLNE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETL cond))
break
}
v.reset(OpAMD64CMOVLLT)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETG cond))
break
}
v.reset(OpAMD64CMOVLGT)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETLE cond))
break
}
v.reset(OpAMD64CMOVLLE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGE cond))
break
}
v.reset(OpAMD64CMOVLGE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETA cond))
break
}
v.reset(OpAMD64CMOVLHI)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETB cond))
break
}
v.reset(OpAMD64CMOVLCS)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETAE cond))
break
}
v.reset(OpAMD64CMOVLCC)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETBE cond))
break
}
v.reset(OpAMD64CMOVLLS)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETEQF cond))
break
}
v.reset(OpAMD64CMOVLEQF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETNEF cond))
break
}
v.reset(OpAMD64CMOVLNEF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGF cond))
break
}
v.reset(OpAMD64CMOVLGTF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGEF cond))
break
}
v.reset(OpAMD64CMOVLGEF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETEQ cond))
break
}
v.reset(OpAMD64CMOVWEQ)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETNE cond))
break
}
v.reset(OpAMD64CMOVWNE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETL cond))
break
}
v.reset(OpAMD64CMOVWLT)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETG cond))
break
}
v.reset(OpAMD64CMOVWGT)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETLE cond))
break
}
v.reset(OpAMD64CMOVWLE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGE cond))
break
}
v.reset(OpAMD64CMOVWGE)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETA cond))
break
}
v.reset(OpAMD64CMOVWHI)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETB cond))
break
}
v.reset(OpAMD64CMOVWCS)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETAE cond))
break
}
v.reset(OpAMD64CMOVWCC)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETBE cond))
break
}
v.reset(OpAMD64CMOVWLS)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETEQF cond))
break
}
v.reset(OpAMD64CMOVWEQF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETNEF cond))
break
}
v.reset(OpAMD64CMOVWNEF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGF cond))
break
}
v.reset(OpAMD64CMOVWGTF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y (SETGEF cond))
break
}
v.reset(OpAMD64CMOVWGEF)
- v.AddArg(y)
- v.AddArg(x)
- v.AddArg(cond)
+ v.AddArg3(y, x, cond)
return true
}
// match: (CondSelect <t> x y check)
}
v.reset(OpCondSelect)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64)
v0.AddArg(check)
- v.AddArg(v0)
+ v.AddArg3(x, y, v0)
return true
}
// match: (CondSelect <t> x y check)
}
v.reset(OpCondSelect)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64)
v0.AddArg(check)
- v.AddArg(v0)
+ v.AddArg3(x, y, v0)
return true
}
// match: (CondSelect <t> x y check)
}
v.reset(OpCondSelect)
v.Type = t
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64)
v0.AddArg(check)
- v.AddArg(v0)
+ v.AddArg3(x, y, v0)
return true
}
// match: (CondSelect <t> x y check)
break
}
v.reset(OpAMD64CMOVQNE)
- v.AddArg(y)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(check)
- v.AddArg(v0)
+ v.AddArg3(y, x, v0)
return true
}
// match: (CondSelect <t> x y check)
break
}
v.reset(OpAMD64CMOVLNE)
- v.AddArg(y)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(check)
- v.AddArg(v0)
+ v.AddArg3(y, x, v0)
return true
}
// match: (CondSelect <t> x y check)
break
}
v.reset(OpAMD64CMOVWNE)
- v.AddArg(y)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(check)
- v.AddArg(v0)
+ v.AddArg3(y, x, v0)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
v1.AddArg(x)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t)
v2.AuxInt = 64
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
v4.AddArg(x)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
v0.AuxInt = a
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
v0.AuxInt = a
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
v0.AuxInt = a
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQ)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQ)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQ)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQ)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQ)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETEQ)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
z := v_2
v.reset(OpAMD64VFMADD231SD)
- v.AddArg(z)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(z, x, y)
return true
}
}
y := v_1
v.reset(OpAMD64SETGEF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGEF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
p := v_0
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags)
- v0.AddArg(p)
- v0.AddArg(p)
+ v0.AddArg2(p, p)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpAMD64SETBE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETLE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETBE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETLE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGEF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETBE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETLE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGEF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETBE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETLE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETBE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETL)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETL)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETL)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETGF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETL)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETB)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
break
}
v.reset(OpAMD64MOVQload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpAMD64MOVLload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpAMD64MOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpAMD64MOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpAMD64MOVSSload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpAMD64MOVSDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x16 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x32 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x64 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh16x8 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x16 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x32 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x64 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh32x8 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh64x16 x y)
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh64x32 x y)
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh64x64 x y)
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh64x8 x y)
break
}
v.reset(OpAMD64SHLQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x16 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x32 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x64 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Lsh8x8 x y)
break
}
v.reset(OpAMD64SHLL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
v0.AuxInt = a
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
v0.AuxInt = a
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
v0.AuxInt = a
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
src := v_1
mem := v_2
v.reset(OpAMD64MOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(OpAMD64MOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(OpAMD64MOVLstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] dst src mem)
src := v_1
mem := v_2
v.reset(OpAMD64MOVQstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [16] dst src mem)
break
}
v.reset(OpAMD64MOVOstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [16] dst src mem)
}
v.reset(OpAMD64MOVQstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [32] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
v2.AuxInt = 16
- v2.AddArg(dst)
- v2.AddArg(src)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg3(dst, src, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [48] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
v2.AuxInt = 16
- v2.AddArg(dst)
- v2.AddArg(src)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg3(dst, src, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [64] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = 32
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = 32
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
v2.AuxInt = 32
- v2.AddArg(dst)
- v2.AddArg(src)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg3(dst, src, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpAMD64MOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [5] dst src mem)
mem := v_2
v.reset(OpAMD64MOVBstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] dst src mem)
mem := v_2
v.reset(OpAMD64MOVWstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [7] dst src mem)
mem := v_2
v.reset(OpAMD64MOVLstore)
v.AuxInt = 3
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
v0.AuxInt = 3
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [9] dst src mem)
mem := v_2
v.reset(OpAMD64MOVBstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [10] dst src mem)
mem := v_2
v.reset(OpAMD64MOVWstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [12] dst src mem)
mem := v_2
v.reset(OpAMD64MOVLstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpAMD64MOVQstore)
v.AuxInt = s - 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
v0.AuxInt = s - 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = s % 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = s % 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v3.AddArg(src)
- v3.AddArg(mem)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v3.AddArg2(src, mem)
+ v2.AddArg3(dst, v3, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = s % 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = s % 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
- v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128)
- v3.AddArg(src)
- v3.AddArg(mem)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v3.AddArg2(src, mem)
+ v2.AddArg3(dst, v3, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = s % 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = s % 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
v2.AuxInt = 8
- v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
v3.AuxInt = 8
- v3.AddArg(src)
- v3.AddArg(mem)
- v2.AddArg(v3)
+ v3.AddArg2(src, mem)
v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem)
- v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
- v5.AddArg(src)
- v5.AddArg(mem)
- v4.AddArg(v5)
- v4.AddArg(mem)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v5.AddArg2(src, mem)
+ v4.AddArg3(dst, v5, mem)
+ v2.AddArg3(dst, v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpAMD64DUFFCOPY)
v.AuxInt = 14 * (64 - s/16)
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Move [s] dst src mem)
break
}
v.reset(OpAMD64REPMOVSQ)
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = s / 8
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
for {
x := v_0
v.reset(OpAMD64PXOR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32)
v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1)))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpAMD64PXOR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64)
v0.AuxInt = auxFrom64F(math.Copysign(0, -1))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNEF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNEF)
v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpAMD64SETNE)
v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpAMD64ADDQ)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = off
- v.AddArg(v0)
- v.AddArg(ptr)
+ v.AddArg2(v0, ptr)
return true
}
}
}
v.reset(OpAMD64LoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpAMD64LoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpAMD64LoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux16 x y)
break
}
v.reset(OpAMD64SHRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux32 x y)
break
}
v.reset(OpAMD64SHRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux64 x y)
break
}
v.reset(OpAMD64SHRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 16
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh16Ux8 x y)
break
}
v.reset(OpAMD64SHRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x16 x y)
break
}
v.reset(OpAMD64SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x32 x y)
break
}
v.reset(OpAMD64SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x64 x y)
break
}
v.reset(OpAMD64SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARW)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x8 x y)
break
}
v.reset(OpAMD64SARW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux16 x y)
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux32 x y)
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux64 x y)
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 32
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh32Ux8 x y)
break
}
v.reset(OpAMD64SHRL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x16 x y)
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x32 x y)
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x64 x y)
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARL)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x8 x y)
break
}
v.reset(OpAMD64SARL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh64Ux16 x y)
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh64Ux32 x y)
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh64Ux64 x y)
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDQ)
v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh64Ux8 x y)
break
}
v.reset(OpAMD64SHRQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARQ)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x16 x y)
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARQ)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x32 x y)
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARQ)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x64 x y)
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARQ)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x8 x y)
break
}
v.reset(OpAMD64SARQ)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux16 x y)
break
}
v.reset(OpAMD64SHRB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux32 x y)
break
}
v.reset(OpAMD64SHRB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux64 x y)
break
}
v.reset(OpAMD64SHRB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64ANDL)
v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t)
v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v2.AuxInt = 8
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Rsh8Ux8 x y)
break
}
v.reset(OpAMD64SHRB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x16 x y)
break
}
v.reset(OpAMD64SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x32 x y)
break
}
v.reset(OpAMD64SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x64 x y)
break
}
v.reset(OpAMD64SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpAMD64SARB)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type)
v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type)
v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x8 x y)
break
}
v.reset(OpAMD64SARB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v.Type = typ.UInt32
v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
v2.AddArg(c)
v1.AddArg(v2)
- v0.AddArg(v1)
+ v0.AddArg3(x, y, v1)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
v2.AddArg(c)
v1.AddArg(v2)
- v0.AddArg(v1)
+ v0.AddArg3(x, y, v1)
v.AddArg(v0)
return true
}
tuple := v_0.Args[1]
val := v_0.Args[0]
v.reset(OpAMD64ADDL)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpSelect0, t)
v0.AddArg(tuple)
- v.AddArg(v0)
+ v.AddArg2(val, v0)
return true
}
// match: (Select0 <t> (AddTupleFirst64 val tuple))
tuple := v_0.Args[1]
val := v_0.Args[0]
v.reset(OpAMD64ADDQ)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpSelect0, t)
v0.AddArg(tuple)
- v.AddArg(v0)
+ v.AddArg2(val, v0)
return true
}
return false
v.reset(OpAMD64SETO)
v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.reset(OpAMD64SETO)
v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
- v2.AddArg(x)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
v4.AddArg(c)
v3.AddArg(v4)
- v2.AddArg(v3)
+ v2.AddArg3(x, y, v3)
v1.AddArg(v2)
v0.AddArg(v1)
v.AddArg(v0)
v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
- v2.AddArg(x)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
v4.AddArg(c)
v3.AddArg(v4)
- v2.AddArg(v3)
+ v2.AddArg3(x, y, v3)
v1.AddArg(v2)
v0.AddArg(v1)
v.AddArg(v0)
break
}
v.reset(OpAMD64MOVSDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpAMD64MOVSSstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpAMD64MOVQstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpAMD64MOVLstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpAMD64MOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpAMD64MOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_1
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [2] destptr mem)
mem := v_1
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [4] destptr mem)
mem := v_1
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [8] destptr mem)
mem := v_1
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [3] destptr mem)
mem := v_1
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 2)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [5] destptr mem)
mem := v_1
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [6] destptr mem)
mem := v_1
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [7] destptr mem)
mem := v_1
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 3)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = s % 8
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(destptr, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [16] destptr mem)
}
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, 8)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [24] destptr mem)
}
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, 16)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v0.AuxInt = makeValAndOff(0, 8)
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(destptr, mem)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [32] destptr mem)
}
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, 24)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v0.AuxInt = makeValAndOff(0, 16)
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v1.AuxInt = makeValAndOff(0, 8)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v2.AuxInt = 0
- v2.AddArg(destptr)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v2.AddArg2(destptr, mem)
+ v1.AddArg2(destptr, v2)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] destptr mem)
}
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, s-8)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = s % 16
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [s] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = s % 16
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(destptr, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [16] destptr mem)
break
}
v.reset(OpAMD64MOVOstore)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [32] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = 16
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
- v2.AddArg(destptr)
v3 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v3.AuxInt = 0
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg3(destptr, v3, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Zero [48] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = 32
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v3.AuxInt = 16
v3.AddArg(destptr)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v4.AuxInt = 0
- v2.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
- v5.AddArg(destptr)
v6 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v2.AddArg(v5)
- v.AddArg(v2)
+ v5.AddArg3(destptr, v6, mem)
+ v2.AddArg3(v3, v4, v5)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Zero [64] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = 48
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v3.AuxInt = 32
v3.AddArg(destptr)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v4.AuxInt = 0
- v2.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
v6 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v6.AuxInt = 16
v6.AddArg(destptr)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v7.AuxInt = 0
- v5.AddArg(v7)
v8 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem)
- v8.AddArg(destptr)
v9 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v9.AuxInt = 0
- v8.AddArg(v9)
- v8.AddArg(mem)
- v5.AddArg(v8)
- v2.AddArg(v5)
- v.AddArg(v2)
+ v8.AddArg3(destptr, v9, mem)
+ v5.AddArg3(v6, v7, v8)
+ v2.AddArg3(v3, v4, v5)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Zero [s] destptr mem)
}
v.reset(OpAMD64DUFFZERO)
v.AuxInt = s
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [s] destptr mem)
break
}
v.reset(OpAMD64REPSTOSQ)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
v0.AuxInt = s / 8
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
- v.AddArg(mem)
+ v.AddArg4(destptr, v0, v1, mem)
return true
}
return false
y := v_0_1
b.Reset(BlockAMD64UGE)
v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
y := v_0_1
b.Reset(BlockAMD64UGE)
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
cond := b.Controls[0]
b.Reset(BlockAMD64NE)
v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags)
- v0.AddArg(cond)
- v0.AddArg(cond)
+ v0.AddArg2(cond, cond)
b.AddControl(v0)
return true
}
y := v_0_1
b.Reset(BlockAMD64ULT)
v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
y := v_0_1
b.Reset(BlockAMD64ULT)
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
v0.AuxInt = offOnly(vo)
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(ptr, mem)
+ v.AddArg2(v0, x)
return true
}
}
flags := v_2
v.reset(OpARMADCconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
break
flags := v_2
v.reset(OpARMADCshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
break
flags := v_2
v.reset(OpARMADCshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
break
flags := v_2
v.reset(OpARMADCshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
break
y := v_1.Args[0]
flags := v_2
v.reset(OpARMADCshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
break
y := v_1.Args[0]
flags := v_2
v.reset(OpARMADCshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
break
y := v_1.Args[0]
flags := v_2
v.reset(OpARMADCshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
break
flags := v_1
v.reset(OpARMADCconst)
v.AuxInt = int64(int32(c + d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
// match: (ADCconst [c] (SUBconst [d] x) flags)
flags := v_1
v.reset(OpARMADCconst)
v.AuxInt = int64(int32(c - d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (ADCshiftLL x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMADCconst)
v.AuxInt = int64(int32(uint32(c) << uint64(d)))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMADCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (ADCshiftLLreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMADCshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRAconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (ADCshiftRA x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMADCconst)
v.AuxInt = int64(int32(c) >> uint64(d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMADCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (ADCshiftRAreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMADCshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRLconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (ADCshiftRL x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMADCconst)
v.AuxInt = int64(int32(uint32(c) >> uint64(d)))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMADCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (ADCshiftRLreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMADCshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMADDshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMADDshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMADDshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMADDshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMADDshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMADDshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpARMSUB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpARMRSBconst)
v.AuxInt = c + d
v0 := b.NewValue0(v.Pos, OpARMADD, t)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
x := v_0.Args[0]
a := v_1
v.reset(OpARMMULA)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(a)
+ v.AddArg3(x, y, a)
return true
}
break
continue
}
v.reset(OpARMMULAD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
continue
}
v.reset(OpARMMULSD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
continue
}
v.reset(OpARMMULAF)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
continue
}
v.reset(OpARMMULSF)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMADDSshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMADDSshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMADDSshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMADDSshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMADDSshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMADDSshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.reset(OpARMADDSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMADDSshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMADDSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMADDSshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMADDSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMADDSshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMADDshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMADDshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMADDshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMANDshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMANDshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMANDshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMANDshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMANDshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMANDshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpARMBIC)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMBICshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMBICshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMBICshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpARMANDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMANDshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMANDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMANDshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMANDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMANDshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMBICshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (BIC x (SRLconst [c] y))
y := v_1.Args[0]
v.reset(OpARMBICshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (BIC x (SRAconst [c] y))
y := v_1.Args[0]
v.reset(OpARMBICshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (BIC x (SLL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMBICshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (BIC x (SRL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMBICshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (BIC x (SRA y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMBICshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (BIC x x)
c := v_2.AuxInt
v.reset(OpARMBICshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_2.AuxInt
v.reset(OpARMBICshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_2.AuxInt
v.reset(OpARMBICshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMCMNshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMCMNshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMCMNshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMCMNshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMCMNshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMCMNshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpARMCMP)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpARMCMNconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMCMNshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMCMNconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMCMNshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMCMNconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMCMNshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
flags := v_1.Args[0]
v.reset(OpARMCMOVWLSconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
flags := v_1.Args[0]
v.reset(OpARMCMOVWHSconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
}
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1.Args[0]
v.reset(OpARMCMPshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMP (SLLconst [c] y) x)
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1.Args[0]
v.reset(OpARMCMPshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMP (SRLconst [c] y) x)
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1.Args[0]
v.reset(OpARMCMPshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMP (SRAconst [c] y) x)
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMCMPshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (CMP (SLL y z) x)
x := v_1
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
v.AddArg(v0)
return true
}
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMCMPshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (CMP (SRL y z) x)
x := v_1
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
v.AddArg(v0)
return true
}
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMCMPshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (CMP (SRA y z) x)
x := v_1
v.reset(OpARMInvertFlags)
v0 := b.NewValue0(v.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
v.AddArg(v0)
return true
}
}
y := v_1.Args[0]
v.reset(OpARMCMN)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v0.AuxInt = c
v1 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
c := v_2.AuxInt
v.reset(OpARMCMPshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v0.AuxInt = c
v1 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
c := v_2.AuxInt
v.reset(OpARMCMPshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v0.AuxInt = c
v1 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
c := v_2.AuxInt
v.reset(OpARMCMPshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMMOVBUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVBUload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVBUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
break
}
v.reset(OpARMMOVBUloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBUload [off] {sym} (SB) _)
mem := v_2
v.reset(OpARMMOVBUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUloadidx (MOVWconst [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVBUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARMMOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVBload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
break
}
v.reset(OpARMMOVBloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_2
v.reset(OpARMMOVBload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBloadidx (MOVWconst [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVBload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARMMOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off1] {sym} (SUBconst [off2] ptr) val mem)
v.reset(OpARMMOVBstore)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpARMMOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
v.reset(OpARMMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem)
v.reset(OpARMMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpARMMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpARMMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [0] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARMMOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARMMOVBstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstoreidx (MOVWconst [c]) ptr val mem)
mem := v_3
v.reset(OpARMMOVBstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpARMMOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVDload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _))
v.reset(OpARMMOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off1] {sym} (SUBconst [off2] ptr) val mem)
v.reset(OpARMMOVDstore)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpARMMOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpARMMOVFload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVFload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVFload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVFload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _))
v.reset(OpARMMOVFstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVFstore [off1] {sym} (SUBconst [off2] ptr) val mem)
v.reset(OpARMMOVFstore)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpARMMOVFstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpARMMOVHUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVHUload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVHUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _))
break
}
v.reset(OpARMMOVHUloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHUload [off] {sym} (SB) _)
mem := v_2
v.reset(OpARMMOVHUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUloadidx (MOVWconst [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVHUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARMMOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVHload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _))
break
}
v.reset(OpARMMOVHloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_2
v.reset(OpARMMOVHload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHloadidx (MOVWconst [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVHload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARMMOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off1] {sym} (SUBconst [off2] ptr) val mem)
v.reset(OpARMMOVHstore)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpARMMOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpARMMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpARMMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [0] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARMMOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARMMOVHstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstoreidx (MOVWconst [c]) ptr val mem)
mem := v_3
v.reset(OpARMMOVHstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpARMMOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym} (SUBconst [off2] ptr) mem)
v.reset(OpARMMOVWload)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpARMMOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
break
}
v.reset(OpARMMOVWloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [0] {sym} (ADDshiftLL ptr idx [c]) mem)
}
v.reset(OpARMMOVWloadshiftLL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [0] {sym} (ADDshiftRL ptr idx [c]) mem)
}
v.reset(OpARMMOVWloadshiftRL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [0] {sym} (ADDshiftRA ptr idx [c]) mem)
}
v.reset(OpARMMOVWloadshiftRA)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off] {sym} (SB) _)
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWloadidx (MOVWconst [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWloadidx ptr (SLLconst idx [c]) mem)
mem := v_2
v.reset(OpARMMOVWloadshiftLL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx (SLLconst idx [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVWloadshiftLL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx ptr (SRLconst idx [c]) mem)
mem := v_2
v.reset(OpARMMOVWloadshiftRL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx (SRLconst idx [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVWloadshiftRL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx ptr (SRAconst idx [c]) mem)
mem := v_2
v.reset(OpARMMOVWloadshiftRA)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx (SRAconst idx [c]) ptr mem)
mem := v_2
v.reset(OpARMMOVWloadshiftRA)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = int64(uint32(c) << uint64(d))
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = int64(int32(c) >> uint64(d))
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = int64(uint32(c) >> uint64(d))
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARMMOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off1] {sym} (SUBconst [off2] ptr) val mem)
v.reset(OpARMMOVWstore)
v.AuxInt = off1 - off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpARMMOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [0] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARMMOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [0] {sym} (ADDshiftLL ptr idx [c]) val mem)
}
v.reset(OpARMMOVWstoreshiftLL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [0] {sym} (ADDshiftRL ptr idx [c]) val mem)
}
v.reset(OpARMMOVWstoreshiftRL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [0] {sym} (ADDshiftRA ptr idx [c]) val mem)
}
v.reset(OpARMMOVWstoreshiftRA)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstoreidx (MOVWconst [c]) ptr val mem)
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstoreidx ptr (SLLconst idx [c]) val mem)
mem := v_3
v.reset(OpARMMOVWstoreshiftLL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx (SLLconst idx [c]) ptr val mem)
mem := v_3
v.reset(OpARMMOVWstoreshiftLL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx ptr (SRLconst idx [c]) val mem)
mem := v_3
v.reset(OpARMMOVWstoreshiftRL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx (SRLconst idx [c]) ptr val mem)
mem := v_3
v.reset(OpARMMOVWstoreshiftRL)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx ptr (SRAconst idx [c]) val mem)
mem := v_3
v.reset(OpARMMOVWstoreshiftRA)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx (SRAconst idx [c]) ptr val mem)
mem := v_3
v.reset(OpARMMOVWstoreshiftRA)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = int64(uint32(c) << uint64(d))
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = int64(int32(c) >> uint64(d))
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = int64(uint32(c) >> uint64(d))
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
}
v.reset(OpARMADDshiftLL)
v.AuxInt = log2(c - 1)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
break
}
v.reset(OpARMRSBshiftLL)
v.AuxInt = log2(c + 1)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
break
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = 1
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 5)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 7)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 9)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
break
}
v.reset(OpARMSUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MULA _ (MOVWconst [0]) a)
}
a := v_2
v.reset(OpARMADD)
- v.AddArg(x)
- v.AddArg(a)
+ v.AddArg2(x, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 3)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 5)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 2
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 7)
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 9)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
break
}
v.reset(OpARMSUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MULA (MOVWconst [0]) _ a)
x := v_1
a := v_2
v.reset(OpARMADD)
- v.AddArg(x)
- v.AddArg(a)
+ v.AddArg2(x, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v.reset(OpARMADD)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 3)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 5)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 2
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 7)
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 9)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULA (MOVWconst [c]) (MOVWconst [d]) a)
continue
}
v.reset(OpARMNMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpARMNMULF)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
break
}
v.reset(OpARMADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MULS _ (MOVWconst [0]) a)
}
a := v_2
v.reset(OpARMRSB)
- v.AddArg(x)
- v.AddArg(a)
+ v.AddArg2(x, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 3)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 5)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 2
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 7)
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS x (MOVWconst [c]) a)
v0.AuxInt = log2(c / 9)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
break
}
v.reset(OpARMADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MULS (MOVWconst [0]) _ a)
x := v_1
a := v_2
v.reset(OpARMRSB)
- v.AddArg(x)
- v.AddArg(a)
+ v.AddArg2(x, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = log2(c)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v.reset(OpARMRSB)
v0 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(a)
+ v0.AddArg2(x, x)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 3)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 1
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 5)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 2
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 7)
v1 := b.NewValue0(v.Pos, OpARMRSBshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) x a)
v0.AuxInt = log2(c / 9)
v1 := b.NewValue0(v.Pos, OpARMADDshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(a)
+ v.AddArg2(v0, a)
return true
}
// match: (MULS (MOVWconst [c]) (MOVWconst [d]) a)
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARMMVNshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (MVN (SRL x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARMMVNshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (MVN (SRA x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARMMVNshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
break
}
v.reset(OpARMNMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
break
}
v.reset(OpARMNMULF)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
x := v_0.Args[0]
y := v_1
v.reset(OpARMMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
x := v_0.Args[0]
y := v_1
v.reset(OpARMMULF)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMORshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMORshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMORshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMORshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMORshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMORshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.reset(OpARMORconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMORshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMORconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMORshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMORconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMORshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMRSBshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RSB (SLLconst [c] y) x)
x := v_1
v.reset(OpARMSUBshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RSB x (SRLconst [c] y))
y := v_1.Args[0]
v.reset(OpARMRSBshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RSB (SRLconst [c] y) x)
x := v_1
v.reset(OpARMSUBshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RSB x (SRAconst [c] y))
y := v_1.Args[0]
v.reset(OpARMRSBshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RSB (SRAconst [c] y) x)
x := v_1
v.reset(OpARMSUBshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (RSB x (SLL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMRSBshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (RSB (SLL y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMSUBshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (RSB x (SRL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMRSBshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (RSB (SRL y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMSUBshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (RSB x (SRA y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMRSBshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (RSB (SRA y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMSUBshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (RSB x x)
break
}
v.reset(OpARMMULS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(a)
+ v.AddArg3(x, y, a)
return true
}
return false
v.reset(OpARMSUBSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMRSBSshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMSUBSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMRSBSshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMSUBSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMRSBSshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMSUBconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMRSBshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMSUBconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMRSBshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMSUBconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMRSBshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
flags := v_1
v.reset(OpARMRSCconst)
v.AuxInt = int64(int32(c - d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
// match: (RSCconst [c] (SUBconst [d] x) flags)
flags := v_1
v.reset(OpARMRSCconst)
v.AuxInt = int64(int32(c + d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (RSCshiftLL x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMRSCconst)
v.AuxInt = int64(int32(uint32(c) << uint64(d)))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMSBCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (RSCshiftLLreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMRSCshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRAconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (RSCshiftRA x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMRSCconst)
v.AuxInt = int64(int32(c) >> uint64(d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMSBCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (RSCshiftRAreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMRSCshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRLconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (RSCshiftRL x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMRSCconst)
v.AuxInt = int64(int32(uint32(c) >> uint64(d)))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMSBCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (RSCshiftRLreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMRSCshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
flags := v_2
v.reset(OpARMRSCconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
// match: (SBC x (MOVWconst [c]) flags)
flags := v_2
v.reset(OpARMSBCconst)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
// match: (SBC x (SLLconst [c] y) flags)
flags := v_2
v.reset(OpARMSBCshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
// match: (SBC (SLLconst [c] y) x flags)
flags := v_2
v.reset(OpARMRSCshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
// match: (SBC x (SRLconst [c] y) flags)
flags := v_2
v.reset(OpARMSBCshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
// match: (SBC (SRLconst [c] y) x flags)
flags := v_2
v.reset(OpARMRSCshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
// match: (SBC x (SRAconst [c] y) flags)
flags := v_2
v.reset(OpARMSBCshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
// match: (SBC (SRAconst [c] y) x flags)
flags := v_2
v.reset(OpARMRSCshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
// match: (SBC x (SLL y z) flags)
y := v_1.Args[0]
flags := v_2
v.reset(OpARMSBCshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
// match: (SBC (SLL y z) x flags)
x := v_1
flags := v_2
v.reset(OpARMRSCshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
// match: (SBC x (SRL y z) flags)
y := v_1.Args[0]
flags := v_2
v.reset(OpARMSBCshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
// match: (SBC (SRL y z) x flags)
x := v_1
flags := v_2
v.reset(OpARMRSCshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
// match: (SBC x (SRA y z) flags)
y := v_1.Args[0]
flags := v_2
v.reset(OpARMSBCshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
// match: (SBC (SRA y z) x flags)
x := v_1
flags := v_2
v.reset(OpARMRSCshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
- v.AddArg(flags)
+ v.AddArg4(x, y, z, flags)
return true
}
return false
flags := v_1
v.reset(OpARMSBCconst)
v.AuxInt = int64(int32(c - d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
// match: (SBCconst [c] (SUBconst [d] x) flags)
flags := v_1
v.reset(OpARMSBCconst)
v.AuxInt = int64(int32(c + d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSLLconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (SBCshiftLL x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMSBCconst)
v.AuxInt = int64(int32(uint32(c) << uint64(d)))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMRSCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (SBCshiftLLreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMSBCshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRAconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (SBCshiftRA x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMSBCconst)
v.AuxInt = int64(int32(c) >> uint64(d))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMRSCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (SBCshiftRAreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMSBCshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRLconst, x.Type)
v0.AuxInt = d
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(flags)
+ v.AddArg2(v0, flags)
return true
}
// match: (SBCshiftRL x (MOVWconst [c]) [d] flags)
flags := v_2
v.reset(OpARMSBCconst)
v.AuxInt = int64(int32(uint32(c) >> uint64(d)))
- v.AddArg(x)
- v.AddArg(flags)
+ v.AddArg2(x, flags)
return true
}
return false
v.reset(OpARMRSCconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(flags)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, flags)
return true
}
// match: (SBCshiftRLreg x y (MOVWconst [c]) flags)
flags := v_3
v.reset(OpARMSBCshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flags)
+ v.AddArg3(x, y, flags)
return true
}
return false
break
}
v.reset(OpARMSRA)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAcond x _ (FlagLT_UGT))
break
}
v.reset(OpARMSRA)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAcond x _ (FlagGT_UGT))
y := v_1.Args[0]
v.reset(OpARMSUBshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUB (SLLconst [c] y) x)
x := v_1
v.reset(OpARMRSBshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUB x (SRLconst [c] y))
y := v_1.Args[0]
v.reset(OpARMSUBshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUB (SRLconst [c] y) x)
x := v_1
v.reset(OpARMRSBshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUB x (SRAconst [c] y))
y := v_1.Args[0]
v.reset(OpARMSUBshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUB (SRAconst [c] y) x)
x := v_1
v.reset(OpARMRSBshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUB x (SLL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMSUBshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUB (SLL y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMRSBshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUB x (SRL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMSUBshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUB (SRL y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMRSBshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUB x (SRA y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMSUBshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUB (SRA y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMRSBshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUB x x)
break
}
v.reset(OpARMMULS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(a)
+ v.AddArg3(x, y, a)
return true
}
return false
break
}
v.reset(OpARMMULSD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (SUBD a (NMULD x y))
break
}
v.reset(OpARMMULAD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
return false
break
}
v.reset(OpARMMULSF)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (SUBF a (NMULF x y))
x := v_1.Args[0]
if !(a.Uses == 1 && objabi.GOARM >= 6) {
break
- }
- v.reset(OpARMMULAF)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ }
+ v.reset(OpARMMULAF)
+ v.AddArg3(a, x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMSUBSshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBS (SLLconst [c] y) x)
x := v_1
v.reset(OpARMRSBSshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBS x (SRLconst [c] y))
y := v_1.Args[0]
v.reset(OpARMSUBSshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBS (SRLconst [c] y) x)
x := v_1
v.reset(OpARMRSBSshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBS x (SRAconst [c] y))
y := v_1.Args[0]
v.reset(OpARMSUBSshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBS (SRAconst [c] y) x)
x := v_1
v.reset(OpARMRSBSshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBS x (SLL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMSUBSshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUBS (SLL y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMRSBSshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUBS x (SRL y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMSUBSshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUBS (SRL y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMRSBSshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUBS x (SRA y z))
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMSUBSshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
// match: (SUBS (SRA y z) x)
y := v_0.Args[0]
x := v_1
v.reset(OpARMRSBSshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
return false
v.reset(OpARMRSBSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMSUBSshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMRSBSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMSUBSshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMRSBSconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMSUBSshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMRSBconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMSUBshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMRSBconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMSUBshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMRSBconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMSUBshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMTEQshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMTEQshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMTEQshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMTEQshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMTEQshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMTEQshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.reset(OpARMTEQconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMTEQshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMTEQconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMTEQshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMTEQconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMTEQshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMTSTshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMTSTshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMTSTshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMTSTshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMTSTshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMTSTshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.reset(OpARMTSTconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMTSTshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMTSTconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMTSTshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMTSTconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMTSTshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_1.Args[0]
v.reset(OpARMXORshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMXORshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMXORshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[0]
v.reset(OpARMXORshiftRR)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMXORshiftLLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMXORshiftRLreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
z := v_1.Args[1]
y := v_1.Args[0]
v.reset(OpARMXORshiftRAreg)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.reset(OpARMXORconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMXORshiftLL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMXORconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRA, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMXORshiftRA)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARMXORconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
c := v_2.AuxInt
v.reset(OpARMXORshiftRL)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRLconst, t)
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpARMSUB, t)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v1 := b.NewValue0(v.Pos, OpARMBICconst, t)
v1.AuxInt = 0xff0000
v2 := b.NewValue0(v.Pos, OpARMXOR, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpARMSRRconst, t)
v3.AuxInt = 16
v3.AddArg(x)
- v2.AddArg(v3)
+ v2.AddArg2(x, v3)
v1.AddArg(v2)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpARMSRRconst, t)
v4.AuxInt = 8
v4.AddArg(x)
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
// match: (Bswap32 x)
v3 := b.NewValue0(v.Pos, OpARMORconst, typ.UInt32)
v3.AuxInt = 0x10000
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARMRSBconst, typ.UInt32)
v4.AuxInt = 0
v5 := b.NewValue0(v.Pos, OpARMORconst, typ.UInt32)
v5.AuxInt = 0x10000
v5.AddArg(x)
v4.AddArg(v5)
- v2.AddArg(v4)
+ v2.AddArg2(v3, v4)
v1.AddArg(v2)
v0.AddArg(v1)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMSUBconst, t)
v1.AuxInt = 1
v2 := b.NewValue0(v.Pos, OpARMAND, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpARMRSBconst, t)
v3.AuxInt = 0
v3.AddArg(x)
- v2.AddArg(v3)
+ v2.AddArg2(x, v3)
v1.AddArg(v2)
v0.AddArg(v1)
v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpARMORconst, typ.UInt32)
v3.AuxInt = 0x100
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARMRSBconst, typ.UInt32)
v4.AuxInt = 0
v5 := b.NewValue0(v.Pos, OpARMORconst, typ.UInt32)
v5.AuxInt = 0x100
v5.AddArg(x)
v4.AddArg(v5)
- v2.AddArg(v4)
+ v2.AddArg2(v3, v4)
v1.AddArg(v2)
v0.AddArg(v1)
v.AddArg(v0)
v.reset(OpDiv32)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpDiv32u)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v2 := b.NewValue0(v.Pos, OpARMCALLudiv, types.NewTuple(typ.UInt32, typ.UInt32))
v3 := b.NewValue0(v.Pos, OpARMSUB, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpARMXOR, typ.UInt32)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v5.AddArg(x)
- v4.AddArg(v5)
- v3.AddArg(v4)
+ v4.AddArg2(x, v5)
v6 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v6.AddArg(x)
- v3.AddArg(v6)
- v2.AddArg(v3)
+ v3.AddArg2(v4, v6)
v7 := b.NewValue0(v.Pos, OpARMSUB, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpARMXOR, typ.UInt32)
- v8.AddArg(y)
v9 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v9.AddArg(y)
- v8.AddArg(v9)
- v7.AddArg(v8)
+ v8.AddArg2(y, v9)
v10 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v10.AddArg(y)
- v7.AddArg(v10)
- v2.AddArg(v7)
+ v7.AddArg2(v8, v10)
+ v2.AddArg2(v3, v7)
v1.AddArg(v2)
- v0.AddArg(v1)
v11 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v12 := b.NewValue0(v.Pos, OpARMXOR, typ.UInt32)
- v12.AddArg(x)
- v12.AddArg(y)
+ v12.AddArg2(x, y)
v11.AddArg(v12)
- v0.AddArg(v11)
- v.AddArg(v0)
+ v0.AddArg2(v1, v11)
v13 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v14 := b.NewValue0(v.Pos, OpARMXOR, typ.UInt32)
- v14.AddArg(x)
- v14.AddArg(y)
+ v14.AddArg2(x, y)
v13.AddArg(v14)
- v.AddArg(v13)
+ v.AddArg2(v0, v13)
return true
}
}
v.reset(OpSelect0)
v.Type = typ.UInt32
v0 := b.NewValue0(v.Pos, OpARMCALLudiv, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpDiv32)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpDiv32u)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMEqual)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpARMXORconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpARMXOR, typ.Bool)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMEqual)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
z := v_2
v.reset(OpARMFMULAD)
- v.AddArg(z)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(z, x, y)
return true
}
}
y := v_1
v.reset(OpARMGreaterEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterThan)
v0 := b.NewValue0(v.Pos, OpARMCMPF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterThan)
v0 := b.NewValue0(v.Pos, OpARMCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpARMLessThanU)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpARMLessEqualU)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMLessEqual)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPF, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMLessEqualU)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMLessThan)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterThan)
v0 := b.NewValue0(v.Pos, OpARMCMPF, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMLessThanU)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMGreaterThan)
v0 := b.NewValue0(v.Pos, OpARMCMPD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
break
}
v.reset(OpARMMOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVHUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVFload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARMMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSLL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSLL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpMod32)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMod32u)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v2 := b.NewValue0(v.Pos, OpARMCALLudiv, types.NewTuple(typ.UInt32, typ.UInt32))
v3 := b.NewValue0(v.Pos, OpARMSUB, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpARMXOR, typ.UInt32)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v5.AddArg(x)
- v4.AddArg(v5)
- v3.AddArg(v4)
+ v4.AddArg2(x, v5)
v6 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v6.AddArg(x)
- v3.AddArg(v6)
- v2.AddArg(v3)
+ v3.AddArg2(v4, v6)
v7 := b.NewValue0(v.Pos, OpARMSUB, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpARMXOR, typ.UInt32)
- v8.AddArg(y)
v9 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v9.AddArg(y)
- v8.AddArg(v9)
- v7.AddArg(v8)
+ v8.AddArg2(y, v9)
v10 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v10.AddArg(y)
- v7.AddArg(v10)
- v2.AddArg(v7)
+ v7.AddArg2(v8, v10)
+ v2.AddArg2(v3, v7)
v1.AddArg(v2)
- v0.AddArg(v1)
v11 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v11.AddArg(x)
- v0.AddArg(v11)
- v.AddArg(v0)
+ v0.AddArg2(v1, v11)
v12 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v12.AddArg(x)
- v.AddArg(v12)
+ v.AddArg2(v0, v12)
return true
}
}
v.reset(OpSelect1)
v.Type = typ.UInt32
v0 := b.NewValue0(v.Pos, OpARMCALLudiv, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpMod32)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMod32u)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(OpARMMOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] {t} dst src mem)
break
}
v.reset(OpARMMOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVHUload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
mem := v_2
v.reset(OpARMMOVBstore)
v.AuxInt = 1
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
v0.AuxInt = 1
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [4] {t} dst src mem)
break
}
v.reset(OpARMMOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVWload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] {t} dst src mem)
}
v.reset(OpARMMOVHstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVHUload, typ.UInt16)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARMMOVHstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARMMOVHUload, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [4] dst src mem)
mem := v_2
v.reset(OpARMMOVBstore)
v.AuxInt = 3
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
v0.AuxInt = 3
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
v2.AuxInt = 2
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v3.AuxInt = 1
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
v4.AuxInt = 1
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
+ v4.AddArg2(src, mem)
v5 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
- v5.AddArg(dst)
v6 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
- v6.AddArg(src)
- v6.AddArg(mem)
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v6.AddArg2(src, mem)
+ v5.AddArg3(dst, v6, mem)
+ v3.AddArg3(dst, v4, v5)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpARMMOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v1.AuxInt = 1
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
v2.AuxInt = 1
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpARMMOVBUload, typ.UInt8)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] {t} dst src mem)
}
v.reset(OpARMDUFFCOPY)
v.AuxInt = 8 * (128 - s/4)
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Move [s] {t} dst src mem)
}
v.reset(OpARMLoweredMove)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpARMADDconst, src.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(src)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMNotEqual)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMNotEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMNotEqual)
v0 := b.NewValue0(v.Pos, OpARMCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARMNotEqual)
v0 := b.NewValue0(v.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
}
v.reset(OpARMLoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpARMLoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpARMLoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
}
v.reset(OpARMLoweredPanicExtendA)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
// match: (PanicExtend [kind] hi lo y mem)
}
v.reset(OpARMLoweredPanicExtendB)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
// match: (PanicExtend [kind] hi lo y mem)
}
v.reset(OpARMLoweredPanicExtendC)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux32, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
x := v_0
y := v_1
v.reset(OpARMSRR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARMRSBconst, y.Type)
v0.AuxInt = 0
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux32, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v3.AuxInt = 256
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpARMSRL)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARMSRAcond)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARMSRAcond)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg3(v0, y, v1)
return true
}
}
v.reset(OpARMSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpARMCMOVWHSconst)
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSRL)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSRAcond)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg3(x, v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSRAcond)
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v0.AuxInt = 256
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg3(x, y, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpARMSRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v3.AuxInt = 256
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARMSRL, x.Type)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpARMSRL)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARMSRAcond)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v2.AuxInt = 256
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARMSRAcond)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
v1 := b.NewValue0(v.Pos, OpARMCMPconst, types.TypeFlags)
v1.AuxInt = 256
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg3(v0, y, v1)
return true
}
}
v.reset(OpARMSRA)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpARMMOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARMMOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARMMOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARMMOVFstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARMMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
ptr := v_0
mem := v_1
v.reset(OpARMMOVBstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] {t} ptr mem)
break
}
v.reset(OpARMMOVHstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] ptr mem)
mem := v_1
v.reset(OpARMMOVBstore)
v.AuxInt = 1
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [4] {t} ptr mem)
break
}
v.reset(OpARMMOVWstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [4] {t} ptr mem)
}
v.reset(OpARMMOVHstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMMOVHstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [4] ptr mem)
mem := v_1
v.reset(OpARMMOVBstore)
v.AuxInt = 3
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v3.AuxInt = 1
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v5.AuxInt = 0
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(ptr, v6, mem)
+ v3.AddArg3(ptr, v4, v5)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [3] ptr mem)
mem := v_1
v.reset(OpARMMOVBstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v1.AuxInt = 1
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARMMOVBstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [s] {t} ptr mem)
}
v.reset(OpARMDUFFZERO)
v.AuxInt = 4 * (128 - s/4)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [s] {t} ptr mem)
}
v.reset(OpARMLoweredZero)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMADDconst, ptr.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(ptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
- v.AddArg(mem)
+ v.AddArg4(ptr, v0, v1, mem)
return true
}
return false
v.AuxInt = 31
v0 := b.NewValue0(v.Pos, OpARMRSBshiftRL, typ.Int32)
v0.AuxInt = 1
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMEQ)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMGT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMLT)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMPshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARMMUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMCMNshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTSTshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQ, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftLLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRLreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARMNE)
v0 := b.NewValue0(v_0.Pos, OpARMTEQshiftRAreg, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
- v0.AddArg(z)
+ v0.AddArg3(x, y, z)
b.AddControl(v0)
return true
}
}
c := v_2_0_0.Args[0]
v.reset(OpARM64ADCSflags)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(c)
+ v.AddArg3(x, y, c)
return true
}
// match: (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (MOVDconst [0]))))
break
}
v.reset(OpARM64ADDSflags)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
continue
}
v.reset(OpARM64MADD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
continue
}
v.reset(OpARM64MSUB)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
continue
}
v.reset(OpARM64MADDW)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
continue
}
v.reset(OpARM64MSUBW)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpARM64SUB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64ADDshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64ADDshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
continue
}
v.reset(OpARM64ROR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
continue
}
v.reset(OpARM64ROR)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpARM64RORW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
continue
}
v.reset(OpARM64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
x2 := v_1
v.reset(OpARM64EXTRconst)
v.AuxInt = 64 - c
- v.AddArg(x2)
- v.AddArg(x)
+ v.AddArg2(x2, x)
return true
}
// match: (ADDshiftLL <t> [c] (UBFX [bfc] x) x2)
}
v.reset(OpARM64EXTRWconst)
v.AuxInt = 32 - c
- v.AddArg(x2)
- v.AddArg(x)
+ v.AddArg2(x2, x)
return true
}
return false
}
y := v_1.Args[0]
v.reset(OpARM64BIC)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64ANDshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64ANDshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64ANDshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64BICshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (BIC x0 x1:(SRLconst [c] y))
}
v.reset(OpARM64BICshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (BIC x0 x1:(SRAconst [c] y))
}
v.reset(OpARM64BICshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
return false
}
v.reset(OpARM64CMNshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64CMNshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64CMNshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64InvertFlags)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
v.reset(OpARM64CMPshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (CMP x0:(SLLconst [c] y) x1)
v.reset(OpARM64InvertFlags)
v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x1)
- v0.AddArg(y)
+ v0.AddArg2(x1, y)
v.AddArg(v0)
return true
}
}
v.reset(OpARM64CMPshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (CMP x0:(SRLconst [c] y) x1)
v.reset(OpARM64InvertFlags)
v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x1)
- v0.AddArg(y)
+ v0.AddArg2(x1, y)
v.AddArg(v0)
return true
}
}
v.reset(OpARM64CMPshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (CMP x0:(SRAconst [c] y) x1)
v.reset(OpARM64InvertFlags)
v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags)
v0.AuxInt = c
- v0.AddArg(x1)
- v0.AddArg(y)
+ v0.AddArg2(x1, y)
v.AddArg(v0)
return true
}
}
v.reset(OpARM64InvertFlags)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
flag := v_2
v.reset(OpARM64CSEL0)
v.Aux = cc
- v.AddArg(x)
- v.AddArg(flag)
+ v.AddArg2(x, flag)
return true
}
// match: (CSEL {cc} (MOVDconst [0]) y flag)
flag := v_2
v.reset(OpARM64CSEL0)
v.Aux = arm64Negate(cc.(Op))
- v.AddArg(y)
- v.AddArg(flag)
+ v.AddArg2(y, flag)
return true
}
// match: (CSEL {cc} x y (InvertFlags cmp))
cmp := v_2.Args[0]
v.reset(OpARM64CSEL)
v.Aux = arm64Invert(cc.(Op))
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cmp)
+ v.AddArg3(x, y, cmp)
return true
}
// match: (CSEL {cc} x _ flag)
}
v.reset(OpARM64CSEL)
v.Aux = boolval.Op
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flagArg(boolval))
+ v.AddArg3(x, y, flagArg(boolval))
return true
}
// match: (CSEL {cc} x y (CMPWconst [0] boolval))
}
v.reset(OpARM64CSEL)
v.Aux = arm64Negate(boolval.Op)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flagArg(boolval))
+ v.AddArg3(x, y, flagArg(boolval))
return true
}
return false
cmp := v_1.Args[0]
v.reset(OpARM64CSEL0)
v.Aux = arm64Invert(cc.(Op))
- v.AddArg(x)
- v.AddArg(cmp)
+ v.AddArg2(x, cmp)
return true
}
// match: (CSEL0 {cc} x flag)
}
v.reset(OpARM64CSEL0)
v.Aux = boolval.Op
- v.AddArg(x)
- v.AddArg(flagArg(boolval))
+ v.AddArg2(x, flagArg(boolval))
return true
}
// match: (CSEL0 {cc} x (CMPWconst [0] boolval))
}
v.reset(OpARM64CSEL0)
v.Aux = arm64Negate(boolval.Op)
- v.AddArg(x)
- v.AddArg(flagArg(boolval))
+ v.AddArg2(x, flagArg(boolval))
return true
}
return false
}
v.reset(OpARM64EONshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (EON x0 x1:(SRLconst [c] y))
}
v.reset(OpARM64EONshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (EON x0 x1:(SRAconst [c] y))
}
v.reset(OpARM64EONshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
return false
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMADDD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMSUBD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMADDS)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMSUBS)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
break
v.reset(OpARM64FMOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVDload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64FMOVDloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64FMOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64FMOVDload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVDloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64FMOVDload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARM64MOVDstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpARM64FMOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARM64FMOVDstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpARM64FMOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64FMOVDstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVDstoreidx (MOVDconst [c]) idx val mem)
mem := v_3
v.reset(OpARM64FMOVDstore)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(idx, val, mem)
return true
}
return false
v.reset(OpARM64FMOVSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVSload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64FMOVSloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64FMOVSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64FMOVSload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVSloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64FMOVSload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARM64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpARM64FMOVSstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARM64FMOVSstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpARM64FMOVSstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64FMOVSstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVSstoreidx (MOVDconst [c]) idx val mem)
mem := v_3
v.reset(OpARM64FMOVSstore)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(idx, val, mem)
return true
}
return false
x := v_0.Args[0]
y := v_1
v.reset(OpARM64FNMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
x := v_0.Args[0]
y := v_1
v.reset(OpARM64FNMULS)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARM64FNMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (FNEGD (FNMULD x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARM64FMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARM64FNMULS)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (FNEGS (FNMULS x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARM64FMULS)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
x := v_0.Args[0]
y := v_1
v.reset(OpARM64FMULD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
x := v_0.Args[0]
y := v_1
v.reset(OpARM64FMULS)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMSUBD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (FSUBD (FMULD x y) a)
x := v_0.Args[0]
a := v_1
v.reset(OpARM64FNMSUBD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (FSUBD a (FNMULD x y))
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMADDD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (FSUBD (FNMULD x y) a)
x := v_0.Args[0]
a := v_1
v.reset(OpARM64FNMADDD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
return false
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMSUBS)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (FSUBS (FMULS x y) a)
x := v_0.Args[0]
a := v_1
v.reset(OpARM64FNMSUBS)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (FSUBS a (FNMULS x y))
y := v_1.Args[1]
x := v_1.Args[0]
v.reset(OpARM64FMADDS)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (FSUBS (FNMULS x y) a)
x := v_0.Args[0]
a := v_1
v.reset(OpARM64FNMADDS)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
return false
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADD a _ (MOVDconst [0]))
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADD a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADD a x (MOVDconst [c]))
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a x (MOVDconst [c]))
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a (MOVDconst [-1]) x)
}
x := v_2
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADD a (MOVDconst [0]) _)
}
x := v_2
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADD a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADD a (MOVDconst [c]) x)
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a (MOVDconst [c]) x)
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADD (MOVDconst [c]) x y)
v.reset(OpARM64ADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADDW a _ (MOVDconst [c]))
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADDW a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADDW a x (MOVDconst [c]))
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a x (MOVDconst [c]))
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADDW a (MOVDconst [c]) _)
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MADDW (MOVDconst [c]) x y)
v.reset(OpARM64ADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpARM64NEG)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = log2(c + 1)
v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = log2(c / 5)
v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v1.AuxInt = 2
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.AuxInt = log2(c / 7)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = log2(c / 9)
v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.reset(OpARM64NEG)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = log2(c + 1)
v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = log2(c / 5)
v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v1.AuxInt = 2
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.AuxInt = log2(c / 7)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = log2(c / 9)
v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v1.AuxInt = 3
- v1.AddArg(x)
- v1.AddArg(x)
+ v1.AddArg2(x, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.reset(OpARM64MOVBUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVBUloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVBUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVBUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVBUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _))
v.reset(OpARM64MOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVBloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVBload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVBload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _))
v.reset(OpARM64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpARM64MOVBstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem)
v.reset(OpARM64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem))
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w0, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w0, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w0, mem)
return true
}
break
v.reset(OpARM64MOVDstore)
v.AuxInt = i - 7
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x6.Pos, OpARM64REV, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem))))))))
continue
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(x5.Pos, OpARM64REV, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 3
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem))))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 3
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem))))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 3
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem))))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
v.reset(OpARM64MOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(ptr)
v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem))
continue
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr0)
- v.AddArg(idx0)
v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr0, idx0, v0, mem)
return true
}
break
mem := v_3
v.reset(OpARM64MOVBstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstoreidx (MOVDconst [c]) idx val mem)
mem := v_3
v.reset(OpARM64MOVBstore)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(idx, val, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVBstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVBreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVBUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVHreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVHUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVWreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx ptr idx (MOVWUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem))
break
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, w, mem)
return true
}
// match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem))))
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpARM64REVW, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, v0, mem)
return true
}
// match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem))))
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, w, mem)
return true
}
// match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem))
break
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type)
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, v0, mem)
return true
}
// match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem))
break
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, w, mem)
return true
}
return false
v.reset(OpARM64MOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVBstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem))
v.reset(OpARM64MOVHstorezero)
v.AuxInt = min(i, j)
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(mem)
+ v.AddArg2(ptr0, mem)
return true
}
// match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem))
continue
}
v.reset(OpARM64MOVHstorezeroidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(mem)
+ v.AddArg3(ptr1, idx1, mem)
return true
}
break
mem := v_2
v.reset(OpARM64MOVBstorezero)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstorezeroidx (MOVDconst [c]) idx mem)
mem := v_2
v.reset(OpARM64MOVBstorezero)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg2(idx, mem)
return true
}
// match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem))
break
}
v.reset(OpARM64MOVHstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpARM64MOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVDloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem)
break
}
v.reset(OpARM64MOVDloadidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVDload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVDload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDloadidx ptr (SLLconst [3] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVDloadidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDloadidx (SLLconst [3] idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVDloadidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _))
mem := v_2
v.reset(OpARM64MOVDload)
v.AuxInt = c << 3
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _))
v.reset(OpARM64FMOVDstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpARM64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem)
break
}
v.reset(OpARM64MOVDstoreidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpARM64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpARM64MOVDstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64MOVDstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstoreidx (MOVDconst [c]) idx val mem)
mem := v_3
v.reset(OpARM64MOVDstore)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(idx, val, mem)
return true
}
// match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVDstoreidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVDstoreidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVDstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64MOVDstore)
v.AuxInt = c << 3
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVDstorezeroidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpARM64MOVDstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVDstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVDstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem)
break
}
v.reset(OpARM64MOVDstorezeroidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem))
v.reset(OpARM64MOVQstorezero)
v.AuxInt = min(i, j)
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(mem)
+ v.AddArg2(ptr0, mem)
return true
}
// match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem))
v.reset(OpARM64MOVQstorezero)
v.AuxInt = 0
v.Aux = s
- v.AddArg(p0)
- v.AddArg(mem)
+ v.AddArg2(p0, mem)
return true
}
break
v.reset(OpARM64MOVQstorezero)
v.AuxInt = 0
v.Aux = s
- v.AddArg(p0)
- v.AddArg(mem)
+ v.AddArg2(p0, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64MOVDstorezero)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDstorezeroidx (MOVDconst [c]) idx mem)
mem := v_2
v.reset(OpARM64MOVDstorezero)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg2(idx, mem)
return true
}
// match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVDstorezeroidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVDstorezeroidx8)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64MOVDstorezero)
v.AuxInt = c << 3
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARM64MOVHUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVHUloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem)
break
}
v.reset(OpARM64MOVHUloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVHUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVHUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVHUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUloadidx ptr (SLLconst [1] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVHUloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHUloadidx ptr (ADD idx idx) mem)
}
mem := v_2
v.reset(OpARM64MOVHUloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHUloadidx (ADD idx idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVHUloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _))
mem := v_2
v.reset(OpARM64MOVHUload)
v.AuxInt = c << 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _))
v.reset(OpARM64MOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVHloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem)
break
}
v.reset(OpARM64MOVHloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVHload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVHload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHloadidx ptr (SLLconst [1] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVHloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHloadidx ptr (ADD idx idx) mem)
}
mem := v_2
v.reset(OpARM64MOVHloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHloadidx (ADD idx idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVHloadidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _))
mem := v_2
v.reset(OpARM64MOVHload)
v.AuxInt = c << 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _))
v.reset(OpARM64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem)
break
}
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpARM64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpARM64MOVHstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpARM64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpARM64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpARM64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem)
v.reset(OpARM64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [i] {s} ptr0 (SRLconst [16] w) x:(MOVHstore [i-2] {s} ptr1 w mem))
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 1
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, v0, w, mem)
return true
}
// match: (MOVHstore [i] {s} ptr0 (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstore [i-2] {s} ptr1 w mem))
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVHstore [2] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 1
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, v0, w, mem)
return true
}
// match: (MOVHstore [i] {s} ptr0 (SRLconst [16] (MOVDreg w)) x:(MOVHstore [i-2] {s} ptr1 w mem))
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 1
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, v0, w, mem)
return true
}
// match: (MOVHstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVHstore [i-2] {s} ptr1 w0:(SRLconst [j-16] w) mem))
v.reset(OpARM64MOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w0, mem)
return true
}
// match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx ptr1 idx1 w0:(SRLconst [j-16] w) mem))
continue
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w0, mem)
return true
}
break
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 1
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, v0, w0, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64MOVHstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstoreidx (MOVDconst [c]) idx val mem)
mem := v_3
v.reset(OpARM64MOVHstore)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(idx, val, mem)
return true
}
// match: (MOVHstoreidx ptr (SLLconst [1] idx) val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstoreidx ptr (ADD idx idx) val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstoreidx (SLLconst [1] idx) ptr val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstoreidx (ADD idx idx) ptr val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstoreidx ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVHstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstoreidx ptr idx (MOVHreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx ptr idx (MOVHUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx ptr idx (MOVWreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx ptr idx (MOVWUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx ptr (ADDconst [2] idx) (SRLconst [16] w) x:(MOVHstoreidx ptr idx w mem))
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, w, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64MOVHstore)
v.AuxInt = c << 1
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVHstorezeroidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstoreidx2 ptr idx (MOVHreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx2 ptr idx (MOVHUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx2 ptr idx (MOVWreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx2 ptr idx (MOVWUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVHstoreidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
return false
v.reset(OpARM64MOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstorezero [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVHstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem)
break
}
v.reset(OpARM64MOVHstorezeroidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstorezero [i] {s} ptr0 x:(MOVHstorezero [j] {s} ptr1 mem))
v.reset(OpARM64MOVWstorezero)
v.AuxInt = min(i, j)
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(mem)
+ v.AddArg2(ptr0, mem)
return true
}
// match: (MOVHstorezero [2] {s} (ADD ptr0 idx0) x:(MOVHstorezeroidx ptr1 idx1 mem))
continue
}
v.reset(OpARM64MOVWstorezeroidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(mem)
+ v.AddArg3(ptr1, idx1, mem)
return true
}
break
break
}
v.reset(OpARM64MOVWstorezeroidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 1
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr1, v0, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64MOVHstorezero)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstorezeroidx (MOVDconst [c]) idx mem)
mem := v_2
v.reset(OpARM64MOVHstorezero)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg2(idx, mem)
return true
}
// match: (MOVHstorezeroidx ptr (SLLconst [1] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVHstorezeroidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstorezeroidx ptr (ADD idx idx) mem)
}
mem := v_2
v.reset(OpARM64MOVHstorezeroidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstorezeroidx (SLLconst [1] idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVHstorezeroidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstorezeroidx (ADD idx idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVHstorezeroidx2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHstorezeroidx ptr (ADDconst [2] idx) x:(MOVHstorezeroidx ptr idx mem))
break
}
v.reset(OpARM64MOVWstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64MOVHstorezero)
v.AuxInt = c << 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARM64MOVQstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVQstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARM64MOVWUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWUload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVWUloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem)
break
}
v.reset(OpARM64MOVWUloadidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVWUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVWUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWUloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVWUload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWUloadidx ptr (SLLconst [2] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVWUloadidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWUloadidx (SLLconst [2] idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVWUloadidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _))
mem := v_2
v.reset(OpARM64MOVWUload)
v.AuxInt = c << 2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _))
v.reset(OpARM64MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVWloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem)
break
}
v.reset(OpARM64MOVWloadidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _))
mem := v_2
v.reset(OpARM64MOVWload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWloadidx (MOVDconst [c]) ptr mem)
mem := v_2
v.reset(OpARM64MOVWload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWloadidx ptr (SLLconst [2] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVWloadidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx (SLLconst [2] idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVWloadidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _))
mem := v_2
v.reset(OpARM64MOVWload)
v.AuxInt = c << 2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _))
v.reset(OpARM64FMOVSstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpARM64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} (ADD ptr idx) val mem)
break
}
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem)
break
}
v.reset(OpARM64MOVWstoreidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpARM64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpARM64MOVWstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpARM64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem)
v.reset(OpARM64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [i] {s} ptr0 (SRLconst [32] w) x:(MOVWstore [i-4] {s} ptr1 w mem))
v.reset(OpARM64MOVDstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w, mem)
return true
}
// match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx ptr1 idx1 w mem))
continue
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w, mem)
return true
}
break
break
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 2
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr1, v0, w, mem)
return true
}
// match: (MOVWstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVWstore [i-4] {s} ptr1 w0:(SRLconst [j-32] w) mem))
v.reset(OpARM64MOVDstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(ptr0, w0, mem)
return true
}
// match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx ptr1 idx1 w0:(SRLconst [j-32] w) mem))
continue
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, idx1, w0, mem)
return true
}
break
break
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 2
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(ptr1, v0, w0, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64MOVWstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstoreidx (MOVDconst [c]) idx val mem)
mem := v_3
v.reset(OpARM64MOVWstore)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(idx, val, mem)
return true
}
// match: (MOVWstoreidx ptr (SLLconst [2] idx) val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVWstoreidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx (SLLconst [2] idx) ptr val mem)
val := v_2
mem := v_3
v.reset(OpARM64MOVWstoreidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstoreidx ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVWstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreidx ptr idx (MOVWreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVWstoreidx ptr idx (MOVWUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVWstoreidx ptr (ADDconst [4] idx) (SRLconst [32] w) x:(MOVWstoreidx ptr idx w mem))
break
}
v.reset(OpARM64MOVDstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, w, mem)
return true
}
return false
mem := v_3
v.reset(OpARM64MOVWstore)
v.AuxInt = c << 2
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem)
}
mem := v_3
v.reset(OpARM64MOVWstorezeroidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstoreidx4 ptr idx (MOVWreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVWstoreidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVWstoreidx4 ptr idx (MOVWUreg x) mem)
x := v_2.Args[0]
mem := v_3
v.reset(OpARM64MOVWstoreidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
return false
v.reset(OpARM64MOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
v.reset(OpARM64MOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstorezero [off] {sym} (ADD ptr idx) mem)
break
}
v.reset(OpARM64MOVWstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem)
break
}
v.reset(OpARM64MOVWstorezeroidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstorezero [i] {s} ptr0 x:(MOVWstorezero [j] {s} ptr1 mem))
v.reset(OpARM64MOVDstorezero)
v.AuxInt = min(i, j)
v.Aux = s
- v.AddArg(ptr0)
- v.AddArg(mem)
+ v.AddArg2(ptr0, mem)
return true
}
// match: (MOVWstorezero [4] {s} (ADD ptr0 idx0) x:(MOVWstorezeroidx ptr1 idx1 mem))
continue
}
v.reset(OpARM64MOVDstorezeroidx)
- v.AddArg(ptr1)
- v.AddArg(idx1)
- v.AddArg(mem)
+ v.AddArg3(ptr1, idx1, mem)
return true
}
break
break
}
v.reset(OpARM64MOVDstorezeroidx)
- v.AddArg(ptr1)
v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type)
v0.AuxInt = 2
v0.AddArg(idx1)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr1, v0, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64MOVWstorezero)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstorezeroidx (MOVDconst [c]) idx mem)
mem := v_2
v.reset(OpARM64MOVWstorezero)
v.AuxInt = c
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg2(idx, mem)
return true
}
// match: (MOVWstorezeroidx ptr (SLLconst [2] idx) mem)
idx := v_1.Args[0]
mem := v_2
v.reset(OpARM64MOVWstorezeroidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstorezeroidx (SLLconst [2] idx) ptr mem)
ptr := v_1
mem := v_2
v.reset(OpARM64MOVWstorezeroidx4)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWstorezeroidx ptr (ADDconst [4] idx) x:(MOVWstorezeroidx ptr idx mem))
break
}
v.reset(OpARM64MOVDstorezeroidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
mem := v_2
v.reset(OpARM64MOVWstorezero)
v.AuxInt = c << 2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUB a _ (MOVDconst [0]))
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUB a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUB a x (MOVDconst [c]))
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a x (MOVDconst [c]))
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a (MOVDconst [-1]) x)
}
x := v_2
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUB a (MOVDconst [0]) _)
}
x := v_2
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUB (MOVDconst [c]) x y)
v.reset(OpARM64ADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARM64MNEG, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUBW a _ (MOVDconst [c]))
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUBW a (MOVDconst [c]) _)
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c)
- v.AddArg(a)
- v.AddArg(x)
+ v.AddArg2(a, x)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
break
}
v.reset(OpARM64SUB)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = log2(c - 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
break
}
v.reset(OpARM64ADD)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = log2(c + 1)
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 3)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 5)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c / 7)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = log2(c / 9)
- v.AddArg(a)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(x, x)
+ v.AddArg2(a, v0)
return true
}
// match: (MSUBW (MOVDconst [c]) x y)
v.reset(OpARM64ADDconst)
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpARM64MNEGW, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
x := v_0.Args[0]
y := v_1
v.reset(OpARM64MNEG)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c - 1)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
break
v.AuxInt = log2(c + 1)
v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 1
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 5)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = 3
v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 9)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
x := v_0.Args[0]
y := v_1
v.reset(OpARM64MNEGW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64ADDshiftLL)
v.AuxInt = log2(c - 1)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
break
v.AuxInt = log2(c + 1)
v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
v.AuxInt = log2(c / 3)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 1
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 5)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 2
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
v0.AuxInt = 3
v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v.AuxInt = log2(c / 9)
v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type)
v0.AuxInt = 3
- v0.AddArg(x)
- v0.AddArg(x)
+ v0.AddArg2(x, x)
v.AddArg(v0)
return true
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARM64MNEG)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (NEG (MULW x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpARM64MNEGW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (NEG (MOVDconst [c]))
}
y := v_1.Args[0]
v.reset(OpARM64ORN)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64ORshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64ORshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64ORshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
continue
}
v.reset(OpARM64ROR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
continue
}
v.reset(OpARM64ROR)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpARM64RORW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
continue
}
v.reset(OpARM64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64BFI)
v.AuxInt = bfc
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
break
}
v.reset(OpARM64BFXIL)
v.AuxInt = bfc
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
break
v1 := b.NewValue0(x3.Pos, OpOffPtr, p.Type)
v1.AuxInt = i0
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
break
v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
- v0.AddArg(idx0)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, idx0, mem)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
break
v1 := b.NewValue0(x7.Pos, OpOffPtr, p.Type)
v1.AuxInt = i0
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
break
v0 := b.NewValue0(x6.Pos, OpARM64MOVDloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
- v0.AddArg(idx0)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, idx0, mem)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
break
v2 := b.NewValue0(x3.Pos, OpOffPtr, p.Type)
v2.AuxInt = i0
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(x3.Pos, OpARM64MOVWUloadidx, t)
- v1.AddArg(ptr0)
- v1.AddArg(idx0)
- v1.AddArg(mem)
+ v1.AddArg3(ptr0, idx0, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t)
- v1.AddArg(ptr)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(ptr, idx, mem)
v0.AddArg(v1)
return true
}
v2 := b.NewValue0(x7.Pos, OpOffPtr, p.Type)
v2.AuxInt = i0
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(x7.Pos, OpARM64MOVDloadidx, t)
- v1.AddArg(ptr0)
- v1.AddArg(idx0)
- v1.AddArg(mem)
+ v1.AddArg3(ptr0, idx0, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t)
- v1.AddArg(ptr)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(ptr, idx, mem)
v0.AddArg(v1)
return true
}
}
v.reset(OpARM64ORNshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (ORN x0 x1:(SRLconst [c] y))
}
v.reset(OpARM64ORNshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (ORN x0 x1:(SRAconst [c] y))
}
v.reset(OpARM64ORNshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
return false
x2 := v_1
v.reset(OpARM64EXTRconst)
v.AuxInt = 64 - c
- v.AddArg(x2)
- v.AddArg(x)
+ v.AddArg2(x2, x)
return true
}
// match: ( ORshiftLL <t> [c] (UBFX [bfc] x) x2)
}
v.reset(OpARM64EXTRWconst)
v.AuxInt = 32 - c
- v.AddArg(x2)
- v.AddArg(x)
+ v.AddArg2(x2, x)
return true
}
// match: (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y))
}
v.reset(OpARM64BFXIL)
v.AuxInt = bfc
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (ORshiftLL <t> [8] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem)))
v1 := b.NewValue0(x1.Pos, OpOffPtr, p.Type)
v1.AuxInt = i0
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (ORshiftLL <t> [8] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem)))
v0 := b.NewValue0(x1.Pos, OpARM64MOVHUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
- v0.AddArg(idx0)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, idx0, mem)
return true
}
break
v0 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (ORshiftLL <t> [24] o0:(ORshiftLL [16] x0:(MOVHUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i3] {s} p mem)))
v1 := b.NewValue0(x2.Pos, OpOffPtr, p.Type)
v1.AuxInt = i0
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (ORshiftLL <t> [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem)))
v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
- v0.AddArg(idx0)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, idx0, mem)
return true
}
break
v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (ORshiftLL <t> [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx2 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADDshiftLL [1] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem)))
v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
v1 := b.NewValue0(x2.Pos, OpARM64SLLconst, idx0.Type)
v1.AuxInt = 1
v1.AddArg(idx0)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, v1, mem)
return true
}
// match: (ORshiftLL <t> [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i4] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i7] {s} p mem)))
v1 := b.NewValue0(x4.Pos, OpOffPtr, p.Type)
v1.AuxInt = i0
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (ORshiftLL <t> [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem)))
v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
- v0.AddArg(idx0)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, idx0, mem)
return true
}
break
v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr0)
v1 := b.NewValue0(x4.Pos, OpARM64SLLconst, idx0.Type)
v1.AuxInt = 2
v1.AddArg(idx0)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg3(ptr0, v1, mem)
return true
}
// match: (ORshiftLL <t> [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [7] idx) mem)))
v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t)
v.reset(OpCopy)
v.AddArg(v0)
- v0.AddArg(ptr)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, idx, mem)
return true
}
// match: (ORshiftLL <t> [8] y0:(MOVDnop x0:(MOVBUload [i1] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i0] {s} p mem)))
v1 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(x0.Pos, OpARM64MOVHUloadidx, t)
- v1.AddArg(ptr0)
- v1.AddArg(idx0)
- v1.AddArg(mem)
+ v1.AddArg3(ptr0, idx0, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t)
- v1.AddArg(ptr)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(ptr, idx, mem)
v0.AddArg(v1)
return true
}
v2 := b.NewValue0(x2.Pos, OpOffPtr, p.Type)
v2.AuxInt = i0
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(x1.Pos, OpARM64MOVWUloadidx, t)
- v1.AddArg(ptr0)
- v1.AddArg(idx0)
- v1.AddArg(mem)
+ v1.AddArg3(ptr0, idx0, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t)
- v1.AddArg(ptr)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(ptr, idx, mem)
v0.AddArg(v1)
return true
}
v2 := b.NewValue0(x4.Pos, OpOffPtr, p.Type)
v2.AuxInt = i0
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(x3.Pos, OpARM64MOVDloadidx, t)
- v1.AddArg(ptr0)
- v1.AddArg(idx0)
- v1.AddArg(mem)
+ v1.AddArg3(ptr0, idx0, mem)
v0.AddArg(v1)
return true
}
v.reset(OpCopy)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t)
- v1.AddArg(ptr)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(ptr, idx, mem)
v0.AddArg(v1)
return true
}
}
v.reset(OpARM64BFI)
v.AuxInt = armBFAuxInt(lc-rc, 64-lc)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ORshiftRL [rc] (ANDconst [ac] y) (SLLconst [lc] x))
}
v.reset(OpARM64BFXIL)
v.AuxInt = armBFAuxInt(rc-lc, 64-rc)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
}
bo := v_2_0_0_0.Args[0]
v.reset(OpARM64SBCSflags)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(bo)
+ v.AddArg3(x, y, bo)
return true
}
// match: (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (MOVDconst [0]))))
break
}
v.reset(OpARM64SUBSflags)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpARM64STP)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val1)
- v.AddArg(val2)
- v.AddArg(mem)
+ v.AddArg4(ptr, val1, val2, mem)
return true
}
// match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
v.reset(OpARM64STP)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val1)
- v.AddArg(val2)
- v.AddArg(mem)
+ v.AddArg4(ptr, val1, val2, mem)
return true
}
// match: (STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem)
v.reset(OpARM64MOVQstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
break
}
v.reset(OpARM64MSUB)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (SUB a l:(MNEG x y))
break
}
v.reset(OpARM64MADD)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (SUB a l:(MULW x y))
x := l.Args[0]
if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) {
break
- }
- v.reset(OpARM64MSUBW)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ }
+ v.reset(OpARM64MSUBW)
+ v.AddArg3(a, x, y)
return true
}
// match: (SUB a l:(MNEGW x y))
break
}
v.reset(OpARM64MADDW)
- v.AddArg(a)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(a, x, y)
return true
}
// match: (SUB x x)
y := v_1.Args[0]
v.reset(OpARM64SUB)
v0 := b.NewValue0(v.Pos, OpARM64ADD, v.Type)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(y)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, y)
return true
}
// match: (SUB (SUB x y) z)
x := v_0.Args[0]
z := v_1
v.reset(OpARM64SUB)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64ADD, y.Type)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
// match: (SUB x0 x1:(SLLconst [c] y))
}
v.reset(OpARM64SUBshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (SUB x0 x1:(SRLconst [c] y))
}
v.reset(OpARM64SUBshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
// match: (SUB x0 x1:(SRAconst [c] y))
}
v.reset(OpARM64SUBshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
return false
}
v.reset(OpARM64TSTshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64TSTshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64TSTshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
y := v_1
v.reset(OpARM64MSUB)
v.Type = typ.UInt64
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpARM64UDIV, typ.UInt64)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
+ v.AddArg3(x, y, v0)
return true
}
// match: (UMOD _ (MOVDconst [1]))
y := v_1
v.reset(OpARM64MSUBW)
v.Type = typ.UInt32
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpARM64UDIVW, typ.UInt32)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
+ v.AddArg3(x, y, v0)
return true
}
// match: (UMODW _ (MOVDconst [c]))
}
y := v_1.Args[0]
v.reset(OpARM64EON)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpARM64XORshiftLL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64XORshiftRL)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
}
v.reset(OpARM64XORshiftRA)
v.AuxInt = c
- v.AddArg(x0)
- v.AddArg(y)
+ v.AddArg2(x0, y)
return true
}
break
continue
}
v.reset(OpARM64ROR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
continue
}
v.reset(OpARM64ROR)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpARM64RORW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
continue
}
v.reset(OpARM64RORW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
x2 := v_1
v.reset(OpARM64EXTRconst)
v.AuxInt = 64 - c
- v.AddArg(x2)
- v.AddArg(x)
+ v.AddArg2(x2, x)
return true
}
// match: (XORshiftLL <t> [c] (UBFX [bfc] x) x2)
}
v.reset(OpARM64EXTRWconst)
v.AuxInt = 32 - c
- v.AddArg(x2)
- v.AddArg(x)
+ v.AddArg2(x2, x)
return true
}
return false
mem := v_2
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8, types.NewTuple(typ.UInt8, types.TypeMem))
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, val, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8, types.NewTuple(typ.UInt8, types.TypeMem))
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, val, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t)
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpARM64SUB, t)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpARM64SUB)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 32
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SUB)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 64
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
}
v.reset(OpARM64CSEL)
v.Aux = boolval.Op
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(flagArg(boolval))
+ v.AddArg3(x, y, flagArg(boolval))
return true
}
// match: (CondSelect x y boolval)
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64NotEqual
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(boolval)
- v.AddArg(v0)
+ v.AddArg3(x, y, v0)
return true
}
return false
v.reset(OpARM64DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64UDIVW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64UDIVW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64Equal)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64Equal)
v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64Equal)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64Equal)
v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpARM64XOR)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool)
- v1.AddArg(x)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(x, y)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpARM64Equal)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
z := v_2
v.reset(OpARM64FMADDD)
- v.AddArg(z)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(z, x, y)
return true
}
}
y := v_1
v.reset(OpARM64GreaterEqualF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64GreaterEqualF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64GreaterThanF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64GreaterThanF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpARM64SRAconst)
v.AuxInt = 32
v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpARM64SRAconst)
v.AuxInt = 32
v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpARM64LessThanU)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpARM64LessEqualU)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessEqual)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessEqualF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessEqualU)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessEqual)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessEqualF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessEqualU)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessThan)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessThanF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessThanU)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessThan)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessThanF)
v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64LessThanU)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
break
}
v.reset(OpARM64MOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVHUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVWUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64MOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64FMOVSload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpARM64FMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64MODW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64UMODW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64MODW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64UMODW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(OpARM64MOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(OpARM64MOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(OpARM64MOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] dst src mem)
src := v_1
mem := v_2
v.reset(OpARM64MOVDstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpARM64MOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [5] dst src mem)
mem := v_2
v.reset(OpARM64MOVBstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] dst src mem)
mem := v_2
v.reset(OpARM64MOVHstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [7] dst src mem)
mem := v_2
v.reset(OpARM64MOVBstore)
v.AuxInt = 6
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8)
v0.AuxInt = 6
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [12] dst src mem)
mem := v_2
v.reset(OpARM64MOVWstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [16] dst src mem)
mem := v_2
v.reset(OpARM64MOVDstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [24] dst src mem)
mem := v_2
v.reset(OpARM64MOVDstore)
v.AuxInt = 16
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
v0.AuxInt = 16
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
v2.AuxInt = 8
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = s - s%8
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = s - s%8
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem)
v2.AuxInt = s - s%8
- v2.AddArg(dst)
- v2.AddArg(src)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg3(dst, src, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpARM64MOVDstore)
v.AuxInt = s - 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64)
v0.AuxInt = s - 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpARM64DUFFCOPY, types.TypeMem)
v1.AuxInt = 8 * (64 - (s-8)/16)
- v1.AddArg(dst)
- v1.AddArg(src)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, src, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpARM64DUFFCOPY)
v.AuxInt = 8 * (64 - s/16)
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Move [s] dst src mem)
break
}
v.reset(OpARM64LoweredMove)
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpARM64ADDconst, src.Type)
v0.AuxInt = s - 8
v0.AddArg(src)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64NotEqual)
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64NotEqual)
v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64NotEqual)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64NotEqual)
v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpARM64NotEqual)
v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpARM64XOR)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpARM64LoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpARM64LoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpARM64LoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
x := v_0
y := v_1
v.reset(OpARM64RORW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpARM64ROR)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpConst64, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpConst64, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpARM64CSEL)
v.Aux = OpARM64LessThanU
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
x := v_0
y := v_1
v.reset(OpARM64SRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v0.Aux = OpARM64LessThanU
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst64, y.Type)
v2.AuxInt = 63
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpARM64SRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v0.Aux = OpARM64LessThanU
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst64, y.Type)
v2.AuxInt = 63
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpARM64SRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v0.Aux = OpARM64LessThanU
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpConst64, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpARM64SRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v0.Aux = OpARM64LessThanU
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst64, y.Type)
v2.AuxInt = 63
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
+ v.AddArg2(x, v0)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpARM64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpConst64, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpARM64SRA)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type)
v1.Aux = OpARM64LessThanU
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpConst64, y.Type)
v3.AuxInt = 63
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags)
v4.AuxInt = 64
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags))
v2.AuxInt = -1
v2.AddArg(c)
v1.AddArg(v2)
- v0.AddArg(v1)
+ v0.AddArg3(x, y, v1)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags))
v2.AddArg(bo)
v1.AddArg(v2)
- v0.AddArg(v1)
+ v0.AddArg3(x, y, v1)
v.AddArg(v0)
return true
}
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags))
- v1.AddArg(x)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags))
v3.AuxInt = -1
v3.AddArg(c)
v2.AddArg(v3)
- v1.AddArg(v2)
+ v1.AddArg3(x, y, v2)
v0.AddArg(v1)
v.AddArg(v0)
return true
v0 := b.NewValue0(v.Pos, OpARM64NGCzerocarry, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags))
- v2.AddArg(x)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags))
v4.AddArg(bo)
v3.AddArg(v4)
- v2.AddArg(v3)
+ v2.AddArg3(x, y, v3)
v1.AddArg(v2)
v0.AddArg(v1)
v.AddArg(v0)
break
}
v.reset(OpARM64MOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARM64MOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARM64MOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARM64MOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARM64FMOVSstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpARM64FMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
ptr := v_0
mem := v_1
v.reset(OpARM64MOVBstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] ptr mem)
ptr := v_0
mem := v_1
v.reset(OpARM64MOVHstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [4] ptr mem)
ptr := v_0
mem := v_1
v.reset(OpARM64MOVWstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [8] ptr mem)
ptr := v_0
mem := v_1
v.reset(OpARM64MOVDstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [3] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem)
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [5] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 4
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [6] ptr mem)
mem := v_1
v.reset(OpARM64MOVHstore)
v.AuxInt = 4
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [7] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 6
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [9] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 8
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [10] ptr mem)
mem := v_1
v.reset(OpARM64MOVHstore)
v.AuxInt = 8
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [11] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 10
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [12] ptr mem)
mem := v_1
v.reset(OpARM64MOVWstore)
v.AuxInt = 8
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [13] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 12
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [14] ptr mem)
mem := v_1
v.reset(OpARM64MOVHstore)
v.AuxInt = 12
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [15] ptr mem)
mem := v_1
v.reset(OpARM64MOVBstore)
v.AuxInt = 14
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem)
v1.AuxInt = 12
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem)
v3.AuxInt = 8
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem)
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(ptr, v6, mem)
+ v3.AddArg3(ptr, v4, v5)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [16] ptr mem)
mem := v_1
v.reset(OpARM64STP)
v.AuxInt = 0
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
- v.AddArg(mem)
+ v.AddArg4(ptr, v0, v1, mem)
return true
}
// match: (Zero [32] ptr mem)
mem := v_1
v.reset(OpARM64STP)
v.AuxInt = 16
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem)
v2.AuxInt = 0
- v2.AddArg(ptr)
v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v3.AuxInt = 0
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v2.AddArg(v4)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg4(ptr, v3, v4, mem)
+ v.AddArg4(ptr, v0, v1, v2)
return true
}
// match: (Zero [48] ptr mem)
mem := v_1
v.reset(OpARM64STP)
v.AuxInt = 32
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem)
v2.AuxInt = 16
- v2.AddArg(ptr)
v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v3.AuxInt = 0
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v2.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem)
v5.AuxInt = 0
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v6.AuxInt = 0
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v7.AuxInt = 0
- v5.AddArg(v7)
- v5.AddArg(mem)
- v2.AddArg(v5)
- v.AddArg(v2)
+ v5.AddArg4(ptr, v6, v7, mem)
+ v2.AddArg4(ptr, v3, v4, v5)
+ v.AddArg4(ptr, v0, v1, v2)
return true
}
// match: (Zero [64] ptr mem)
mem := v_1
v.reset(OpARM64STP)
v.AuxInt = 48
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem)
v2.AuxInt = 32
- v2.AddArg(ptr)
v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v3.AuxInt = 0
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v4.AuxInt = 0
- v2.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem)
v5.AuxInt = 16
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v6.AuxInt = 0
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v7.AuxInt = 0
- v5.AddArg(v7)
v8 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem)
v8.AuxInt = 0
- v8.AddArg(ptr)
v9 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v9.AuxInt = 0
- v8.AddArg(v9)
v10 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
v10.AuxInt = 0
- v8.AddArg(v10)
- v8.AddArg(mem)
- v5.AddArg(v8)
- v2.AddArg(v5)
- v.AddArg(v2)
+ v8.AddArg4(ptr, v9, v10, mem)
+ v5.AddArg4(ptr, v6, v7, v8)
+ v2.AddArg4(ptr, v3, v4, v5)
+ v.AddArg4(ptr, v0, v1, v2)
return true
}
// match: (Zero [s] ptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type)
v0.AuxInt = s - 8
v0.AddArg(ptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v1.AuxInt = s - s%16
- v1.AddArg(ptr)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(ptr, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [s] ptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type)
v0.AuxInt = s - 16
v0.AddArg(ptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v1.AuxInt = s - s%16
- v1.AddArg(ptr)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(ptr, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [s] ptr mem)
}
v.reset(OpARM64DUFFZERO)
v.AuxInt = 4 * (64 - s/16)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Zero [s] ptr mem)
break
}
v.reset(OpARM64LoweredZero)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64ADDconst, ptr.Type)
v0.AuxInt = s - 16
v0.AddArg(ptr)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64EQ)
v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64GT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64LT)
v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
}
b.Reset(BlockARM64NE)
v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags)
- v0.AddArg(a)
v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
+ v1.AddArg2(x, y)
+ v0.AddArg2(a, v1)
b.AddControl(v0)
return true
}
y := v_1
c := v_2
v.reset(OpMIPSADD)
- v.AddArg(c)
v0 := b.NewValue0(v.Pos, OpMIPSADD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
+ v.AddArg2(c, v0)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSAND, typ.UInt32Ptr)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = ^3
- v0.AddArg(v1)
- v0.AddArg(ptr)
- v.AddArg(v0)
+ v0.AddArg2(v1, ptr)
v2 := b.NewValue0(v.Pos, OpMIPSOR, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(val)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPSSLLconst, typ.UInt32)
v5.AuxInt = 3
v6 := b.NewValue0(v.Pos, OpMIPSANDconst, typ.UInt32)
v6.AuxInt = 3
v6.AddArg(ptr)
v5.AddArg(v6)
- v3.AddArg(v5)
- v2.AddArg(v3)
+ v3.AddArg2(v4, v5)
v7 := b.NewValue0(v.Pos, OpMIPSNORconst, typ.UInt32)
v7.AuxInt = 0
v8 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
v9 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v9.AuxInt = 0xff
- v8.AddArg(v9)
v10 := b.NewValue0(v.Pos, OpMIPSSLLconst, typ.UInt32)
v10.AuxInt = 3
v11 := b.NewValue0(v.Pos, OpMIPSANDconst, typ.UInt32)
v11.AuxInt = 3
v11.AddArg(ptr)
v10.AddArg(v11)
- v8.AddArg(v10)
+ v8.AddArg2(v9, v10)
v7.AddArg(v8)
- v2.AddArg(v7)
- v.AddArg(v2)
- v.AddArg(mem)
+ v2.AddArg2(v3, v7)
+ v.AddArg3(v0, v2, mem)
return true
}
// match: (AtomicAnd8 ptr val mem)
v0 := b.NewValue0(v.Pos, OpMIPSAND, typ.UInt32Ptr)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = ^3
- v0.AddArg(v1)
- v0.AddArg(ptr)
- v.AddArg(v0)
+ v0.AddArg2(v1, ptr)
v2 := b.NewValue0(v.Pos, OpMIPSOR, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(val)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPSSLLconst, typ.UInt32)
v5.AuxInt = 3
v6 := b.NewValue0(v.Pos, OpMIPSANDconst, typ.UInt32)
v7.AddArg(ptr)
v6.AddArg(v7)
v5.AddArg(v6)
- v3.AddArg(v5)
- v2.AddArg(v3)
+ v3.AddArg2(v4, v5)
v8 := b.NewValue0(v.Pos, OpMIPSNORconst, typ.UInt32)
v8.AuxInt = 0
v9 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
v10 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v10.AuxInt = 0xff
- v9.AddArg(v10)
v11 := b.NewValue0(v.Pos, OpMIPSSLLconst, typ.UInt32)
v11.AuxInt = 3
v12 := b.NewValue0(v.Pos, OpMIPSANDconst, typ.UInt32)
v13.AddArg(ptr)
v12.AddArg(v13)
v11.AddArg(v12)
- v9.AddArg(v11)
+ v9.AddArg2(v10, v11)
v8.AddArg(v9)
- v2.AddArg(v8)
- v.AddArg(v2)
- v.AddArg(mem)
+ v2.AddArg2(v3, v8)
+ v.AddArg3(v0, v2, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpMIPSAND, typ.UInt32Ptr)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = ^3
- v0.AddArg(v1)
- v0.AddArg(ptr)
- v.AddArg(v0)
+ v0.AddArg2(v1, ptr)
v2 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v3.AddArg(val)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSLLconst, typ.UInt32)
v4.AuxInt = 3
v5 := b.NewValue0(v.Pos, OpMIPSANDconst, typ.UInt32)
v5.AuxInt = 3
v5.AddArg(ptr)
v4.AddArg(v5)
- v2.AddArg(v4)
- v.AddArg(v2)
- v.AddArg(mem)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v2, mem)
return true
}
// match: (AtomicOr8 ptr val mem)
v0 := b.NewValue0(v.Pos, OpMIPSAND, typ.UInt32Ptr)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = ^3
- v0.AddArg(v1)
- v0.AddArg(ptr)
- v.AddArg(v0)
+ v0.AddArg2(v1, ptr)
v2 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v3.AddArg(val)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSLLconst, typ.UInt32)
v4.AuxInt = 3
v5 := b.NewValue0(v.Pos, OpMIPSANDconst, typ.UInt32)
v6.AddArg(ptr)
v5.AddArg(v6)
v4.AddArg(v5)
- v2.AddArg(v4)
- v.AddArg(v2)
- v.AddArg(mem)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v2, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpMIPSSRLconst, t)
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpMIPSSUB, t)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpMIPSSUB)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 32
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCLZ, t)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSUB)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 32
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCLZ, t)
v2 := b.NewValue0(v.Pos, OpMIPSSUBconst, t)
v2.AuxInt = 1
v3 := b.NewValue0(v.Pos, OpMIPSAND, t)
- v3.AddArg(x)
v4 := b.NewValue0(v.Pos, OpMIPSNEG, t)
v4.AddArg(x)
- v3.AddArg(v4)
+ v3.AddArg2(x, v4)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSDIV, types.NewTuple(typ.Int32, typ.Int32))
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIVU, types.NewTuple(typ.UInt32, typ.UInt32))
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPSDIV, types.NewTuple(typ.Int32, typ.Int32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPSDIVU, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIV, types.NewTuple(typ.Int32, typ.Int32))
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIVU, types.NewTuple(typ.UInt32, typ.UInt32))
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpMIPSSGTUconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPEQF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPEQD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpMIPSXORconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.Bool)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpMIPSSGTUconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGEF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGED, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGTF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGTD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPSMULT, types.NewTuple(typ.Int32, typ.Int32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPSMULTU, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
idx := v_0
len := v_1
v.reset(OpMIPSSGTU)
- v.AddArg(len)
- v.AddArg(idx)
+ v.AddArg2(len, idx)
return true
}
}
for {
ptr := v_0
v.reset(OpMIPSSGTU)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
+ v.AddArg2(ptr, v0)
return true
}
}
v.reset(OpMIPSXORconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSSGT, typ.Bool)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpMIPSXORconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSSGT, typ.Bool)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGEF, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpMIPSXORconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGED, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSSGT, typ.Bool)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpMIPSSGT)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSGTU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPSSGT)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGTF, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
x := v_0
y := v_1
v.reset(OpMIPSSGTU)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
y := v_1
v.reset(OpMIPSFPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPSCMPGTD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpMIPSSGT)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSGTU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpMIPSMOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVHUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVFload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPSMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v2.AuxInt = 32
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v2.AuxInt = 32
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v2.AuxInt = 32
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSLL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
}
y := v_1.Args[0]
v.reset(OpMIPSSUB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpMIPSSGTUconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpMIPSOR, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
}
c := v_2
v.reset(OpMIPSCMOVZzero)
- v.AddArg(a)
- v.AddArg(c)
+ v.AddArg2(a, c)
return true
}
return false
}
v.reset(OpMIPSLoweredAtomicAddconst)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
mem := v_2
v.reset(OpMIPSLoweredAtomicStorezero)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPSMOVBUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVBUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBUreg (ANDconst [c] x))
v.reset(OpMIPSMOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVBreg (ANDconst [c] x))
v.reset(OpMIPSMOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPSMOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWconst [0]) mem)
v.reset(OpMIPSMOVBstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
v.reset(OpMIPSMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem)
v.reset(OpMIPSMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpMIPSMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpMIPSMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpMIPSMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpMIPSMOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPSMOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _))
v.reset(OpMIPSMOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPSMOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpMIPSMOVFload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVFload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _))
v.reset(OpMIPSMOVFstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPSMOVFstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpMIPSMOVHUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVHUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVHUreg (ANDconst [c] x))
v.reset(OpMIPSMOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _))
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
// match: (MOVHreg (ANDconst [c] x))
v.reset(OpMIPSMOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPSMOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWconst [0]) mem)
v.reset(OpMIPSMOVHstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpMIPSMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpMIPSMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpMIPSMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpMIPSMOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPSMOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
v.reset(OpMIPSMOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPSMOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWconst [0]) mem)
v.reset(OpMIPSMOVWstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpMIPSMOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpMIPSMOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPSMOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
y := v_1.Args[0]
v.reset(OpMIPSSGTUzero)
v0 := b.NewValue0(v.Pos, OpMIPSOR, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIV, types.NewTuple(typ.Int32, typ.Int32))
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIVU, types.NewTuple(typ.UInt32, typ.UInt32))
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPSDIV, types.NewTuple(typ.Int32, typ.Int32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPSDIVU, types.NewTuple(typ.UInt32, typ.UInt32))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIV, types.NewTuple(typ.Int32, typ.Int32))
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSDIVU, types.NewTuple(typ.UInt32, typ.UInt32))
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
src := v_1
mem := v_2
v.reset(OpMIPSMOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] {t} dst src mem)
break
}
v.reset(OpMIPSMOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVHUload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
mem := v_2
v.reset(OpMIPSMOVBstore)
v.AuxInt = 1
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
v0.AuxInt = 1
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [4] {t} dst src mem)
break
}
v.reset(OpMIPSMOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] {t} dst src mem)
}
v.reset(OpMIPSMOVHstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVHUload, typ.UInt16)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVHUload, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [4] dst src mem)
mem := v_2
v.reset(OpMIPSMOVBstore)
v.AuxInt = 3
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
v0.AuxInt = 3
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
v2.AuxInt = 2
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v3.AuxInt = 1
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
v4.AuxInt = 1
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
+ v4.AddArg2(src, mem)
v5 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
- v5.AddArg(dst)
v6 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
- v6.AddArg(src)
- v6.AddArg(mem)
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v6.AddArg2(src, mem)
+ v5.AddArg3(dst, v6, mem)
+ v3.AddArg3(dst, v4, v5)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpMIPSMOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v1.AuxInt = 1
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
v2.AuxInt = 1
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPSMOVBUload, typ.UInt8)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [8] {t} dst src mem)
}
v.reset(OpMIPSMOVWstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [8] {t} dst src mem)
}
v.reset(OpMIPSMOVHstore)
v.AuxInt = 6
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
v0.AuxInt = 6
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
v3.AuxInt = 2
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
v4.AuxInt = 2
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
+ v4.AddArg2(src, mem)
v5 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
- v5.AddArg(dst)
v6 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
- v6.AddArg(src)
- v6.AddArg(mem)
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v6.AddArg2(src, mem)
+ v5.AddArg3(dst, v6, mem)
+ v3.AddArg3(dst, v4, v5)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] {t} dst src mem)
}
v.reset(OpMIPSMOVHstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
v2.AuxInt = 2
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPSMOVHload, typ.Int16)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [12] {t} dst src mem)
}
v.reset(OpMIPSMOVWstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [16] {t} dst src mem)
}
v.reset(OpMIPSMOVWstore)
v.AuxInt = 12
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
v0.AuxInt = 12
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
v2.AuxInt = 8
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v3.AuxInt = 4
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
v4.AuxInt = 4
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
+ v4.AddArg2(src, mem)
v5 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
- v5.AddArg(dst)
v6 := b.NewValue0(v.Pos, OpMIPSMOVWload, typ.UInt32)
- v6.AddArg(src)
- v6.AddArg(mem)
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v6.AddArg2(src, mem)
+ v5.AddArg3(dst, v6, mem)
+ v3.AddArg3(dst, v4, v5)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] {t} dst src mem)
}
v.reset(OpMIPSLoweredMove)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpMIPSADDconst, src.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(src)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
y := v_1
v.reset(OpMIPSSGTU)
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPSFPFlagFalse)
v0 := b.NewValue0(v.Pos, OpMIPSCMPEQF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPSFPFlagFalse)
v0 := b.NewValue0(v.Pos, OpMIPSCMPEQD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
y := v_1
v.reset(OpMIPSSGTU)
v0 := b.NewValue0(v.Pos, OpMIPSXOR, typ.UInt32)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
}
v.reset(OpMIPSLoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpMIPSLoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpMIPSLoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
}
v.reset(OpMIPSLoweredPanicExtendA)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
// match: (PanicExtend [kind] hi lo y mem)
}
v.reset(OpMIPSLoweredPanicExtendB)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
// match: (PanicExtend [kind] hi lo y mem)
}
v.reset(OpMIPSLoweredPanicExtendC)
v.AuxInt = kind
- v.AddArg(hi)
- v.AddArg(lo)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg4(hi, lo, y, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux32, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr32)
v0 := b.NewValue0(v.Pos, OpLsh32x32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = c & 31
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh32Ux32, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -c & 31
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr64)
v0 := b.NewValue0(v.Pos, OpLsh64x32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = c & 63
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh64Ux32, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -c & 63
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux32, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v.reset(OpMIPSSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -1
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = -1
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -1
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v2.AuxInt = 32
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
v.reset(OpMIPSCMOVZ)
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPSSRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = -1
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPSSRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = -1
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v2.AuxInt = 32
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPSSRA)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = -1
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v4.AddArg(y)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
+ v.AddArg2(x, v0)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPSSRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v.AddArg(v4)
+ v.AddArg3(v0, v3, v4)
return true
}
}
v.reset(OpMIPSSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -1
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = -1
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v3.AuxInt = 32
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPSSRA)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSCMOVZ, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v3.AuxInt = -1
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPSSGTUconst, typ.Bool)
v4.AuxInt = 32
v5 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v5.AddArg(y)
v4.AddArg(v5)
- v1.AddArg(v4)
- v.AddArg(v1)
+ v1.AddArg3(v2, v3, v4)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0.Args[0]
v.reset(OpMIPSADD)
v.Type = t.FieldType(0)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Select0 (Sub32carry <t> x y))
x := v_0.Args[0]
v.reset(OpMIPSSUB)
v.Type = t.FieldType(0)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Select0 (MULTU (MOVWconst [0]) _ ))
v0 := b.NewValue0(v.Pos, OpMIPSADDconst, x.Type)
v0.AuxInt = -1
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v.AddArg(v1)
- v.AddArg(x)
+ v.AddArg3(v0, v1, x)
return true
}
break
x := v_0.Args[0]
v.reset(OpMIPSSGTU)
v.Type = typ.Bool
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPSADD, t.FieldType(0))
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
+ v.AddArg2(x, v0)
return true
}
// match: (Select1 (Sub32carry <t> x y))
v.reset(OpMIPSSGTU)
v.Type = typ.Bool
v0 := b.NewValue0(v.Pos, OpMIPSSUB, t.FieldType(0))
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(x)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, x)
return true
}
// match: (Select1 (MULTU (MOVWconst [0]) _ ))
break
}
v.reset(OpMIPSMOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPSMOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPSMOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPSMOVFstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPSMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
c := v_2
v.reset(OpMIPSSUB)
v0 := b.NewValue0(v.Pos, OpMIPSSUB, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
- v.AddArg(c)
+ v0.AddArg2(x, y)
+ v.AddArg2(v0, c)
return true
}
}
ptr := v_0
mem := v_1
v.reset(OpMIPSMOVBstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] {t} ptr mem)
break
}
v.reset(OpMIPSMOVHstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] ptr mem)
mem := v_1
v.reset(OpMIPSMOVBstore)
v.AuxInt = 1
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [4] {t} ptr mem)
break
}
v.reset(OpMIPSMOVWstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [4] {t} ptr mem)
}
v.reset(OpMIPSMOVHstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [4] ptr mem)
mem := v_1
v.reset(OpMIPSMOVBstore)
v.AuxInt = 3
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v3.AuxInt = 1
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v5.AuxInt = 0
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(ptr, v6, mem)
+ v3.AddArg3(ptr, v4, v5)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [3] ptr mem)
mem := v_1
v.reset(OpMIPSMOVBstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v1.AuxInt = 1
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVBstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [6] {t} ptr mem)
}
v.reset(OpMIPSMOVHstore)
v.AuxInt = 4
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVHstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [8] {t} ptr mem)
}
v.reset(OpMIPSMOVWstore)
v.AuxInt = 4
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [12] {t} ptr mem)
}
v.reset(OpMIPSMOVWstore)
v.AuxInt = 8
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [16] {t} ptr mem)
}
v.reset(OpMIPSMOVWstore)
v.AuxInt = 12
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v3.AuxInt = 4
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPSMOVWstore, types.TypeMem)
v5.AuxInt = 0
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(ptr, v6, mem)
+ v3.AddArg3(ptr, v4, v5)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [s] {t} ptr mem)
}
v.reset(OpMIPSLoweredZero)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSADDconst, ptr.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(ptr)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
x := v_0
v.reset(OpMIPSNEG)
v0 := b.NewValue0(v.Pos, OpMIPSSGTU, typ.Bool)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
v1.AuxInt = 0
- v0.AddArg(v1)
+ v0.AddArg2(x, v1)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64SRLVconst, t)
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpMIPS64SUBV, t)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpMIPS64NOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpMIPS64NOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpMIPS64NOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpMIPS64NOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPEQF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
- v1.AddArg(x)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(x, y)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPEQD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.Bool)
- v1.AddArg(x)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(x, y)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
- v1.AddArg(x)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(x, y)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGEF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGED, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGTF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGTD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpMIPS64MULV, types.NewTuple(typ.Int64, typ.Int64))
v2 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
v.AddArg(v0)
return true
v1 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
v.AddArg(v0)
return true
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPS64MULV, types.NewTuple(typ.Int64, typ.Int64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
idx := v_0
len := v_1
v.reset(OpMIPS64SGTU)
- v.AddArg(len)
- v.AddArg(idx)
+ v.AddArg2(len, idx)
return true
}
}
for {
ptr := v_0
v.reset(OpMIPS64SGTU)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
+ v.AddArg2(ptr, v0)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
- v1.AddArg(idx)
- v1.AddArg(len)
- v.AddArg(v1)
+ v1.AddArg2(idx, len)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGT, typ.Bool)
v2 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGT, typ.Bool)
v2 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGEF, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGT, typ.Bool)
- v1.AddArg(x)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(x, y)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGED, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
- v1.AddArg(x)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(x, y)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGT, typ.Bool)
v2 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64XOR)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg2(v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SGT)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SGT)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGTF, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPS64SGT)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagTrue)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPGTD, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
x := v_0
y := v_1
v.reset(OpMIPS64SGTU)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
v.reset(OpMIPS64SGT)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpMIPS64MOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVHUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVWUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVVload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVFload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpMIPS64MOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v3.AddArg(x)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(x, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v3.AddArg(x)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(x, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v3.AddArg(x)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(x, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v3.AddArg(x)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(x, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SLLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
}
y := v_1.Args[0]
v.reset(OpMIPS64SUBV)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpMIPS64LoweredAtomicAddconst32)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpMIPS64LoweredAtomicAddconst64)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
mem := v_2
v.reset(OpMIPS64LoweredAtomicStorezero32)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
mem := v_2
v.reset(OpMIPS64LoweredAtomicStorezero64)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVBUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVBUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem)
v.reset(OpMIPS64MOVBstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem)
v.reset(OpMIPS64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpMIPS64MOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPS64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpMIPS64MOVFload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVFload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVFstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPS64MOVFstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpMIPS64MOVHUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVHUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPS64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem)
v.reset(OpMIPS64MOVHstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpMIPS64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem)
v.reset(OpMIPS64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpMIPS64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem)
v.reset(OpMIPS64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpMIPS64MOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVVload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVVload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVVstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPS64MOVVstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem)
v.reset(OpMIPS64MOVVstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVVstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVVstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVWUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVWUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpMIPS64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
v.reset(OpMIPS64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem)
v.reset(OpMIPS64MOVWstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem)
mem := v_2
v.reset(OpMIPS64MOVWstore)
v.AuxInt = off
- v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.Aux = sym
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem)
v.reset(OpMIPS64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpMIPS64MOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
v.reset(OpMIPS64MOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect0)
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVV, types.NewTuple(typ.Int64, typ.Int64))
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64DIVVU, types.NewTuple(typ.UInt64, typ.UInt64))
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
src := v_1
mem := v_2
v.reset(OpMIPS64MOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] {t} dst src mem)
break
}
v.reset(OpMIPS64MOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
mem := v_2
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 1
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
v0.AuxInt = 1
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [4] {t} dst src mem)
break
}
v.reset(OpMIPS64MOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVWload, typ.Int32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] {t} dst src mem)
}
v.reset(OpMIPS64MOVHstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [4] dst src mem)
mem := v_2
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 3
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
v0.AuxInt = 3
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
v2.AuxInt = 2
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v3.AuxInt = 1
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
v4.AuxInt = 1
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
+ v4.AddArg2(src, mem)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
- v5.AddArg(dst)
v6 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
- v6.AddArg(src)
- v6.AddArg(mem)
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v6.AddArg2(src, mem)
+ v5.AddArg3(dst, v6, mem)
+ v3.AddArg3(dst, v4, v5)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [8] {t} dst src mem)
break
}
v.reset(OpMIPS64MOVVstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVload, typ.UInt64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] {t} dst src mem)
}
v.reset(OpMIPS64MOVWstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVWload, typ.Int32)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVWload, typ.Int32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [8] {t} dst src mem)
}
v.reset(OpMIPS64MOVHstore)
v.AuxInt = 6
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
v0.AuxInt = 6
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v3.AuxInt = 2
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
v4.AuxInt = 2
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
+ v4.AddArg2(src, mem)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
- v5.AddArg(dst)
v6 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
- v6.AddArg(src)
- v6.AddArg(mem)
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v6.AddArg2(src, mem)
+ v5.AddArg3(dst, v6, mem)
+ v3.AddArg3(dst, v4, v5)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v1.AuxInt = 1
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
v2.AuxInt = 1
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVBload, typ.Int8)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] {t} dst src mem)
}
v.reset(OpMIPS64MOVHstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
v2.AuxInt = 2
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVHload, typ.Int16)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [12] {t} dst src mem)
}
v.reset(OpMIPS64MOVWstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVWload, typ.Int32)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVWstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVWload, typ.Int32)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVWstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVWload, typ.Int32)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [16] {t} dst src mem)
}
v.reset(OpMIPS64MOVVstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVload, typ.UInt64)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [24] {t} dst src mem)
}
v.reset(OpMIPS64MOVVstore)
v.AuxInt = 16
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVload, typ.UInt64)
v0.AuxInt = 16
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVload, typ.UInt64)
v2.AuxInt = 8
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVload, typ.UInt64)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] {t} dst src mem)
}
v.reset(OpMIPS64DUFFCOPY)
v.AuxInt = 16 * (128 - s/8)
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Move [s] {t} dst src mem)
}
v.reset(OpMIPS64LoweredMove)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpMIPS64ADDVconst, src.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(src)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpSelect1)
v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagFalse)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPEQF, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpMIPS64FPFlagFalse)
v0 := b.NewValue0(v.Pos, OpMIPS64CMPEQD, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
y := v_1
v.reset(OpMIPS64SGTU)
v0 := b.NewValue0(v.Pos, OpMIPS64XOR, typ.UInt64)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
}
v.reset(OpMIPS64LoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpMIPS64LoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpMIPS64LoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr32)
v0 := b.NewValue0(v.Pos, OpLsh32x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v1.AuxInt = c & 31
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh32Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = -c & 31
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr64)
v0 := b.NewValue0(v.Pos, OpLsh64x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v1.AuxInt = c & 63
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh64Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = -c & 63
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(x)
- v3.AddArg(v4)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(v4, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
- v3.AddArg(y)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 63
- v3.AddArg(v4)
+ v3.AddArg2(y, v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(v2, y)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(x)
- v3.AddArg(v4)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(v4, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
- v3.AddArg(y)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 63
- v3.AddArg(v4)
+ v3.AddArg2(y, v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(v2, y)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
- v3.AddArg(x)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(x, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPS64SRAV)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v1 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v2 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 63
- v2.AddArg(v4)
+ v2.AddArg2(v3, v4)
v1.AddArg(v2)
- v0.AddArg(v1)
v5 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v5.AddArg(y)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPS64SRAV)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v1 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v2 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 63
- v2.AddArg(v4)
+ v2.AddArg2(v3, v4)
v1.AddArg(v2)
- v0.AddArg(v1)
v5 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v5.AddArg(y)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPS64SRAV)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v1 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v2 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v3.AuxInt = 63
- v2.AddArg(v3)
+ v2.AddArg2(y, v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpMIPS64SRAV)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v1 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v2 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 63
- v2.AddArg(v4)
+ v2.AddArg2(v3, v4)
v1.AddArg(v2)
- v0.AddArg(v1)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(y)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
+ v.AddArg2(x, v0)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
- v1.AddArg(y)
+ v1.AddArg2(v2, y)
v0.AddArg(v1)
- v.AddArg(v0)
v3 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(x)
- v3.AddArg(v4)
- v3.AddArg(y)
- v.AddArg(v3)
+ v3.AddArg2(v4, y)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 64
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v3.AddArg(y)
- v1.AddArg(v3)
+ v1.AddArg2(v2, v3)
v0.AddArg(v1)
- v.AddArg(v0)
v4 := b.NewValue0(v.Pos, OpMIPS64SRLV, t)
v5 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v6.AddArg(y)
- v4.AddArg(v6)
- v.AddArg(v4)
+ v4.AddArg2(v5, v6)
+ v.AddArg2(v0, v4)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
- v3.AddArg(y)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 63
- v3.AddArg(v4)
+ v3.AddArg2(y, v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v1.AddArg(y)
- v.AddArg(v1)
+ v1.AddArg2(v2, y)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMIPS64SRAV)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64OR, t)
v2 := b.NewValue0(v.Pos, OpMIPS64NEGV, t)
v3 := b.NewValue0(v.Pos, OpMIPS64SGTU, typ.Bool)
v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v4.AddArg(y)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v5.AuxInt = 63
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v1.AddArg(v2)
v6 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v6.AddArg(y)
- v1.AddArg(v6)
- v.AddArg(v1)
+ v1.AddArg2(v2, v6)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpMIPS64MOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPS64MOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPS64MOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPS64MOVVstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPS64MOVFstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpMIPS64MOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
ptr := v_0
mem := v_1
v.reset(OpMIPS64MOVBstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] {t} ptr mem)
break
}
v.reset(OpMIPS64MOVHstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] ptr mem)
mem := v_1
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 1
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [4] {t} ptr mem)
break
}
v.reset(OpMIPS64MOVWstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [4] {t} ptr mem)
}
v.reset(OpMIPS64MOVHstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [4] ptr mem)
mem := v_1
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 3
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v3.AuxInt = 1
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v5.AuxInt = 0
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(ptr, v6, mem)
+ v3.AddArg3(ptr, v4, v5)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [8] {t} ptr mem)
break
}
v.reset(OpMIPS64MOVVstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [8] {t} ptr mem)
}
v.reset(OpMIPS64MOVWstore)
v.AuxInt = 4
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVWstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [8] {t} ptr mem)
}
v.reset(OpMIPS64MOVHstore)
v.AuxInt = 6
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v3.AuxInt = 2
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v5.AuxInt = 0
- v5.AddArg(ptr)
v6 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(ptr, v6, mem)
+ v3.AddArg3(ptr, v4, v5)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [3] ptr mem)
mem := v_1
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 2
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v1.AuxInt = 1
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVBstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [6] {t} ptr mem)
}
v.reset(OpMIPS64MOVHstore)
v.AuxInt = 4
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v1.AuxInt = 2
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVHstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [12] {t} ptr mem)
}
v.reset(OpMIPS64MOVWstore)
v.AuxInt = 8
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVWstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVWstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [16] {t} ptr mem)
}
v.reset(OpMIPS64MOVVstore)
v.AuxInt = 8
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVstore, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(ptr, v2, mem)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [24] {t} ptr mem)
}
v.reset(OpMIPS64MOVVstore)
v.AuxInt = 16
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(ptr)
v2 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpMIPS64MOVVstore, types.TypeMem)
v3.AuxInt = 0
- v3.AddArg(ptr)
v4 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(ptr, v4, mem)
+ v1.AddArg3(ptr, v2, v3)
+ v.AddArg3(ptr, v0, v1)
return true
}
// match: (Zero [s] {t} ptr mem)
}
v.reset(OpMIPS64DUFFZERO)
v.AuxInt = 8 * (128 - s/8)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Zero [s] {t} ptr mem)
}
v.reset(OpMIPS64LoweredZero)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64ADDVconst, ptr.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(ptr)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
return false
mem := v_3
v.reset(OpPPC64LoweredAtomicCas32)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(old)
- v.AddArg(new_)
- v.AddArg(mem)
+ v.AddArg4(ptr, old, new_, mem)
return true
}
}
mem := v_3
v.reset(OpPPC64LoweredAtomicCas64)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(old)
- v.AddArg(new_)
- v.AddArg(mem)
+ v.AddArg4(ptr, old, new_, mem)
return true
}
}
mem := v_3
v.reset(OpPPC64LoweredAtomicCas32)
v.AuxInt = 0
- v.AddArg(ptr)
- v.AddArg(old)
- v.AddArg(new_)
- v.AddArg(mem)
+ v.AddArg4(ptr, old, new_, mem)
return true
}
}
mem := v_1
v.reset(OpPPC64LoweredAtomicLoad32)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
}
mem := v_1
v.reset(OpPPC64LoweredAtomicLoad64)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
}
mem := v_1
v.reset(OpPPC64LoweredAtomicLoad8)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
}
mem := v_1
v.reset(OpPPC64LoweredAtomicLoad32)
v.AuxInt = 0
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
}
mem := v_1
v.reset(OpPPC64LoweredAtomicLoadPtr)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
}
mem := v_2
v.reset(OpPPC64LoweredAtomicStore32)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
}
mem := v_2
v.reset(OpPPC64LoweredAtomicStore64)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
}
mem := v_2
v.reset(OpPPC64LoweredAtomicStore8)
v.AuxInt = 1
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
}
mem := v_2
v.reset(OpPPC64LoweredAtomicStore32)
v.AuxInt = 0
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
}
v0 := b.NewValue0(v.Pos, OpPPC64SRDconst, t)
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpPPC64SUB, t)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpPPC64SUB)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 32
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64CNTLZW, typ.Int)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SUB)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 64
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64CNTLZD, typ.Int)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
for {
x := v_0
v.reset(OpPPC64NOR)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
}
for {
x := v_0
v.reset(OpPPC64NOR)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
}
for {
x := v_0
v.reset(OpPPC64NOR)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
}
for {
x := v_0
v.reset(OpPPC64NOR)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
}
}
v.reset(OpPPC64ISEL)
v.AuxInt = 2
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(bool)
+ v.AddArg3(x, y, bool)
return true
}
// match: (CondSelect x y bool)
}
v.reset(OpPPC64ISEL)
v.AuxInt = 2
- v.AddArg(x)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags)
v0.AuxInt = 0
v0.AddArg(bool)
- v.AddArg(v0)
+ v.AddArg3(x, y, v0)
return true
}
return false
x := v_0
y := v_1
v.reset(OpPPC64FCPSGN)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int16)
v2.AuxInt = -1
v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
+ v1.AddArg2(v2, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int)
v2.AuxInt = -1
v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
+ v1.AddArg2(v2, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v1 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int64)
v1.AuxInt = -1
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.UInt8)
v2.AuxInt = -1
v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
+ v1.AddArg2(v2, x)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.reset(OpPPC64DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64DIVWU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64DIVWU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64Equal)
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64Equal)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64Equal)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64Equal)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v.reset(OpPPC64ANDconst)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpPPC64EQV, typ.Int64)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64Equal)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FGreaterEqual)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FGreaterEqual)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FGreaterThan)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FGreaterThan)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpPPC64LessThan)
v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
len := v_1
v.reset(OpPPC64LessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags)
- v0.AddArg(idx)
- v0.AddArg(len)
+ v0.AddArg2(idx, len)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FLessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FLessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessThan)
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FLessThan)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessThan)
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessThan)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64FLessThan)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64LessThan)
v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
break
}
v.reset(OpPPC64MOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64MOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64MOVWZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64MOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64MOVHZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64MOVBZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpPPC64MOVBreg)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8)
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
break
}
v.reset(OpPPC64MOVBZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64FMOVSload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpPPC64FMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -16
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -16
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x64 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -16
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -16
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x64 x (AND y (MOVDconst [31])))
continue
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32)
v0.AuxInt = 31
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32)
v0.AuxInt = 31
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh32x64 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x64 x (AND y (MOVDconst [63])))
continue
}
v.reset(OpPPC64SLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64)
v0.AuxInt = 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpPPC64SLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64)
v0.AuxInt = 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh64x64 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -8
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -8
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x64 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -8
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -8
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpMod32)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMod32u)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
y := v_1
v.reset(OpPPC64SUB)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64DIVW, typ.Int32)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(x, y)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpPPC64SUB)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64DIVWU, typ.Int32)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(x, y)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpPPC64SUB)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64DIVD, typ.Int64)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(x, y)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
y := v_1
v.reset(OpPPC64SUB)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64DIVDU, typ.Int64)
- v1.AddArg(x)
- v1.AddArg(y)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(x, y)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpMod32)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMod32u)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(OpPPC64MOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(OpPPC64MOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(OpPPC64MOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] {t} dst src mem)
break
}
v.reset(OpPPC64MOVDstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] dst src mem)
mem := v_2
v.reset(OpPPC64MOVWstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpPPC64MOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpPPC64MOVHload, typ.Int16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [5] dst src mem)
mem := v_2
v.reset(OpPPC64MOVBstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] dst src mem)
mem := v_2
v.reset(OpPPC64MOVHstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [7] dst src mem)
mem := v_2
v.reset(OpPPC64MOVBstore)
v.AuxInt = 6
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8)
v0.AuxInt = 6
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpPPC64LoweredMove)
v.AuxInt = s
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64NotEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64NotEqual)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64NotEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64NotEqual)
v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpPPC64NotEqual)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpPPC64ADD)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = off
- v.AddArg(v0)
- v.AddArg(ptr)
+ v.AddArg2(v0, ptr)
return true
}
}
continue
}
v.reset(OpPPC64ROTL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpPPC64ROTLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpPPC64ANDN)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpPPC64InvertFlags)
v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
v.reset(OpPPC64InvertFlags)
v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
y := v_1.Args[0]
v.reset(OpPPC64CMPW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPW (MOVWreg x) y)
x := v_0.Args[0]
y := v_1
v.reset(OpPPC64CMPW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPW x (MOVDconst [c]))
}
v.reset(OpPPC64InvertFlags)
v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
y := v_1.Args[0]
v.reset(OpPPC64CMPWU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWU (MOVWZreg x) y)
x := v_0.Args[0]
y := v_1
v.reset(OpPPC64CMPWU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWU x (MOVDconst [c]))
}
v.reset(OpPPC64InvertFlags)
v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.AuxInt = 2
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
x := v_0.Args[0]
z := v_1
v.reset(OpPPC64FMADD)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
x := v_0.Args[0]
z := v_1
v.reset(OpPPC64FMADDS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.AuxInt = 2
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ISELB, typ.Int32)
v1.AuxInt = 1
v2 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v2.AuxInt = 1
- v1.AddArg(v2)
- v1.AddArg(cmp)
- v.AddArg(v1)
- v.AddArg(cmp)
+ v1.AddArg2(v2, cmp)
+ v.AddArg3(v0, v1, cmp)
return true
}
}
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
v.AuxInt = 2
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ISELB, typ.Int32)
v1.AuxInt = 0
v2 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v2.AuxInt = 1
- v1.AddArg(v2)
- v1.AddArg(cmp)
- v.AddArg(v1)
- v.AddArg(cmp)
+ v1.AddArg2(v2, cmp)
+ v.AddArg3(v0, v1, cmp)
return true
}
}
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
v.reset(OpPPC64FMOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
v.reset(OpPPC64FMOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVDstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpPPC64FMOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpPPC64FMOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpPPC64FMOVSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
v.reset(OpPPC64FMOVSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64FMOVSstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpPPC64FMOVSstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
x := v_0.Args[0]
z := v_1
v.reset(OpPPC64FMSUB)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
return false
x := v_0.Args[0]
z := v_1
v.reset(OpPPC64FMSUBS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
return false
v.AuxInt = 4
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
}
v.reset(OpPPC64ISEL)
v.AuxInt = n + 1
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(bool)
+ v.AddArg3(x, y, bool)
return true
}
// match: (ISEL [n] x y (InvertFlags bool))
}
v.reset(OpPPC64ISEL)
v.AuxInt = n - 1
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(bool)
+ v.AddArg3(x, y, bool)
return true
}
// match: (ISEL [n] x y (InvertFlags bool))
}
v.reset(OpPPC64ISEL)
v.AuxInt = n
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(bool)
+ v.AddArg3(x, y, bool)
return true
}
return false
v.AuxInt = n + 1
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(bool)
+ v.AddArg2(v0, bool)
return true
}
// match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool))
v.AuxInt = n - 1
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(bool)
+ v.AddArg2(v0, bool)
return true
}
// match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool))
v.AuxInt = n
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(bool)
+ v.AddArg2(v0, bool)
return true
}
return false
v.AuxInt = 5
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
v.AuxInt = 0
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVBZload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBZload [off1] {sym} (ADDconst [off2] x) mem)
v.reset(OpPPC64MOVBZload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVBZload [0] {sym} p:(ADD ptr idx) mem)
break
}
v.reset(OpPPC64MOVBZloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(OpPPC64MOVBZload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBZloadidx (MOVDconst [c]) ptr mem)
}
v.reset(OpPPC64MOVBZload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(x, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off] {sym} p:(ADD ptr idx) val mem)
break
}
v.reset(OpPPC64MOVBstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBZreg x) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVHZreg x) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVWZreg x) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (SRWconst (MOVHreg x) [c]) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (SRWconst (MOVHZreg x) [c]) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (SRWconst (MOVWreg x) [c]) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (SRWconst (MOVWZreg x) [c]) mem)
v.reset(OpPPC64MOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (MOVBstore [i1] {s} p (SRWconst w [24]) x0:(MOVBstore [i0] {s} p (SRWconst w [16]) mem))
v.reset(OpPPC64MOVHstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x0.Pos, OpPPC64SRWconst, typ.UInt16)
v0.AuxInt = 16
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVBstore [i1] {s} p (SRDconst w [24]) x0:(MOVBstore [i0] {s} p (SRDconst w [16]) mem))
v.reset(OpPPC64MOVHstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x0.Pos, OpPPC64SRWconst, typ.UInt16)
v0.AuxInt = 16
v0.AddArg(w)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
// match: (MOVBstore [i1] {s} p (SRWconst w [8]) x0:(MOVBstore [i0] {s} p w mem))
v.reset(OpPPC64MOVHstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i1] {s} p (SRDconst w [8]) x0:(MOVBstore [i0] {s} p w mem))
v.reset(OpPPC64MOVHstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i3] {s} p w x0:(MOVBstore [i2] {s} p (SRWconst w [8]) x1:(MOVBstore [i1] {s} p (SRWconst w [16]) x2:(MOVBstore [i0] {s} p (SRWconst w [24]) mem))))
v0.AuxInt = i0
v0.Aux = s
v0.AddArg(p)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(v0, w, mem)
return true
}
// match: (MOVBstore [i1] {s} p w x0:(MOVBstore [i0] {s} p (SRWconst w [8]) mem))
v0.AuxInt = i0
v0.Aux = s
v0.AddArg(p)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(v0, w, mem)
return true
}
// match: (MOVBstore [i7] {s} p (SRDconst w [56]) x0:(MOVBstore [i6] {s} p (SRDconst w [48]) x1:(MOVBstore [i5] {s} p (SRDconst w [40]) x2:(MOVBstore [i4] {s} p (SRDconst w [32]) x3:(MOVWstore [i0] {s} p w mem)))))
v.reset(OpPPC64MOVDstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i7] {s} p w x0:(MOVBstore [i6] {s} p (SRDconst w [8]) x1:(MOVBstore [i5] {s} p (SRDconst w [16]) x2:(MOVBstore [i4] {s} p (SRDconst w [24]) x3:(MOVBstore [i3] {s} p (SRDconst w [32]) x4:(MOVBstore [i2] {s} p (SRDconst w [40]) x5:(MOVBstore [i1] {s} p (SRDconst w [48]) x6:(MOVBstore [i0] {s} p (SRDconst w [56]) mem))))))))
v0.AuxInt = i0
v0.Aux = s
v0.AddArg(p)
- v.AddArg(v0)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(v0, w, mem)
return true
}
return false
}
v.reset(OpPPC64MOVBstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstoreidx (MOVDconst [c]) ptr val mem)
}
v.reset(OpPPC64MOVBstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (MOVBreg x) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (MOVBZreg x) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (MOVHreg x) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (MOVHZreg x) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (MOVWreg x) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (MOVWZreg x) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVHreg x) [c]) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, v0, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVHZreg x) [c]) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, v0, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVWreg x) [c]) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, v0, mem)
return true
}
// match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVWZreg x) [c]) mem)
v.reset(OpPPC64MOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32)
v0.AuxInt = c
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, v0, mem)
return true
}
return false
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem)
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
return false
v.reset(OpPPC64MOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off1] {sym} (ADDconst [off2] x) mem)
v.reset(OpPPC64MOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVDload [0] {sym} p:(ADD ptr idx) mem)
break
}
v.reset(OpPPC64MOVDloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(OpPPC64MOVDload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDloadidx (MOVDconst [c]) ptr mem)
}
v.reset(OpPPC64MOVDload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64FMOVDstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem)
v.reset(OpPPC64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(x, val, mem)
return true
}
// match: (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpPPC64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpPPC64MOVDstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDstore [off] {sym} p:(ADD ptr idx) val mem)
break
}
v.reset(OpPPC64MOVDstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
}
v.reset(OpPPC64MOVDstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstoreidx (MOVDconst [c]) ptr val mem)
}
v.reset(OpPPC64MOVDstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
v.reset(OpPPC64MOVDstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem)
v.reset(OpPPC64MOVDstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
return false
mem := v_2
v.reset(OpPPC64MOVHBRstore)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHBRstore {sym} ptr (MOVHZreg x) mem)
mem := v_2
v.reset(OpPPC64MOVHBRstore)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHBRstore {sym} ptr (MOVWreg x) mem)
mem := v_2
v.reset(OpPPC64MOVHBRstore)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHBRstore {sym} ptr (MOVWZreg x) mem)
mem := v_2
v.reset(OpPPC64MOVHBRstore)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpPPC64MOVHZload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHZload [off1] {sym} (ADDconst [off2] x) mem)
v.reset(OpPPC64MOVHZload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVHZload [0] {sym} p:(ADD ptr idx) mem)
break
}
v.reset(OpPPC64MOVHZloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(OpPPC64MOVHZload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHZloadidx (MOVDconst [c]) ptr mem)
}
v.reset(OpPPC64MOVHZload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off1] {sym} (ADDconst [off2] x) mem)
v.reset(OpPPC64MOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVHload [0] {sym} p:(ADD ptr idx) mem)
break
}
v.reset(OpPPC64MOVHloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(OpPPC64MOVHload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHloadidx (MOVDconst [c]) ptr mem)
}
v.reset(OpPPC64MOVHload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(x, val, mem)
return true
}
// match: (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpPPC64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpPPC64MOVHstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstore [off] {sym} p:(ADD ptr idx) val mem)
break
}
v.reset(OpPPC64MOVHstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem)
v.reset(OpPPC64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHZreg x) mem)
v.reset(OpPPC64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpPPC64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVWZreg x) mem)
v.reset(OpPPC64MOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [i1] {s} p (SRWconst w [16]) x0:(MOVHstore [i0] {s} p w mem))
v.reset(OpPPC64MOVWstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVHstore [i1] {s} p (SRDconst w [16]) x0:(MOVHstore [i0] {s} p w mem))
v.reset(OpPPC64MOVWstore)
v.AuxInt = i0
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
return false
}
v.reset(OpPPC64MOVHstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstoreidx (MOVDconst [c]) ptr val mem)
}
v.reset(OpPPC64MOVHstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstoreidx [off] {sym} ptr idx (MOVHreg x) mem)
v.reset(OpPPC64MOVHstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx [off] {sym} ptr idx (MOVHZreg x) mem)
v.reset(OpPPC64MOVHstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx [off] {sym} ptr idx (MOVWreg x) mem)
v.reset(OpPPC64MOVHstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVHstoreidx [off] {sym} ptr idx (MOVWZreg x) mem)
v.reset(OpPPC64MOVHstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
return false
v.reset(OpPPC64MOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem)
v.reset(OpPPC64MOVHstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
return false
mem := v_2
v.reset(OpPPC64MOVWBRstore)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWBRstore {sym} ptr (MOVWZreg x) mem)
mem := v_2
v.reset(OpPPC64MOVWBRstore)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
v.reset(OpPPC64MOVWZload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWZload [off1] {sym} (ADDconst [off2] x) mem)
v.reset(OpPPC64MOVWZload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVWZload [0] {sym} p:(ADD ptr idx) mem)
break
}
v.reset(OpPPC64MOVWZloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(OpPPC64MOVWZload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWZloadidx (MOVDconst [c]) ptr mem)
}
v.reset(OpPPC64MOVWZload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym} (ADDconst [off2] x) mem)
v.reset(OpPPC64MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVWload [0] {sym} p:(ADD ptr idx) mem)
break
}
v.reset(OpPPC64MOVWloadidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
}
v.reset(OpPPC64MOVWload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWloadidx (MOVDconst [c]) ptr mem)
}
v.reset(OpPPC64MOVWload)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpPPC64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(x, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem)
v.reset(OpPPC64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem)
v.reset(OpPPC64MOVWstorezero)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off] {sym} p:(ADD ptr idx) val mem)
break
}
v.reset(OpPPC64MOVWstoreidx)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem)
v.reset(OpPPC64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWZreg x) mem)
v.reset(OpPPC64MOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
return false
}
v.reset(OpPPC64MOVWstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstoreidx (MOVDconst [c]) ptr val mem)
}
v.reset(OpPPC64MOVWstore)
v.AuxInt = c
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstoreidx [off] {sym} ptr idx (MOVWreg x) mem)
v.reset(OpPPC64MOVWstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
// match: (MOVWstoreidx [off] {sym} ptr idx (MOVWZreg x) mem)
v.reset(OpPPC64MOVWstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, x, mem)
return true
}
return false
v.reset(OpPPC64MOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
// match: (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem)
v.reset(OpPPC64MOVWstorezero)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg2(x, mem)
return true
}
return false
v.AddArg(v0)
v0.AuxInt = off
v0.Aux = sym
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
return true
}
return false
v.AuxInt = 6
v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(cmp)
+ v.AddArg2(v0, cmp)
return true
}
}
continue
}
v.reset(OpPPC64ROTL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpPPC64ROTLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
break
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
break
v2.AuxInt = i0
v2.Aux = s
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v2.AuxInt = i0
v2.Aux = s
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
v2.AuxInt = i0
v2.Aux = s
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v2.AuxInt = i0
v2.Aux = s
v2.AddArg(p)
- v1.AddArg(v2)
- v1.AddArg(mem)
+ v1.AddArg2(v2, mem)
v0.AddArg(v1)
return true
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
v1.AuxInt = i0
v1.Aux = s
v1.AddArg(p)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
}
continue
}
v.reset(OpPPC64ROTL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
continue
}
v.reset(OpPPC64ROTLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpPPC64LoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpPPC64LoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
break
}
v.reset(OpPPC64LoweredPanicBoundsC)
- v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AuxInt = kind
+ v.AddArg3(x, y, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
x := v_0
y := v_1
v.reset(OpPPC64ROTLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
x := v_0
y := v_1
v.reset(OpPPC64ROTL)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux16 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux32 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux64 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux8 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x16 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x32 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x64 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x8 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -16
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpPPC64SRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux64 x (AND y (MOVDconst [31])))
continue
}
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32)
v0.AuxInt = 31
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v0.AuxInt = 31
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux64 x (SUB <typ.UInt> (MOVDconst [32]) (ANDconst <typ.UInt> [31] y)))
}
y := v_1_1.Args[0]
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 32
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 31
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux64 x (SUB <typ.UInt> (MOVDconst [32]) (AND <typ.UInt> y (MOVDconst [31]))))
continue
}
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 32
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 31
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
break
x := v_0
y := v_1
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x64 x (AND y (MOVDconst [31])))
continue
}
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32)
v0.AuxInt = 31
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v0.AuxInt = 31
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x64 x (SUB <typ.UInt> (MOVDconst [32]) (ANDconst <typ.UInt> [31] y)))
}
y := v_1_1.Args[0]
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 32
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 31
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x64 x (SUB <typ.UInt> (MOVDconst [32]) (AND <typ.UInt> y (MOVDconst [31]))))
continue
}
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 32
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 31
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
break
x := v_0
y := v_1
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -32
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux64 x (AND y (MOVDconst [63])))
continue
}
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64)
v0.AuxInt = 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v0.AuxInt = 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux64 x (SUB <typ.UInt> (MOVDconst [64]) (ANDconst <typ.UInt> [63] y)))
}
y := v_1_1.Args[0]
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 64
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 63
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux64 x (SUB <typ.UInt> (MOVDconst [64]) (AND <typ.UInt> y (MOVDconst [63]))))
continue
}
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 64
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 63
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
break
x := v_0
y := v_1
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x16 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x32 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x64 x (AND y (MOVDconst [63])))
continue
}
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64)
v0.AuxInt = 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v0.AuxInt = 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x64 x (SUB <typ.UInt> (MOVDconst [64]) (ANDconst <typ.UInt> [63] y)))
}
y := v_1_1.Args[0]
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 64
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 63
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x64 x (SUB <typ.UInt> (MOVDconst [64]) (AND <typ.UInt> y (MOVDconst [63]))))
continue
}
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64)
v1.AuxInt = 64
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt)
v2.AuxInt = 63
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
+ v.AddArg2(x, v0)
return true
}
break
x := v_0
y := v_1
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpPPC64SRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x8 x y)
x := v_0
y := v_1
v.reset(OpPPC64SRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v2.AuxInt = -64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux16 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux32 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux64 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux8 x y)
v.reset(OpPPC64SRW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x16 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x32 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x64 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x8 x y)
v.reset(OpPPC64SRAW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64)
v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags)
v3.AuxInt = -8
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpPPC64FMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpPPC64FMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpPPC64FMOVSstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpPPC64MOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpPPC64MOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpPPC64MOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpPPC64MOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
destptr := v_0
mem := v_1
v.reset(OpPPC64MOVBstorezero)
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [2] destptr mem)
destptr := v_0
mem := v_1
v.reset(OpPPC64MOVHstorezero)
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [3] destptr mem)
mem := v_1
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = 2
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem)
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [4] destptr mem)
destptr := v_0
mem := v_1
v.reset(OpPPC64MOVWstorezero)
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [5] destptr mem)
mem := v_1
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = 4
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem)
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [6] destptr mem)
mem := v_1
v.reset(OpPPC64MOVHstorezero)
v.AuxInt = 4
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem)
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [7] destptr mem)
mem := v_1
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = 6
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem)
v0.AuxInt = 4
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem)
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(destptr, mem)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [8] {t} destptr mem)
break
}
v.reset(OpPPC64MOVDstorezero)
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [8] destptr mem)
mem := v_1
v.reset(OpPPC64MOVWstorezero)
v.AuxInt = 4
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [12] {t} destptr mem)
}
v.reset(OpPPC64MOVWstorezero)
v.AuxInt = 8
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [16] {t} destptr mem)
}
v.reset(OpPPC64MOVDstorezero)
v.AuxInt = 8
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [24] {t} destptr mem)
}
v.reset(OpPPC64MOVDstorezero)
v.AuxInt = 16
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v0.AuxInt = 8
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v1.AuxInt = 0
- v1.AddArg(destptr)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(destptr, mem)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [32] {t} destptr mem)
}
v.reset(OpPPC64MOVDstorezero)
v.AuxInt = 24
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v0.AuxInt = 16
- v0.AddArg(destptr)
v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem)
v2.AuxInt = 0
- v2.AddArg(destptr)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v2.AddArg2(destptr, mem)
+ v1.AddArg2(destptr, v2)
+ v0.AddArg2(destptr, v1)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] ptr mem)
mem := v_1
v.reset(OpPPC64LoweredZero)
v.AuxInt = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
}
}
b.Reset(BlockPPC64EQ)
v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64EQ)
v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64EQ)
v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64GE)
v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64GE)
v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64GE)
v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64GT)
v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64GT)
v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64GT)
v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64LE)
v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64LE)
v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64LE)
v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64LT)
v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64LT)
v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64LT)
v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64NE)
v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64NE)
v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
}
b.Reset(BlockPPC64NE)
v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
b.AddControl(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpRISCV64SRLI, t)
v1.AuxInt = 1
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpRISCV64SRLI, t)
v2.AuxInt = 1
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpRISCV64ANDI, t)
v3.AuxInt = 1
v4 := b.NewValue0(v.Pos, OpRISCV64AND, t)
- v4.AddArg(x)
- v4.AddArg(y)
+ v4.AddArg2(x, y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
}
v.reset(OpRISCV64DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64DIVUW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64DIVW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64DIVUW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64SEQZ)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
y := v_1
v.reset(OpRISCV64SEQZ)
v0 := b.NewValue0(v.Pos, OpRISCV64SUBW, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpRISCV64SEQZ)
v0 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpRISCV64SEQZ)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
v.reset(OpRISCV64XORI)
v.AuxInt = 1
v0 := b.NewValue0(v.Pos, OpRISCV64XOR, typ.Bool)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpRISCV64SEQZ)
v0 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
x := v_0
y := v_1
v.reset(OpRISCV64FLES)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
x := v_0
y := v_1
v.reset(OpRISCV64FLED)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
x := v_0
y := v_1
v.reset(OpRISCV64FLTS)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
x := v_0
y := v_1
v.reset(OpRISCV64FLTD)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64MUL, typ.Int64)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpRISCV64MUL, typ.Int64)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
p := v_0
v.reset(OpNeqPtr)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
- v.AddArg(v0)
- v.AddArg(p)
+ v.AddArg2(v0, p)
return true
}
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess16, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess16U, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess32, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess32U, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess64, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess64U, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess8, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpNot)
v0 := b.NewValue0(v.Pos, OpLess8U, typ.Bool)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v.reset(OpRISCV64SLT)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64SLTU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64SLT)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64SLTU)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64SLT)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64SLTU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpRISCV64MOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVBUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVHUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVWUload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64MOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64FMOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpRISCV64FMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg16, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg16, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg16, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg16, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg32, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg32, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg32, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg32, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg8, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg8, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg8, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg8, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64REMW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64REMUW)
v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64REMW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64REMUW)
v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(OpRISCV64MOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVBload, typ.Int8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(OpRISCV64MOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVHload, typ.Int16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(OpRISCV64MOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVWload, typ.Int32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] dst src mem)
src := v_1
mem := v_2
v.reset(OpRISCV64MOVDstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [s] {t} dst src mem)
mem := v_2
v.reset(OpRISCV64LoweredMove)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpRISCV64ADDI, src.Type)
v0.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
v0.AddArg(src)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg4(dst, src, v0, mem)
return true
}
}
v.reset(OpRISCV64MULW)
v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpRISCV64MULW)
v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
v.reset(OpRISCV64SUB)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVHconst, typ.UInt16)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
x := v_0
v.reset(OpRISCV64SUB)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVWconst, typ.UInt32)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
x := v_0
v.reset(OpRISCV64SUB)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
x := v_0
v.reset(OpRISCV64SUB)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVBconst, typ.UInt8)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpRISCV64SNEZ)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
y := v_1
v.reset(OpRISCV64SNEZ)
v0 := b.NewValue0(v.Pos, OpRISCV64SUBW, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
y := v_1
v.reset(OpRISCV64SNEZ)
v0 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpRISCV64SNEZ)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
v.AddArg(v0)
return true
y := v_1
v.reset(OpRISCV64SNEZ)
v0 := b.NewValue0(v.Pos, OpRISCV64SUB, x.Type)
- v0.AddArg(x)
- v0.AddArg(y)
+ v0.AddArg2(x, y)
v.AddArg(v0)
return true
}
v.reset(OpRISCV64ADD)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v0.AuxInt = off
- v.AddArg(v0)
- v.AddArg(ptr)
+ v.AddArg2(v0, ptr)
return true
}
}
}
v.reset(OpRISCV64LoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpRISCV64LoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpRISCV64LoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
v.reset(OpRISCV64MOVBUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBUload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVBUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVBstore [off1] {sym} (ADDI [off2] base) val mem)
v.reset(OpRISCV64MOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v1.AuxInt = c>>32 + 1
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v2.AuxInt = int64(int32(c))
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (MOVDconst <t> [c])
v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v1.AuxInt = c>>32 + 0
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v2.AuxInt = int64(int32(c))
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
return false
v.reset(OpRISCV64MOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVDload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVDstore [off1] {sym} (ADDI [off2] base) val mem)
v.reset(OpRISCV64MOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpRISCV64MOVHUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVHUload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVHUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVHload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVHstore [off1] {sym} (ADDI [off2] base) val mem)
v.reset(OpRISCV64MOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
v.reset(OpRISCV64MOVWUload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWUload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVWUload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWload [off1] {sym} (ADDI [off2] base) mem)
v.reset(OpRISCV64MOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
return false
v.reset(OpRISCV64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDI [off2] base) val mem)
v.reset(OpRISCV64MOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpRISCV64MOVHconst, typ.UInt16)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpRISCV64MOVHconst, typ.UInt16)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr32)
v0 := b.NewValue0(v.Pos, OpLsh32x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpRISCV64MOVWconst, typ.UInt32)
v1.AuxInt = c & 31
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh32Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpRISCV64MOVWconst, typ.UInt32)
v3.AuxInt = -c & 31
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr64)
v0 := b.NewValue0(v.Pos, OpLsh64x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v1.AuxInt = c & 63
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh64Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v3.AuxInt = -c & 63
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpRISCV64MOVBconst, typ.UInt8)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpRISCV64MOVBconst, typ.UInt8)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg16, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg16, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg16, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg16, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v3.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg32, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg32, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg32, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg32, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v3.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64AND)
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v2.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRISCV64SRA)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v1.AuxInt = -1
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRISCV64SRA)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v1.AuxInt = -1
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRISCV64SRA)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v1.AuxInt = -1
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v2.AuxInt = 64
v2.AddArg(y)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRISCV64SRA)
v.Type = t
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v1.AuxInt = -1
v2 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v3.AddArg(y)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(y, v1)
+ v.AddArg2(x, v0)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg8, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg8, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg8, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpRISCV64SRL, t)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpNeg8, t)
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, t)
v3.AuxInt = 64
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v3.AuxInt = 64
v3.AddArg(y)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
v.Type = t
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpRISCV64OR, y.Type)
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpRISCV64ADDI, y.Type)
v2.AuxInt = -1
v3 := b.NewValue0(v.Pos, OpRISCV64SLTIU, y.Type)
v4.AddArg(y)
v3.AddArg(v4)
v2.AddArg(v3)
- v1.AddArg(v2)
- v.AddArg(v1)
+ v1.AddArg2(y, v2)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpRISCV64MOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpRISCV64MOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpRISCV64MOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpRISCV64MOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpRISCV64FMOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpRISCV64FMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
ptr := v_0
mem := v_1
v.reset(OpRISCV64MOVBstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVBconst, typ.UInt8)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [2] ptr mem)
ptr := v_0
mem := v_1
v.reset(OpRISCV64MOVHstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVHconst, typ.UInt16)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [4] ptr mem)
ptr := v_0
mem := v_1
v.reset(OpRISCV64MOVWstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVWconst, typ.UInt32)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [8] ptr mem)
ptr := v_0
mem := v_1
v.reset(OpRISCV64MOVDstore)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(ptr, v0, mem)
return true
}
// match: (Zero [s] {t} ptr mem)
mem := v_1
v.reset(OpRISCV64LoweredZero)
v.AuxInt = t.(*types.Type).Alignment()
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpRISCV64ADD, ptr.Type)
- v0.AddArg(ptr)
v1 := b.NewValue0(v.Pos, OpRISCV64MOVDconst, typ.UInt64)
v1.AuxInt = s - moveSize(t.(*types.Type).Alignment(), config)
- v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(ptr, v1)
+ v.AddArg3(ptr, v0, mem)
return true
}
}
val := v_1
mem := v_2
v.reset(OpS390XAddTupleFirst32)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpS390XLAA, types.NewTuple(typ.UInt32, types.TypeMem))
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(ptr, val, mem)
+ v.AddArg2(val, v0)
return true
}
}
val := v_1
mem := v_2
v.reset(OpS390XAddTupleFirst64)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpS390XLAAG, types.NewTuple(typ.UInt64, types.TypeMem))
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(ptr, val, mem)
+ v.AddArg2(val, v0)
return true
}
}
val := v_1
mem := v_2
v.reset(OpS390XLANfloor)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpS390XRLL, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpS390XORWconst, typ.UInt32)
v1.AuxInt = -1 << 8
v1.AddArg(val)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XRXSBG, typ.UInt32)
v2.Aux = s390x.NewRotateParams(59, 60, 3)
v3 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v3.AuxInt = 3 << 3
- v2.AddArg(v3)
- v2.AddArg(ptr)
- v0.AddArg(v2)
- v.AddArg(v0)
- v.AddArg(mem)
+ v2.AddArg2(v3, ptr)
+ v0.AddArg2(v1, v2)
+ v.AddArg3(ptr, v0, mem)
return true
}
}
val := v_1
mem := v_2
v.reset(OpS390XLAOfloor)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpS390XSLW, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt32)
v1.AddArg(val)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XRXSBG, typ.UInt32)
v2.Aux = s390x.NewRotateParams(59, 60, 3)
v3 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v3.AuxInt = 3 << 3
- v2.AddArg(v3)
- v2.AddArg(ptr)
- v0.AddArg(v2)
- v.AddArg(v0)
- v.AddArg(mem)
+ v2.AddArg2(v3, ptr)
+ v0.AddArg2(v1, v2)
+ v.AddArg3(ptr, v0, mem)
return true
}
}
mem := v_2
v.reset(OpS390XSYNC)
v0 := b.NewValue0(v.Pos, OpS390XMOVWatomicstore, types.TypeMem)
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, val, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpS390XSYNC)
v0 := b.NewValue0(v.Pos, OpS390XMOVDatomicstore, types.TypeMem)
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, val, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpS390XSYNC)
v0 := b.NewValue0(v.Pos, OpS390XMOVBatomicstore, types.TypeMem)
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, val, mem)
v.AddArg(v0)
return true
}
mem := v_2
v.reset(OpS390XSYNC)
v0 := b.NewValue0(v.Pos, OpS390XMOVDatomicstore, types.TypeMem)
- v0.AddArg(ptr)
- v0.AddArg(val)
- v0.AddArg(mem)
+ v0.AddArg3(ptr, val, mem)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpS390XSRDconst, t)
v0.AuxInt = 1
v1 := b.NewValue0(v.Pos, OpS390XSUB, t)
- v1.AddArg(x)
- v1.AddArg(y)
+ v1.AddArg2(x, y)
v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpS390XSUB)
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 64
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XFLOGR, typ.UInt64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSUB)
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 64
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XFLOGR, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpS390XMOVWZreg, typ.UInt64)
v3 := b.NewValue0(v.Pos, OpS390XANDW, t)
v4 := b.NewValue0(v.Pos, OpS390XSUBWconst, t)
v4.AuxInt = 1
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpS390XNOTW, t)
v5.AddArg(x)
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSUB)
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 64
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XFLOGR, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpS390XAND, t)
v3 := b.NewValue0(v.Pos, OpS390XSUBconst, t)
v3.AuxInt = 1
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XNOT, t)
v4.AddArg(x)
- v2.AddArg(v4)
+ v2.AddArg2(v3, v4)
v1.AddArg(v2)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XDIVW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XDIVWU)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XDIVW)
v0 := b.NewValue0(v.Pos, OpS390XMOVWreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpS390XDIVWU)
v0 := b.NewValue0(v.Pos, OpS390XMOVWZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpS390XDIVW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XDIVWU)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMPS, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Equal
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
z := v_2
v.reset(OpS390XFMADD)
- v.AddArg(z)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg3(z, x, y)
return true
}
}
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMPS, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Greater
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMPS, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Greater
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpS390XMULLD, typ.Int64)
v1 := b.NewValue0(v.Pos, OpS390XMOVWreg, typ.Int64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XMOVWreg, typ.Int64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpS390XMULLD, typ.Int64)
v1 := b.NewValue0(v.Pos, OpS390XMOVWZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XMOVWZreg, typ.UInt64)
v2.AddArg(y)
- v0.AddArg(v2)
+ v0.AddArg2(v1, v2)
v.AddArg(v0)
return true
}
mem := v_0.Args[1]
ptr := v_0.Args[0]
v.reset(OpS390XMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPU, types.TypeFlags)
- v2.AddArg(idx)
- v2.AddArg(len)
- v.AddArg(v2)
+ v2.AddArg2(idx, len)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPconst, types.TypeFlags)
v2.AuxInt = 0
v2.AddArg(p)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPU, types.TypeFlags)
- v2.AddArg(idx)
- v2.AddArg(len)
- v.AddArg(v2)
+ v2.AddArg2(idx, len)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMPS, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPU, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.LessOrEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMPS, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPU, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.Less
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XMOVWload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XMOVWZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XMOVHload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XMOVHZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XMOVBload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XMOVBZload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XFMOVSload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpS390XFMOVDload)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x16 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x32 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x64 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh16x8 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x16 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x32 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x64 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh32x8 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x16 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x32 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x64 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x8 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x16 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x32 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x64 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh8x8 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSLW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpS390XMODW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XMODWU)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XMODW)
v0 := b.NewValue0(v.Pos, OpS390XMOVWreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpS390XMODWU)
v0 := b.NewValue0(v.Pos, OpS390XMOVWZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.reset(OpS390XMODW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XMODWU)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(OpS390XMOVBstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZload, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(OpS390XMOVHstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZload, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(OpS390XMOVWstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVWZload, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] dst src mem)
src := v_1
mem := v_2
v.reset(OpS390XMOVDstore)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVDload, typ.UInt64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [16] dst src mem)
mem := v_2
v.reset(OpS390XMOVDstore)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVDload, typ.UInt64)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpS390XMOVDstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpS390XMOVDload, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [24] dst src mem)
mem := v_2
v.reset(OpS390XMOVDstore)
v.AuxInt = 16
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVDload, typ.UInt64)
v0.AuxInt = 16
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpS390XMOVDstore, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpS390XMOVDload, typ.UInt64)
v2.AuxInt = 8
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpS390XMOVDstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpS390XMOVDload, typ.UInt64)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpS390XMOVBstore)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZload, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpS390XMOVHstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpS390XMOVHZload, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [5] dst src mem)
mem := v_2
v.reset(OpS390XMOVBstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZload, typ.UInt8)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpS390XMOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpS390XMOVWZload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] dst src mem)
mem := v_2
v.reset(OpS390XMOVHstore)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZload, typ.UInt16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpS390XMOVWstore, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpS390XMOVWZload, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [7] dst src mem)
mem := v_2
v.reset(OpS390XMOVBstore)
v.AuxInt = 6
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZload, typ.UInt8)
v0.AuxInt = 6
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpS390XMOVHstore, types.TypeMem)
v1.AuxInt = 4
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpS390XMOVHZload, typ.UInt16)
v2.AuxInt = 4
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
+ v2.AddArg2(src, mem)
v3 := b.NewValue0(v.Pos, OpS390XMOVWstore, types.TypeMem)
- v3.AddArg(dst)
v4 := b.NewValue0(v.Pos, OpS390XMOVWZload, typ.UInt32)
- v4.AddArg(src)
- v4.AddArg(mem)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v4.AddArg2(src, mem)
+ v3.AddArg3(dst, v4, mem)
+ v1.AddArg3(dst, v2, v3)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpS390XMVC)
v.AuxInt = makeValAndOff(s, 0)
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpS390XMVC)
v.AuxInt = makeValAndOff(s-256, 256)
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XMVC, types.TypeMem)
v0.AuxInt = makeValAndOff(256, 0)
- v0.AddArg(dst)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(dst, src, mem)
+ v.AddArg3(dst, src, v0)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpS390XMVC)
v.AuxInt = makeValAndOff(s-512, 512)
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XMVC, types.TypeMem)
v0.AuxInt = makeValAndOff(256, 256)
- v0.AddArg(dst)
- v0.AddArg(src)
v1 := b.NewValue0(v.Pos, OpS390XMVC, types.TypeMem)
v1.AuxInt = makeValAndOff(256, 0)
- v1.AddArg(dst)
- v1.AddArg(src)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg3(dst, src, mem)
+ v0.AddArg3(dst, src, v1)
+ v.AddArg3(dst, src, v0)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpS390XMVC)
v.AuxInt = makeValAndOff(s-768, 768)
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XMVC, types.TypeMem)
v0.AuxInt = makeValAndOff(256, 512)
- v0.AddArg(dst)
- v0.AddArg(src)
v1 := b.NewValue0(v.Pos, OpS390XMVC, types.TypeMem)
v1.AuxInt = makeValAndOff(256, 256)
- v1.AddArg(dst)
- v1.AddArg(src)
v2 := b.NewValue0(v.Pos, OpS390XMVC, types.TypeMem)
v2.AuxInt = makeValAndOff(256, 0)
- v2.AddArg(dst)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v2.AddArg3(dst, src, mem)
+ v1.AddArg3(dst, src, v2)
+ v0.AddArg3(dst, src, v1)
+ v.AddArg3(dst, src, v0)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpS390XLoweredMove)
v.AuxInt = s % 256
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XADD, src.Type)
- v0.AddArg(src)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = (s / 256) * 256
- v0.AddArg(v1)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, v1)
+ v.AddArg4(dst, src, v0, mem)
return true
}
return false
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMPS, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XFCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
v3 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v4.AddArg(y)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v2.AddArg2(v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.Aux = s390x.NotEqual
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 1
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v2.AddArg(x)
- v2.AddArg(y)
- v.AddArg(v2)
+ v2.AddArg2(x, y)
+ v.AddArg3(v0, v1, v2)
return true
}
}
v.reset(OpS390XADD)
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = off
- v.AddArg(v0)
- v.AddArg(ptr)
+ v.AddArg2(v0, ptr)
return true
}
}
}
v.reset(OpS390XLoweredPanicBoundsA)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpS390XLoweredPanicBoundsB)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
// match: (PanicBounds [kind] x y mem)
}
v.reset(OpS390XLoweredPanicBoundsC)
v.AuxInt = kind
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(mem)
+ v.AddArg3(x, y, mem)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux16 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux32 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux64 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16Ux8 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x16 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x32 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x64 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh16x8 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVHreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux16 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux32 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux64 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32Ux8 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x16 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x32 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x64 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh32x8 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux16 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux32 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux64 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux8 <t> x y)
v.Type = t
v.Aux = s390x.GreaterOrEqual
v0 := b.NewValue0(v.Pos, OpS390XSRD, t)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
}
break
}
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x16 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x32 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x64 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v2.AuxInt = 64
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x8 x y)
x := v_0
y := v_1
v.reset(OpS390XSRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v0.Aux = s390x.GreaterOrEqual
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v2.AuxInt = 64
v3 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v3.AddArg(y)
v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux16 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux32 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux64 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8Ux8 <t> x y)
v0 := b.NewValue0(v.Pos, OpS390XSRW, t)
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(v1, y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v.AddArg(v3)
+ v.AddArg3(v0, v2, v3)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x16 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVHZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x32 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x64 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPUconst, types.TypeFlags)
v3.AuxInt = 64
v3.AddArg(y)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
// match: (Rsh8x8 x y)
v.reset(OpS390XSRAW)
v0 := b.NewValue0(v.Pos, OpS390XMOVBreg, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpS390XLOCGR, y.Type)
v1.Aux = s390x.GreaterOrEqual
- v1.AddArg(y)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, y.Type)
v2.AuxInt = 63
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XCMPWUconst, types.TypeFlags)
v3.AuxInt = 64
v4 := b.NewValue0(v.Pos, OpS390XMOVBZreg, typ.UInt64)
v4.AddArg(y)
v3.AddArg(v4)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v1.AddArg3(y, v2, v3)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpS390XMOVDaddridx)
v.AuxInt = c
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(idx)
+ v.AddArg2(ptr, idx)
return true
}
break
}
y := v_1.Args[0]
v.reset(OpS390XSUB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
break
}
v.reset(OpS390XADDC)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDE x y (FlagLT))
break
}
v.reset(OpS390XADDC)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDE x y (Select1 (ADDCconst [-1] (Select0 (ADDE (MOVDconst [0]) (MOVDconst [0]) c)))))
break
}
v.reset(OpS390XADDE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(c)
+ v.AddArg3(x, y, c)
return true
}
return false
}
y := v_1.Args[0]
v.reset(OpS390XSUBW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpS390XADDWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (ADDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XADDWload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpS390XMOVDaddridx)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (ADDconst [0] x)
break
}
v.reset(OpS390XADD)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpS390XLGDR, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (ADDload [off1] {sym} x (ADDconst [off2] ptr) mem)
v.reset(OpS390XADDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (ADDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XADDload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpS390XANDWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (ANDWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XANDWload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
break
}
v.reset(OpS390XAND)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpS390XLGDR, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (ANDload [off1] {sym} x (ADDconst [off2] ptr) mem)
v.reset(OpS390XANDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (ANDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XANDload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
}
v.reset(OpS390XInvertFlags)
v0 := b.NewValue0(v.Pos, OpS390XCMP, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
v.reset(OpS390XInvertFlags)
v0 := b.NewValue0(v.Pos, OpS390XCMPU, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
v.reset(OpS390XInvertFlags)
v0 := b.NewValue0(v.Pos, OpS390XCMPW, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
y := v_1.Args[0]
v.reset(OpS390XCMPW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPW x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XCMPW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPW (MOVWreg x) y)
x := v_0.Args[0]
y := v_1
v.reset(OpS390XCMPW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPW (MOVWZreg x) y)
x := v_0.Args[0]
y := v_1
v.reset(OpS390XCMPW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
}
v.reset(OpS390XInvertFlags)
v0 := b.NewValue0(v.Pos, OpS390XCMPWU, types.TypeFlags)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
}
y := v_1.Args[0]
v.reset(OpS390XCMPWU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWU x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XCMPWU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWU (MOVWreg x) y)
x := v_0.Args[0]
y := v_1
v.reset(OpS390XCMPWU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (CMPWU (MOVWZreg x) y)
x := v_0.Args[0]
y := v_1
v.reset(OpS390XCMPWU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
y := v_0.Args[0]
x := v_1
v.reset(OpS390XFMADD)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
y := v_0.Args[0]
x := v_1
v.reset(OpS390XFMADDS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
break
v.reset(OpS390XFMOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
v.reset(OpS390XFMOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (FMOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XFMOVDloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (FMOVDload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XFMOVDloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XFMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
v.reset(OpS390XFMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpS390XFMOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem)
v.reset(OpS390XFMOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (FMOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem)
v.reset(OpS390XFMOVDstoreidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem)
v.reset(OpS390XFMOVDstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XFMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
v.reset(OpS390XFMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
v.reset(OpS390XFMOVSload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
v.reset(OpS390XFMOVSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (FMOVSload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XFMOVSloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (FMOVSload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XFMOVSloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XFMOVSloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem)
v.reset(OpS390XFMOVSloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
return false
v.reset(OpS390XFMOVSstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem)
v.reset(OpS390XFMOVSstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (FMOVSstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem)
v.reset(OpS390XFMOVSstoreidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem)
v.reset(OpS390XFMOVSstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XFMOVSstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem)
v.reset(OpS390XFMOVSstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
return false
y := v_0.Args[0]
x := v_1
v.reset(OpS390XFMSUB)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
return false
y := v_0.Args[0]
x := v_1
v.reset(OpS390XFMSUBS)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(z)
+ v.AddArg3(x, y, z)
return true
}
return false
v2 := b.NewValue0(x.Pos, OpS390XMOVDload, t1)
v2.AuxInt = off
v2.Aux = sym
- v2.AddArg(ptr)
- v2.AddArg(mem)
+ v2.AddArg2(ptr, mem)
v1.AddArg(v2)
v0.AddArg(v1)
return true
cmp := v_2.Args[0]
v.reset(OpS390XLOCGR)
v.Aux = c.(s390x.CCMask).ReverseComparison()
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(cmp)
+ v.AddArg3(x, y, cmp)
return true
}
// match: (LOCGR {c} _ x (FlagEQ))
v.reset(OpS390XMOVBZload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
v.reset(OpS390XMOVBZload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBZload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVBZloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
// match: (MOVBZreg <t> x:(MOVBloadidx [o] {s} p i mem))
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(i)
- v0.AddArg(mem)
+ v0.AddArg3(p, i, mem)
return true
}
// match: (MOVBZreg x:(Arg <t>))
v.reset(OpS390XMOVBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
v.reset(OpS390XMOVBload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVBload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVBloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVBload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVBloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVBloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVBloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
// match: (MOVBreg <t> x:(MOVBZloadidx [o] {s} p i mem))
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(i)
- v0.AddArg(mem)
+ v0.AddArg3(p, i, mem)
return true
}
// match: (MOVBreg x:(Arg <t>))
v.reset(OpS390XMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVBZreg x) mem)
v.reset(OpS390XMOVBstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpS390XMOVBstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem)
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem)
v.reset(OpS390XMOVBstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVBstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem)
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVBstore [off] {sym} (ADD ptr idx) val mem)
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w0:(SRDconst [j] w) x:(MOVBstore [i-1] {s} p (SRDconst [j+8] w) mem))
v.reset(OpS390XMOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRWconst [8] w) mem))
v.reset(OpS390XMOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p w0:(SRWconst [j] w) x:(MOVBstore [i-1] {s} p (SRWconst [j+8] w) mem))
v.reset(OpS390XMOVHstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVBstore [i] {s} p (SRDconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
v.reset(OpS390XMOVHBRstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SRDconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRDconst [j-8] w) mem))
v.reset(OpS390XMOVHBRstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVBstore [i] {s} p (SRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem))
v.reset(OpS390XMOVHBRstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVBstore [i] {s} p (SRWconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRWconst [j-8] w) mem))
v.reset(OpS390XMOVHBRstore)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
return false
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem)
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem))
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = makeValAndOff(ValAndOff(c).Val()&0xff|ValAndOff(a).Val()<<8, ValAndOff(a).Off())
v.Aux = s
- v.AddArg(p)
- v.AddArg(mem)
+ v.AddArg2(p, mem)
return true
}
return false
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVBstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVHBRstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVHBRstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVHBRstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVHBRstoreidx)
v.AuxInt = i - 1
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVDaddridx)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (MOVDaddridx [c] {s} x (ADDconst [d] y))
v.reset(OpS390XMOVDaddridx)
v.AuxInt = c + d
v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y)
v.reset(OpS390XMOVDaddridx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y))
v.reset(OpS390XMOVDaddridx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpS390XMOVDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
v.reset(OpS390XMOVDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVDloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVDload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVDloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVDloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVDstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem)
v.reset(OpS390XMOVDstoreconst)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem)
v.reset(OpS390XMOVDstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem)
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVDstore [off] {sym} (ADD ptr idx) val mem)
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XSTMG2)
v.AuxInt = i - 8
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(mem)
+ v.AddArg4(p, w0, w1, mem)
return true
}
// match: (MOVDstore [i] {s} p w2 x:(STMG2 [i-16] {s} p w0 w1 mem))
v.reset(OpS390XSTMG3)
v.AuxInt = i - 16
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(w2)
- v.AddArg(mem)
+ v.AddArg5(p, w0, w1, w2, mem)
return true
}
// match: (MOVDstore [i] {s} p w3 x:(STMG3 [i-24] {s} p w0 w1 w2 mem))
v.reset(OpS390XSTMG4)
v.AuxInt = i - 24
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(w2)
- v.AddArg(w3)
- v.AddArg(mem)
+ v.AddArg6(p, w0, w1, w2, w3, mem)
return true
}
return false
v.reset(OpS390XMOVDstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVDstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem)
v.reset(OpS390XMOVDstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVWBRstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVHBRstore [i] {s} p (SRDconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRDconst [j-16] w) mem))
v.reset(OpS390XMOVWBRstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVHBRstore [i] {s} p (SRWconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem))
v.reset(OpS390XMOVWBRstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVHBRstore [i] {s} p (SRWconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRWconst [j-16] w) mem))
v.reset(OpS390XMOVWBRstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
return false
v.reset(OpS390XMOVWBRstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVWBRstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVWBRstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVWBRstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVHZload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
v.reset(OpS390XMOVHZload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVHZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHZload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVHZloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
// match: (MOVHZreg <t> x:(MOVHloadidx [o] {s} p i mem))
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(i)
- v0.AddArg(mem)
+ v0.AddArg3(p, i, mem)
return true
}
// match: (MOVHZreg x:(Arg <t>))
v.reset(OpS390XMOVHload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
v.reset(OpS390XMOVHload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVHload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVHloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVHload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVHloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVHloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVHloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
// match: (MOVHreg <t> x:(MOVHZloadidx [o] {s} p i mem))
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(i)
- v0.AddArg(mem)
+ v0.AddArg3(p, i, mem)
return true
}
// match: (MOVHreg x:(Arg <t>))
v.reset(OpS390XMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVHZreg x) mem)
v.reset(OpS390XMOVHstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpS390XMOVHstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem)
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = makeValAndOff(int64(int16(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem)
v.reset(OpS390XMOVHstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVHstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem)
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVHstore [off] {sym} (ADD ptr idx) val mem)
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVHstore [i] {s} p w0:(SRDconst [j] w) x:(MOVHstore [i-2] {s} p (SRDconst [j+16] w) mem))
v.reset(OpS390XMOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRWconst [16] w) mem))
v.reset(OpS390XMOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVHstore [i] {s} p w0:(SRWconst [j] w) x:(MOVHstore [i-2] {s} p (SRWconst [j+16] w) mem))
v.reset(OpS390XMOVWstore)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
return false
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem)
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVHstoreconst [c] {s} p x:(MOVHstoreconst [a] {s} p mem))
v.reset(OpS390XMOVWstore)
v.AuxInt = ValAndOff(a).Off()
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = int64(int32(ValAndOff(c).Val()&0xffff | ValAndOff(a).Val()<<16))
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
return false
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVHstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = i - 2
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVDBRstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVWBRstore [i] {s} p (SRDconst [j] w) x:(MOVWBRstore [i-4] {s} p w0:(SRDconst [j-32] w) mem))
v.reset(OpS390XMOVDBRstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
return false
v.reset(OpS390XMOVDBRstoreidx)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVDBRstoreidx)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.reset(OpS390XMOVWZload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
v.reset(OpS390XMOVWZload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWZload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVWZloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
// match: (MOVWZreg <t> x:(MOVWloadidx [o] {s} p i mem))
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(i)
- v0.AddArg(mem)
+ v0.AddArg3(p, i, mem)
return true
}
// match: (MOVWZreg x:(Arg <t>))
v.reset(OpS390XMOVWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem)
v.reset(OpS390XMOVWload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(mem)
+ v.AddArg2(base, mem)
return true
}
// match: (MOVWload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem)
v.reset(OpS390XMOVWloadidx)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
// match: (MOVWload [off] {sym} (ADD ptr idx) mem)
v.reset(OpS390XMOVWloadidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVWloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.reset(OpS390XMOVWloadidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(mem)
+ v.AddArg3(ptr, idx, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
// match: (MOVWreg <t> x:(MOVWZloadidx [o] {s} p i mem))
v.AddArg(v0)
v0.AuxInt = o
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(i)
- v0.AddArg(mem)
+ v0.AddArg3(p, i, mem)
return true
}
// match: (MOVWreg x:(Arg <t>))
v.reset(OpS390XMOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVWZreg x) mem)
v.reset(OpS390XMOVWstore)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(ptr, x, mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem)
v.reset(OpS390XMOVWstore)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem)
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem)
v.reset(OpS390XMOVWstore)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(base)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(base, val, mem)
return true
}
// match: (MOVWstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem)
}
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = off1 + off2
- v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.Aux = mergeSym(sym1, sym2)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
// match: (MOVWstore [off] {sym} (ADD ptr idx) val mem)
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = off
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVDstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg3(p, w, mem)
return true
}
// match: (MOVWstore [i] {s} p w0:(SRDconst [j] w) x:(MOVWstore [i-4] {s} p (SRDconst [j+32] w) mem))
v.reset(OpS390XMOVDstore)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg3(p, w0, mem)
return true
}
// match: (MOVWstore [i] {s} p w1 x:(MOVWstore [i-4] {s} p w0 mem))
v.reset(OpS390XSTM2)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(mem)
+ v.AddArg4(p, w0, w1, mem)
return true
}
// match: (MOVWstore [i] {s} p w2 x:(STM2 [i-8] {s} p w0 w1 mem))
v.reset(OpS390XSTM3)
v.AuxInt = i - 8
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(w2)
- v.AddArg(mem)
+ v.AddArg5(p, w0, w1, w2, mem)
return true
}
// match: (MOVWstore [i] {s} p w3 x:(STM3 [i-12] {s} p w0 w1 w2 mem))
v.reset(OpS390XSTM4)
v.AuxInt = i - 12
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(w2)
- v.AddArg(w3)
- v.AddArg(mem)
+ v.AddArg6(p, w0, w1, w2, w3, mem)
return true
}
return false
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = s
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem)
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = ValAndOff(sc).add(off)
v.Aux = mergeSym(sym1, sym2)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem))
v.reset(OpS390XMOVDstore)
v.AuxInt = ValAndOff(a).Off()
v.Aux = s
- v.AddArg(p)
v0 := b.NewValue0(x.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = ValAndOff(c).Val()&0xffffffff | ValAndOff(a).Val()<<32
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(p, v0, mem)
return true
}
return false
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVWstoreidx)
v.AuxInt = c + d
v.Aux = sym
- v.AddArg(ptr)
- v.AddArg(idx)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg4(ptr, idx, val, mem)
return true
}
break
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w, mem)
return true
}
}
v.reset(OpS390XMOVDstoreidx)
v.AuxInt = i - 4
v.Aux = s
- v.AddArg(p)
- v.AddArg(idx)
- v.AddArg(w0)
- v.AddArg(mem)
+ v.AddArg4(p, idx, w0, mem)
return true
}
}
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v0 := b.NewValue0(v.Pos, OpS390XSLDconst, v.Type)
v0.AuxInt = log2(c + 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLDconst [c] x)
v0 := b.NewValue0(v.Pos, OpS390XSLDconst, v.Type)
v0.AuxInt = log2(c - 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLDconst [c] (MOVDconst [d]))
break
}
v.reset(OpS390XMULLD)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpS390XLGDR, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (MULLDload [off1] {sym} x (ADDconst [off2] ptr) mem)
v.reset(OpS390XMULLDload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (MULLDload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XMULLDload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v0 := b.NewValue0(v.Pos, OpS390XSLWconst, v.Type)
v0.AuxInt = log2(c + 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLWconst [c] x)
v0 := b.NewValue0(v.Pos, OpS390XSLWconst, v.Type)
v0.AuxInt = log2(c - 1)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (MULLWconst [c] (MOVDconst [d]))
v.reset(OpS390XMULLWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (MULLWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XMULLWload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpS390XXOR)
v0 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v0.AuxInt = -1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
y := v_1_0.Args[0]
v.reset(OpS390XLGDR)
v0 := b.NewValue0(v.Pos, OpS390XCPSDR, t)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpS390XCPSDR, x.Type)
v1 := b.NewValue0(v.Pos, OpS390XFMOVDconst, x.Type)
v1.AuxInt = c
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
y := v_1_0.Args[0]
v.reset(OpS390XLGDR)
v0 := b.NewValue0(v.Pos, OpS390XCPSDR, t)
- v0.AddArg(y)
- v0.AddArg(x)
+ v0.AddArg2(y, x)
v.AddArg(v0)
return true
}
v0 := b.NewValue0(v.Pos, OpS390XCPSDR, x.Type)
v1 := b.NewValue0(v.Pos, OpS390XFMOVDconst, x.Type)
v1.AuxInt = c
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v2 := b.NewValue0(x1.Pos, OpS390XMOVHZload, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(mem)
+ v2.AddArg2(p, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v2 := b.NewValue0(x1.Pos, OpS390XMOVWZload, typ.UInt32)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(mem)
+ v2.AddArg2(p, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v2 := b.NewValue0(v.Pos, OpS390XMOVHZloadidx, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(idx)
- v2.AddArg(mem)
+ v2.AddArg3(p, idx, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v2 := b.NewValue0(v.Pos, OpS390XMOVWZloadidx, typ.UInt32)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(idx)
- v2.AddArg(mem)
+ v2.AddArg3(p, idx, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(x1.Pos, OpS390XMOVHBRload, typ.UInt16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(x1.Pos, OpS390XMOVWBRload, typ.UInt32)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v3 := b.NewValue0(x0.Pos, OpS390XMOVHBRload, typ.UInt16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(mem)
+ v3.AddArg2(p, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v3 := b.NewValue0(x0.Pos, OpS390XMOVWBRload, typ.UInt32)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(mem)
+ v3.AddArg2(p, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(v.Pos, OpS390XMOVHBRloadidx, typ.Int16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v1 := b.NewValue0(v.Pos, OpS390XMOVWBRloadidx, typ.Int32)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v3 := b.NewValue0(v.Pos, OpS390XMOVHBRloadidx, typ.Int16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(idx)
- v3.AddArg(mem)
+ v3.AddArg3(p, idx, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v3 := b.NewValue0(v.Pos, OpS390XMOVWBRloadidx, typ.Int32)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(idx)
- v3.AddArg(mem)
+ v3.AddArg3(p, idx, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v2 := b.NewValue0(x1.Pos, OpS390XMOVHZload, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(mem)
+ v2.AddArg2(p, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v2 := b.NewValue0(v.Pos, OpS390XMOVHZloadidx, typ.UInt16)
v2.AuxInt = i0
v2.Aux = s
- v2.AddArg(p)
- v2.AddArg(idx)
- v2.AddArg(mem)
+ v2.AddArg3(p, idx, mem)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(x1.Pos, OpS390XMOVHBRload, typ.UInt16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(mem)
+ v1.AddArg2(p, mem)
v0.AddArg(v1)
return true
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(mem)
+ v0.AddArg2(p, mem)
return true
}
break
v3 := b.NewValue0(x0.Pos, OpS390XMOVHBRload, typ.UInt16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(mem)
+ v3.AddArg2(p, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v1 := b.NewValue0(v.Pos, OpS390XMOVHBRloadidx, typ.Int16)
v1.AuxInt = i0
v1.Aux = s
- v1.AddArg(p)
- v1.AddArg(idx)
- v1.AddArg(mem)
+ v1.AddArg3(p, idx, mem)
v0.AddArg(v1)
return true
}
v.AddArg(v0)
v0.AuxInt = i0
v0.Aux = s
- v0.AddArg(p)
- v0.AddArg(idx)
- v0.AddArg(mem)
+ v0.AddArg3(p, idx, mem)
return true
}
}
v3 := b.NewValue0(v.Pos, OpS390XMOVHBRloadidx, typ.Int16)
v3.AuxInt = i0
v3.Aux = s
- v3.AddArg(p)
- v3.AddArg(idx)
- v3.AddArg(mem)
+ v3.AddArg3(p, idx, mem)
v2.AddArg(v3)
v1.AddArg(v2)
- v0.AddArg(v1)
- v0.AddArg(y)
+ v0.AddArg2(v1, y)
return true
}
}
v.reset(OpS390XORWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (ORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XORWload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
break
}
v.reset(OpS390XOR)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpS390XLGDR, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (ORload [off1] {sym} x (ADDconst [off2] ptr) mem)
v.reset(OpS390XORload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (ORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XORload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
c := v_1_0.AuxInt
y := v_1_1
v.reset(OpS390XSLD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XANDWconst, typ.UInt32)
v0.AuxInt = c & 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
break
}
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLD x (MOVWreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLD x (MOVHreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLD x (MOVBreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLD x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLD x (MOVHZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLD x (MOVBZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_1_0.AuxInt
y := v_1_1
v.reset(OpS390XSLW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XANDWconst, typ.UInt32)
v0.AuxInt = c & 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
break
}
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLW x (MOVWreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLW x (MOVHreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLW x (MOVBreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLW x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLW x (MOVHZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SLW x (MOVBZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSLW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_1_0.AuxInt
y := v_1_1
v.reset(OpS390XSRAD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XANDWconst, typ.UInt32)
v0.AuxInt = c & 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
break
}
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAD x (MOVWreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAD x (MOVHreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAD x (MOVBreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAD x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAD x (MOVHZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAD x (MOVBZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_1_0.AuxInt
y := v_1_1
v.reset(OpS390XSRAW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XANDWconst, typ.UInt32)
v0.AuxInt = c & 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
break
}
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAW x (MOVWreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAW x (MOVHreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAW x (MOVBreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAW x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAW x (MOVHZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRAW x (MOVBZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRAW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_1_0.AuxInt
y := v_1_1
v.reset(OpS390XSRD)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XANDWconst, typ.UInt32)
v0.AuxInt = c & 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
break
}
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRD x (MOVWreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRD x (MOVHreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRD x (MOVBreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRD x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRD x (MOVHZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRD x (MOVBZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRD)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
c := v_1_0.AuxInt
y := v_1_1
v.reset(OpS390XSRW)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpS390XANDWconst, typ.UInt32)
v0.AuxInt = c & 63
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
break
break
}
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRW x (MOVWreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRW x (MOVHreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRW x (MOVBreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRW x (MOVWZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRW x (MOVHZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SRW x (MOVBZreg y))
}
y := v_1.Args[0]
v.reset(OpS390XSRW)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
return false
v.reset(OpS390XSTM4)
v.AuxInt = i - 8
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(w2)
- v.AddArg(w3)
- v.AddArg(mem)
+ v.AddArg6(p, w0, w1, w2, w3, mem)
return true
}
// match: (STM2 [i] {s} p (SRDconst [32] x) x mem)
v.reset(OpS390XMOVDstore)
v.AuxInt = i
v.Aux = s
- v.AddArg(p)
- v.AddArg(x)
- v.AddArg(mem)
+ v.AddArg3(p, x, mem)
return true
}
return false
v.reset(OpS390XSTMG4)
v.AuxInt = i - 16
v.Aux = s
- v.AddArg(p)
- v.AddArg(w0)
- v.AddArg(w1)
- v.AddArg(w2)
- v.AddArg(w3)
- v.AddArg(mem)
+ v.AddArg6(p, w0, w1, w2, w3, mem)
return true
}
return false
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
break
}
v.reset(OpS390XSUBC)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBE x y (FlagOV))
break
}
v.reset(OpS390XSUBC)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (SUBE x y (Select1 (SUBC (MOVDconst [0]) (NEG (Select0 (SUBE (MOVDconst [0]) (MOVDconst [0]) c))))))
break
}
v.reset(OpS390XSUBE)
- v.AddArg(x)
- v.AddArg(y)
- v.AddArg(c)
+ v.AddArg3(x, y, c)
return true
}
return false
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (SUBW <t> x g:(MOVWZload [off] {sym} ptr mem))
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpS390XSUBWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (SUBWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XSUBWload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
break
}
v.reset(OpS390XSUB)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpS390XLGDR, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (SUBload [off1] {sym} x (ADDconst [off2] ptr) mem)
v.reset(OpS390XSUBload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (SUBload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XSUBload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpS390XSRWconst, typ.UInt8)
v0.AuxInt = 8
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v1 := b.NewValue0(v.Pos, OpS390XSRWconst, typ.UInt16)
v1.AuxInt = 16
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpS390XSRDconst, typ.UInt32)
v1.AuxInt = 32
v1.AddArg(x)
- v0.AddArg(v1)
- v0.AddArg(x)
+ v0.AddArg2(v1, x)
v.AddArg(v0)
return true
}
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.Type = t
v.AuxInt = off
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
break
v.reset(OpS390XXORWload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (XORWload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XXORWload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
break
}
v.reset(OpS390XXOR)
- v.AddArg(x)
v0 := b.NewValue0(v_2.Pos, OpS390XLGDR, t)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (XORload [off1] {sym} x (ADDconst [off2] ptr) mem)
v.reset(OpS390XXORload)
v.AuxInt = off1 + off2
v.Aux = sym
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
// match: (XORload [o1] {s1} x (MOVDaddr [o2] {s2} ptr) mem)
v.reset(OpS390XXORload)
v.AuxInt = o1 + o2
v.Aux = mergeSym(s1, s2)
- v.AddArg(x)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg3(x, ptr, mem)
return true
}
return false
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpS390XADDE, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpS390XADDCconst, types.NewTuple(typ.UInt64, types.TypeFlags))
v2.AuxInt = -1
v2.AddArg(c)
v1.AddArg(v2)
- v0.AddArg(v1)
+ v0.AddArg3(x, y, v1)
v.AddArg(v0)
return true
}
v.reset(OpSelect0)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpS390XSUBE, types.NewTuple(typ.UInt64, types.TypeFlags))
- v0.AddArg(x)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v2 := b.NewValue0(v.Pos, OpS390XSUBC, types.NewTuple(typ.UInt64, types.TypeFlags))
v3 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v3.AuxInt = 0
- v2.AddArg(v3)
- v2.AddArg(c)
+ v2.AddArg2(v3, c)
v1.AddArg(v2)
- v0.AddArg(v1)
+ v0.AddArg3(x, y, v1)
v.AddArg(v0)
return true
}
tuple := v_0.Args[1]
val := v_0.Args[0]
v.reset(OpS390XADDW)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpSelect0, t)
v0.AddArg(tuple)
- v.AddArg(v0)
+ v.AddArg2(val, v0)
return true
}
// match: (Select0 <t> (AddTupleFirst64 val tuple))
tuple := v_0.Args[1]
val := v_0.Args[0]
v.reset(OpS390XADD)
- v.AddArg(val)
v0 := b.NewValue0(v.Pos, OpSelect0, t)
v0.AddArg(tuple)
- v.AddArg(v0)
+ v.AddArg2(val, v0)
return true
}
// match: (Select0 (ADDCconst (MOVDconst [c]) [d]))
v0 := b.NewValue0(v.Pos, OpS390XADDE, types.NewTuple(typ.UInt64, types.TypeFlags))
v1 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v1.AuxInt = 0
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpS390XADDE, types.NewTuple(typ.UInt64, types.TypeFlags))
- v4.AddArg(x)
- v4.AddArg(y)
v5 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v6 := b.NewValue0(v.Pos, OpS390XADDCconst, types.NewTuple(typ.UInt64, types.TypeFlags))
v6.AuxInt = -1
v6.AddArg(c)
v5.AddArg(v6)
- v4.AddArg(v5)
+ v4.AddArg3(x, y, v5)
v3.AddArg(v4)
- v0.AddArg(v3)
+ v0.AddArg3(v1, v2, v3)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpS390XSUBE, types.NewTuple(typ.UInt64, types.TypeFlags))
v2 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v3.AuxInt = 0
- v1.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v5 := b.NewValue0(v.Pos, OpS390XSUBE, types.NewTuple(typ.UInt64, types.TypeFlags))
- v5.AddArg(x)
- v5.AddArg(y)
v6 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v7 := b.NewValue0(v.Pos, OpS390XSUBC, types.NewTuple(typ.UInt64, types.TypeFlags))
v8 := b.NewValue0(v.Pos, OpS390XMOVDconst, typ.UInt64)
v8.AuxInt = 0
- v7.AddArg(v8)
- v7.AddArg(c)
+ v7.AddArg2(v8, c)
v6.AddArg(v7)
- v5.AddArg(v6)
+ v5.AddArg3(x, y, v6)
v4.AddArg(v5)
- v1.AddArg(v4)
+ v1.AddArg3(v2, v3, v4)
v0.AddArg(v1)
v.AddArg(v0)
return true
break
}
v.reset(OpS390XFMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpS390XFMOVSstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpS390XMOVDstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpS390XMOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpS390XMOVHstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpS390XMOVBstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
mem := v_1
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [2] destptr mem)
mem := v_1
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [4] destptr mem)
mem := v_1
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [8] destptr mem)
mem := v_1
v.reset(OpS390XMOVDstoreconst)
v.AuxInt = 0
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [3] destptr mem)
mem := v_1
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = makeValAndOff(0, 2)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpS390XMOVHstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [5] destptr mem)
mem := v_1
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpS390XMOVWstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [6] destptr mem)
mem := v_1
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = makeValAndOff(0, 4)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpS390XMOVWstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [7] destptr mem)
mem := v_1
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = makeValAndOff(0, 3)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpS390XMOVWstoreconst, types.TypeMem)
v0.AuxInt = 0
- v0.AddArg(destptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(destptr, mem)
+ v.AddArg2(destptr, v0)
return true
}
// match: (Zero [s] destptr mem)
}
v.reset(OpS390XCLEAR)
v.AuxInt = makeValAndOff(s, 0)
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
// match: (Zero [s] destptr mem)
}
v.reset(OpS390XLoweredZero)
v.AuxInt = s % 256
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpS390XADDconst, destptr.Type)
v0.AuxInt = (s / 256) * 256
v0.AddArg(destptr)
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
return false
v.reset(OpWasmI64Sub)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 64
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Clz, typ.Int64)
v1.AddArg(x)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64Xor)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = -1
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64Xor)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = -1
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64Xor)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = -1
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64Xor)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = -1
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
x := v_0
v.reset(OpWasmI64Ctz)
v0 := b.NewValue0(v.Pos, OpWasmI64Or, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 0x10000
- v0.AddArg(v1)
+ v0.AddArg2(x, v1)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpWasmI64Ctz)
v0 := b.NewValue0(v.Pos, OpWasmI64Or, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 0x100000000
- v0.AddArg(v1)
+ v0.AddArg2(x, v1)
v.AddArg(v0)
return true
}
x := v_0
v.reset(OpWasmI64Ctz)
v0 := b.NewValue0(v.Pos, OpWasmI64Or, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 0x100
- v0.AddArg(v1)
+ v0.AddArg2(x, v1)
v.AddArg(v0)
return true
}
v.reset(OpWasmI64DivS)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64DivU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64DivS)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64DivU)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64DivS)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64DivU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64Eq)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64Eq)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64Eq)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LeS)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LeU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LeS)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LeU)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LeS)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LeU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LtS)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LtU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LtS)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LtU)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LtS)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64LtU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
break
}
v.reset(OpWasmF32Load)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmF64Load)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load32U)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load32S)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load16U)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load16S)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load8U)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (Load <t> ptr mem)
break
}
v.reset(OpWasmI64Load8S)
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpWasmI64Shl)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Lsh64x64 x (I64Const [c]))
break
}
v.reset(OpWasmI64Shl)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = c
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh64x64 x (I64Const [c]))
y := v_1
v.reset(OpWasmSelect)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v3.AuxInt = 64
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(y, v3)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpLsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
v.reset(OpWasmI64RemS)
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64RemU)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64RemS)
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64RemU)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64RemS)
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64RemU)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
src := v_1
mem := v_2
v.reset(OpWasmI64Store8)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load8U, typ.UInt8)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [2] dst src mem)
src := v_1
mem := v_2
v.reset(OpWasmI64Store16)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load16U, typ.UInt16)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [4] dst src mem)
src := v_1
mem := v_2
v.reset(OpWasmI64Store32)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load32U, typ.UInt32)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [8] dst src mem)
src := v_1
mem := v_2
v.reset(OpWasmI64Store)
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
- v.AddArg(mem)
+ v0.AddArg2(src, mem)
+ v.AddArg3(dst, v0, mem)
return true
}
// match: (Move [16] dst src mem)
mem := v_2
v.reset(OpWasmI64Store)
v.AuxInt = 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
v0.AuxInt = 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [3] dst src mem)
mem := v_2
v.reset(OpWasmI64Store8)
v.AuxInt = 2
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load8U, typ.UInt8)
v0.AuxInt = 2
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpWasmI64Store16, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpWasmI64Load16U, typ.UInt16)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [5] dst src mem)
mem := v_2
v.reset(OpWasmI64Store8)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load8U, typ.UInt8)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpWasmI64Store32, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpWasmI64Load32U, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [6] dst src mem)
mem := v_2
v.reset(OpWasmI64Store16)
v.AuxInt = 4
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load16U, typ.UInt16)
v0.AuxInt = 4
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpWasmI64Store32, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpWasmI64Load32U, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [7] dst src mem)
mem := v_2
v.reset(OpWasmI64Store32)
v.AuxInt = 3
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load32U, typ.UInt32)
v0.AuxInt = 3
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpWasmI64Store32, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpWasmI64Load32U, typ.UInt32)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpWasmI64Store)
v.AuxInt = s - 8
- v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
v0.AuxInt = s - 8
- v0.AddArg(src)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(src, mem)
v1 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v1.AddArg(dst)
v2 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
- v2.AddArg(src)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v2.AddArg2(src, mem)
+ v1.AddArg3(dst, v2, mem)
+ v.AddArg3(dst, v0, v1)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = s % 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = s % 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
- v3.AddArg(src)
- v3.AddArg(mem)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v3.AddArg2(src, mem)
+ v2.AddArg3(dst, v3, mem)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
v0.AuxInt = s % 16
v0.AddArg(dst)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
v1.AuxInt = s % 16
v1.AddArg(src)
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
v2.AuxInt = 8
- v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
v3.AuxInt = 8
- v3.AddArg(src)
- v3.AddArg(mem)
- v2.AddArg(v3)
+ v3.AddArg2(src, mem)
v4 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpWasmI64Load, typ.UInt64)
- v5.AddArg(src)
- v5.AddArg(mem)
- v4.AddArg(v5)
- v4.AddArg(mem)
- v2.AddArg(v4)
- v.AddArg(v2)
+ v5.AddArg2(src, mem)
+ v4.AddArg3(dst, v5, mem)
+ v2.AddArg3(dst, v3, v4)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Move [s] dst src mem)
}
v.reset(OpWasmLoweredMove)
v.AuxInt = s / 8
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
return false
v.reset(OpWasmI64Sub)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpWasmI64Sub)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpWasmI64Sub)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpWasmI64Sub)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpWasmI64Ne)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64Ne)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpWasmI64Ne)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
c := v_1.AuxInt
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = c & 15
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v3.AuxInt = -c & 15
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
c := v_1.AuxInt
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = c & 7
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v3.AuxInt = -c & 7
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(x, v3)
+ v.AddArg2(v0, v2)
return true
}
return false
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_1
v.reset(OpRsh64Ux64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRsh64Ux64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpWasmI64ShrU)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64Ux64 x (I64Const [c]))
break
}
v.reset(OpWasmI64ShrU)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = c
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux64 x (I64Const [c]))
y := v_1
v.reset(OpWasmSelect)
v0 := b.NewValue0(v.Pos, OpWasmI64ShrU, typ.Int64)
- v0.AddArg(x)
- v0.AddArg(y)
- v.AddArg(v0)
+ v0.AddArg2(x, y)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v3.AuxInt = 64
- v2.AddArg(v3)
- v.AddArg(v2)
+ v2.AddArg2(y, v3)
+ v.AddArg3(v0, v1, v2)
return true
}
}
y := v_1
v.reset(OpRsh64Ux64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
break
}
v.reset(OpWasmI64ShrS)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Rsh64x64 x (I64Const [c]))
break
}
v.reset(OpWasmI64ShrS)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = c
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x64 x (I64Const [c]))
break
}
v.reset(OpWasmI64ShrS)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 63
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x64 x y)
x := v_0
y := v_1
v.reset(OpWasmI64ShrS)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmSelect, typ.Int64)
- v0.AddArg(y)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 63
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpWasmI64LtU, typ.Bool)
- v2.AddArg(y)
v3 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v3.AuxInt = 64
- v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v2.AddArg2(y, v3)
+ v0.AddArg3(y, v1, v2)
+ v.AddArg2(x, v0)
return true
}
}
y := v_1
v.reset(OpRsh64x64)
v.AuxInt = c
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(y)
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(y)
+ v.AddArg2(v0, y)
return true
}
}
v.AuxInt = c
v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
x := v_0
v.reset(OpWasmI64ShrS)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 48
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 48
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
x := v_0
v.reset(OpWasmI64ShrS)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 48
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 48
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
x := v_0
v.reset(OpWasmI64ShrS)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 32
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 32
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
x := v_0
v.reset(OpWasmI64ShrS)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 56
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 56
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
x := v_0
v.reset(OpWasmI64ShrS)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 56
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 56
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
x := v_0
v.reset(OpWasmI64ShrS)
v0 := b.NewValue0(v.Pos, OpWasmI64Shl, typ.Int64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 56
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 56
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpWasmI64Sub, typ.Int64)
v1 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v1.AuxInt = 0
- v0.AddArg(v1)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(v1, x)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 63
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
break
}
v.reset(OpWasmF64Store)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpWasmF32Store)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpWasmI64Store)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpWasmI64Store32)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpWasmI64Store16)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
// match: (Store {t} ptr val mem)
break
}
v.reset(OpWasmI64Store8)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
x := v_0.AuxInt
y := v_1
v.reset(OpWasmF64Add)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmF64Const, typ.Float64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
return false
x := v_0.AuxInt
y := v_1
v.reset(OpWasmF64Mul)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmF64Const, typ.Float64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
return false
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64Add)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
// match: (I64Add x (I64Const [y]))
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64And)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
return false
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64Eq)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
// match: (I64Eq x (I64Const [0]))
}
v.reset(OpWasmI64Load)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (I64Load [off] (LoweredAddr {sym} [off2] (SB)) _)
}
v.reset(OpWasmI64Load16S)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpWasmI64Load16U)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (I64Load16U [off] (LoweredAddr {sym} [off2] (SB)) _)
}
v.reset(OpWasmI64Load32S)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpWasmI64Load32U)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (I64Load32U [off] (LoweredAddr {sym} [off2] (SB)) _)
}
v.reset(OpWasmI64Load8S)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
return false
}
v.reset(OpWasmI64Load8U)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(mem)
+ v.AddArg2(ptr, mem)
return true
}
// match: (I64Load8U [off] (LoweredAddr {sym} [off2] (SB)) _)
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64Mul)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
return false
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64Ne)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
// match: (I64Ne x (I64Const [0]))
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64Or)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
return false
}
v.reset(OpWasmI64Store)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
}
v.reset(OpWasmI64Store16)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
}
v.reset(OpWasmI64Store32)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
}
v.reset(OpWasmI64Store8)
v.AuxInt = off + off2
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
+ v.AddArg3(ptr, val, mem)
return true
}
return false
x := v_0.AuxInt
y := v_1
v.reset(OpWasmI64Xor)
- v.AddArg(y)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = x
- v.AddArg(v0)
+ v.AddArg2(y, v0)
return true
}
return false
destptr := v_0
mem := v_1
v.reset(OpWasmI64Store8)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [2] destptr mem)
destptr := v_0
mem := v_1
v.reset(OpWasmI64Store16)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [4] destptr mem)
destptr := v_0
mem := v_1
v.reset(OpWasmI64Store32)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [8] destptr mem)
destptr := v_0
mem := v_1
v.reset(OpWasmI64Store)
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(mem)
+ v.AddArg3(destptr, v0, mem)
return true
}
// match: (Zero [3] destptr mem)
mem := v_1
v.reset(OpWasmI64Store8)
v.AuxInt = 2
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store16, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [5] destptr mem)
mem := v_1
v.reset(OpWasmI64Store8)
v.AuxInt = 4
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store32, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [6] destptr mem)
mem := v_1
v.reset(OpWasmI64Store16)
v.AuxInt = 4
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store32, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [7] destptr mem)
mem := v_1
v.reset(OpWasmI64Store32)
v.AuxInt = 3
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store32, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [s] destptr mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = s % 8
v0.AddArg(destptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Zero [16] destptr mem)
mem := v_1
v.reset(OpWasmI64Store)
v.AuxInt = 8
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(destptr, v2, mem)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [24] destptr mem)
mem := v_1
v.reset(OpWasmI64Store)
v.AuxInt = 16
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
v1.AuxInt = 8
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v3.AddArg(destptr)
v4 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v4.AuxInt = 0
- v3.AddArg(v4)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(destptr, v4, mem)
+ v1.AddArg3(destptr, v2, v3)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [32] destptr mem)
mem := v_1
v.reset(OpWasmI64Store)
v.AuxInt = 24
- v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
v1.AuxInt = 16
- v1.AddArg(destptr)
v2 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v2.AuxInt = 0
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
v3.AuxInt = 8
- v3.AddArg(destptr)
v4 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v4.AuxInt = 0
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpWasmI64Store, types.TypeMem)
- v5.AddArg(destptr)
v6 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v6.AuxInt = 0
- v5.AddArg(v6)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(destptr, v6, mem)
+ v3.AddArg3(destptr, v4, v5)
+ v1.AddArg3(destptr, v2, v3)
+ v.AddArg3(destptr, v0, v1)
return true
}
// match: (Zero [s] destptr mem)
}
v.reset(OpWasmLoweredZero)
v.AuxInt = s / 8
- v.AddArg(destptr)
- v.AddArg(mem)
+ v.AddArg2(destptr, mem)
return true
}
return false
for {
x := v_0
v.reset(OpWasmI64And)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0xffff
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64And)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0xffff
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64And)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0xffffffff
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64And)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0xff
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64And)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0xff
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
for {
x := v_0
v.reset(OpWasmI64And)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpWasmI64Const, typ.Int64)
v0.AuxInt = 0xff
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
}
}
v.reset(OpComplexMake)
v0 := b.NewValue0(v.Pos, OpLoad, typ.Float32)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.Float32)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.Float32Ptr)
v2.AuxInt = 4
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpComplexMake)
v0 := b.NewValue0(v.Pos, OpLoad, typ.Float64)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.Float64)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.Float64Ptr)
v2.AuxInt = 8
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpStringMake)
v0 := b.NewValue0(v.Pos, OpLoad, typ.BytePtr)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.Int)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.IntPtr)
v2.AuxInt = config.PtrSize
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpSliceMake)
v0 := b.NewValue0(v.Pos, OpLoad, t.Elem().PtrTo())
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.Int)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.IntPtr)
v2.AuxInt = config.PtrSize
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
v3 := b.NewValue0(v.Pos, OpLoad, typ.Int)
v4 := b.NewValue0(v.Pos, OpOffPtr, typ.IntPtr)
v4.AuxInt = 2 * config.PtrSize
v4.AddArg(ptr)
- v3.AddArg(v4)
- v3.AddArg(mem)
- v.AddArg(v3)
+ v3.AddArg2(v4, mem)
+ v.AddArg3(v0, v1, v3)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpIMake)
v0 := b.NewValue0(v.Pos, OpLoad, typ.Uintptr)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.BytePtr)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.BytePtrPtr)
v2.AuxInt = config.PtrSize
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
+ v.AddArg2(v0, v1)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpOffPtr, typ.Float32Ptr)
v0.AuxInt = 4
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(imag)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typ.Float32
- v1.AddArg(dst)
- v1.AddArg(real)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, real, mem)
+ v.AddArg3(v0, imag, v1)
return true
}
// match: (Store {t} dst (ComplexMake real imag) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, typ.Float64Ptr)
v0.AuxInt = 8
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(imag)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typ.Float64
- v1.AddArg(dst)
- v1.AddArg(real)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, real, mem)
+ v.AddArg3(v0, imag, v1)
return true
}
// match: (Store dst (StringMake ptr len) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, typ.IntPtr)
v0.AuxInt = config.PtrSize
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(len)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typ.BytePtr
- v1.AddArg(dst)
- v1.AddArg(ptr)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, ptr, mem)
+ v.AddArg3(v0, len, v1)
return true
}
// match: (Store dst (SliceMake ptr len cap) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, typ.IntPtr)
v0.AuxInt = 2 * config.PtrSize
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(cap)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typ.Int
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.IntPtr)
v2.AuxInt = config.PtrSize
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(len)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typ.BytePtr
- v3.AddArg(dst)
- v3.AddArg(ptr)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(dst, ptr, mem)
+ v1.AddArg3(v2, len, v3)
+ v.AddArg3(v0, cap, v1)
return true
}
// match: (Store dst (IMake itab data) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, typ.BytePtrPtr)
v0.AuxInt = config.PtrSize
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(data)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typ.Uintptr
- v1.AddArg(dst)
- v1.AddArg(itab)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, itab, mem)
+ v.AddArg3(v0, data, v1)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpAdd32withcarry, typ.Int32)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpAdd32carry, types.NewTuple(typ.UInt32, types.TypeFlags))
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v6.AddArg(y)
- v4.AddArg(v6)
+ v4.AddArg2(v5, v6)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
v7 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpAdd32carry, types.NewTuple(typ.UInt32, types.TypeFlags))
v9 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v9.AddArg(x)
- v8.AddArg(v9)
v10 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v10.AddArg(y)
- v8.AddArg(v10)
+ v8.AddArg2(v9, v10)
v7.AddArg(v8)
- v.AddArg(v7)
+ v.AddArg2(v0, v7)
return true
}
}
v0 := b.NewValue0(v.Pos, OpAnd32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpAnd32, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(y)
- v3.AddArg(v5)
- v.AddArg(v3)
+ v3.AddArg2(v4, v5)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpArg, typ.Int32)
v0.AuxInt = off + 4
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.UInt32)
v1.AuxInt = off
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, typ.UInt32)
v0.AuxInt = off + 4
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.UInt32)
v1.AuxInt = off
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, typ.Int32)
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.UInt32)
v1.AuxInt = off + 4
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, typ.UInt32)
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.UInt32)
v1.AuxInt = off + 4
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpBitLen32, typ.Int)
v3 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v6.AddArg(x)
v5.AddArg(v6)
- v3.AddArg(v5)
+ v3.AddArg2(v4, v5)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v1 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v1.AddArg(x)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpBswap32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v3.AddArg(x)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpCom32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v3.AddArg(x)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpConst32, typ.Int32)
v0.AuxInt = c >> 32
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v1.AuxInt = int64(int32(c))
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Const64 <t> [c])
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v0.AuxInt = c >> 32
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v1.AuxInt = int64(int32(c))
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v1.AddArg(x)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpAnd32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpCom32, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v5.AddArg(x)
v4.AddArg(v5)
v3.AddArg(v4)
- v2.AddArg(v3)
v6 := b.NewValue0(v.Pos, OpCtz32, typ.UInt32)
v7 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v7.AddArg(x)
v6.AddArg(v7)
- v2.AddArg(v6)
- v.AddArg(v2)
+ v2.AddArg2(v3, v6)
+ v.AddArg2(v0, v2)
return true
}
}
v0 := b.NewValue0(v.Pos, OpEq32, typ.Bool)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpEq32, typ.Bool)
v4 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(y)
- v3.AddArg(v5)
- v.AddArg(v3)
+ v3.AddArg2(v4, v5)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpLess32, typ.Bool)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpAndB, typ.Bool)
v4 := b.NewValue0(v.Pos, OpEq32, typ.Bool)
v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v6.AddArg(y)
- v4.AddArg(v6)
- v3.AddArg(v4)
+ v4.AddArg2(v5, v6)
v7 := b.NewValue0(v.Pos, OpLeq32U, typ.Bool)
v8 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v8.AddArg(x)
- v7.AddArg(v8)
v9 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v9.AddArg(y)
- v7.AddArg(v9)
- v3.AddArg(v7)
- v.AddArg(v3)
+ v7.AddArg2(v8, v9)
+ v3.AddArg2(v4, v7)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpLess32U, typ.Bool)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpAndB, typ.Bool)
v4 := b.NewValue0(v.Pos, OpEq32, typ.Bool)
v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v6.AddArg(y)
- v4.AddArg(v6)
- v3.AddArg(v4)
+ v4.AddArg2(v5, v6)
v7 := b.NewValue0(v.Pos, OpLeq32U, typ.Bool)
v8 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v8.AddArg(x)
- v7.AddArg(v8)
v9 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v9.AddArg(y)
- v7.AddArg(v9)
- v3.AddArg(v7)
- v.AddArg(v3)
+ v7.AddArg2(v8, v9)
+ v3.AddArg2(v4, v7)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpLess32, typ.Bool)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpAndB, typ.Bool)
v4 := b.NewValue0(v.Pos, OpEq32, typ.Bool)
v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v6.AddArg(y)
- v4.AddArg(v6)
- v3.AddArg(v4)
+ v4.AddArg2(v5, v6)
v7 := b.NewValue0(v.Pos, OpLess32U, typ.Bool)
v8 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v8.AddArg(x)
- v7.AddArg(v8)
v9 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v9.AddArg(y)
- v7.AddArg(v9)
- v3.AddArg(v7)
- v.AddArg(v3)
+ v7.AddArg2(v8, v9)
+ v3.AddArg2(v4, v7)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpLess32U, typ.Bool)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpAndB, typ.Bool)
v4 := b.NewValue0(v.Pos, OpEq32, typ.Bool)
v5 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v6.AddArg(y)
- v4.AddArg(v6)
- v3.AddArg(v4)
+ v4.AddArg2(v5, v6)
v7 := b.NewValue0(v.Pos, OpLess32U, typ.Bool)
v8 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v8.AddArg(x)
- v7.AddArg(v8)
v9 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v9.AddArg(y)
- v7.AddArg(v9)
- v3.AddArg(v7)
- v.AddArg(v3)
+ v7.AddArg2(v8, v9)
+ v3.AddArg2(v4, v7)
+ v.AddArg2(v0, v3)
return true
}
}
v1 := b.NewValue0(v.Pos, OpOffPtr, typ.Int32Ptr)
v1.AuxInt = 4
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(v1, mem)
v2 := b.NewValue0(v.Pos, OpLoad, typ.UInt32)
- v2.AddArg(ptr)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg2(ptr, mem)
+ v.AddArg2(v0, v2)
return true
}
// match: (Load <t> ptr mem)
v1 := b.NewValue0(v.Pos, OpOffPtr, typ.UInt32Ptr)
v1.AuxInt = 4
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(v1, mem)
v2 := b.NewValue0(v.Pos, OpLoad, typ.UInt32)
- v2.AddArg(ptr)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg2(ptr, mem)
+ v.AddArg2(v0, v2)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpLoad, typ.Int32)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.UInt32Ptr)
v2.AuxInt = 4
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
+ v.AddArg2(v0, v1)
return true
}
// match: (Load <t> ptr mem)
}
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpLoad, typ.UInt32)
- v0.AddArg(ptr)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(ptr, mem)
v1 := b.NewValue0(v.Pos, OpLoad, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOffPtr, typ.UInt32Ptr)
v2.AuxInt = 4
v2.AddArg(ptr)
- v1.AddArg(v2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(v2, mem)
+ v.AddArg2(v0, v1)
return true
}
return false
}
v.reset(OpLsh16x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Lsh16x64 x (Int64Make hi lo))
break
}
v.reset(OpLsh16x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
}
v.reset(OpLsh32x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Lsh32x64 x (Int64Make hi lo))
break
}
v.reset(OpLsh32x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpLsh32x16, typ.UInt32)
- v2.AddArg(hi)
- v2.AddArg(s)
- v1.AddArg(v2)
+ v2.AddArg2(hi, s)
v3 := b.NewValue0(v.Pos, OpRsh32Ux16, typ.UInt32)
- v3.AddArg(lo)
v4 := b.NewValue0(v.Pos, OpSub16, typ.UInt16)
v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v5.AuxInt = 32
- v4.AddArg(v5)
- v4.AddArg(s)
- v3.AddArg(v4)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v4.AddArg2(v5, s)
+ v3.AddArg2(lo, v4)
+ v1.AddArg2(v2, v3)
v6 := b.NewValue0(v.Pos, OpLsh32x16, typ.UInt32)
- v6.AddArg(lo)
v7 := b.NewValue0(v.Pos, OpSub16, typ.UInt16)
- v7.AddArg(s)
v8 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v8.AuxInt = 32
- v7.AddArg(v8)
- v6.AddArg(v7)
- v0.AddArg(v6)
- v.AddArg(v0)
+ v7.AddArg2(s, v8)
+ v6.AddArg2(lo, v7)
+ v0.AddArg2(v1, v6)
v9 := b.NewValue0(v.Pos, OpLsh32x16, typ.UInt32)
- v9.AddArg(lo)
- v9.AddArg(s)
- v.AddArg(v9)
+ v9.AddArg2(lo, s)
+ v.AddArg2(v0, v9)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32)
- v2.AddArg(hi)
- v2.AddArg(s)
- v1.AddArg(v2)
+ v2.AddArg2(hi, s)
v3 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32)
- v3.AddArg(lo)
v4 := b.NewValue0(v.Pos, OpSub32, typ.UInt32)
v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v5.AuxInt = 32
- v4.AddArg(v5)
- v4.AddArg(s)
- v3.AddArg(v4)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v4.AddArg2(v5, s)
+ v3.AddArg2(lo, v4)
+ v1.AddArg2(v2, v3)
v6 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32)
- v6.AddArg(lo)
v7 := b.NewValue0(v.Pos, OpSub32, typ.UInt32)
- v7.AddArg(s)
v8 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v8.AuxInt = 32
- v7.AddArg(v8)
- v6.AddArg(v7)
- v0.AddArg(v6)
- v.AddArg(v0)
+ v7.AddArg2(s, v8)
+ v6.AddArg2(lo, v7)
+ v0.AddArg2(v1, v6)
v9 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32)
- v9.AddArg(lo)
- v9.AddArg(s)
- v.AddArg(v9)
+ v9.AddArg2(lo, s)
+ v.AddArg2(v0, v9)
return true
}
return false
}
v.reset(OpLsh64x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Lsh64x64 x (Int64Make hi lo))
break
}
v.reset(OpLsh64x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpLsh32x8, typ.UInt32)
- v2.AddArg(hi)
- v2.AddArg(s)
- v1.AddArg(v2)
+ v2.AddArg2(hi, s)
v3 := b.NewValue0(v.Pos, OpRsh32Ux8, typ.UInt32)
- v3.AddArg(lo)
v4 := b.NewValue0(v.Pos, OpSub8, typ.UInt8)
v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v5.AuxInt = 32
- v4.AddArg(v5)
- v4.AddArg(s)
- v3.AddArg(v4)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v4.AddArg2(v5, s)
+ v3.AddArg2(lo, v4)
+ v1.AddArg2(v2, v3)
v6 := b.NewValue0(v.Pos, OpLsh32x8, typ.UInt32)
- v6.AddArg(lo)
v7 := b.NewValue0(v.Pos, OpSub8, typ.UInt8)
- v7.AddArg(s)
v8 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v8.AuxInt = 32
- v7.AddArg(v8)
- v6.AddArg(v7)
- v0.AddArg(v6)
- v.AddArg(v0)
+ v7.AddArg2(s, v8)
+ v6.AddArg2(lo, v7)
+ v0.AddArg2(v1, v6)
v9 := b.NewValue0(v.Pos, OpLsh32x8, typ.UInt32)
- v9.AddArg(lo)
- v9.AddArg(s)
- v.AddArg(v9)
+ v9.AddArg2(lo, s)
+ v.AddArg2(v0, v9)
return true
}
return false
}
v.reset(OpLsh8x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Lsh8x64 x (Int64Make hi lo))
break
}
v.reset(OpLsh8x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v2.AddArg(x)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v3.AddArg(y)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32)
v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v6 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v6.AddArg(x)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v7.AddArg(y)
- v5.AddArg(v7)
- v4.AddArg(v5)
+ v5.AddArg2(v6, v7)
v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32)
v9 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32))
v10 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v10.AddArg(x)
- v9.AddArg(v10)
v11 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v11.AddArg(y)
- v9.AddArg(v11)
+ v9.AddArg2(v10, v11)
v8.AddArg(v9)
- v4.AddArg(v8)
- v0.AddArg(v4)
- v.AddArg(v0)
+ v4.AddArg2(v5, v8)
+ v0.AddArg2(v1, v4)
v12 := b.NewValue0(v.Pos, OpSelect1, typ.UInt32)
v13 := b.NewValue0(v.Pos, OpMul32uhilo, types.NewTuple(typ.UInt32, typ.UInt32))
v14 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v14.AddArg(x)
- v13.AddArg(v14)
v15 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v15.AddArg(y)
- v13.AddArg(v15)
+ v13.AddArg2(v14, v15)
v12.AddArg(v13)
- v.AddArg(v12)
+ v.AddArg2(v0, v12)
return true
}
}
v.reset(OpSub64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpNeq32, typ.Bool)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpNeq32, typ.Bool)
v4 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(y)
- v3.AddArg(v5)
- v.AddArg(v3)
+ v3.AddArg2(v4, v5)
+ v.AddArg2(v0, v3)
return true
}
}
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(y)
- v3.AddArg(v5)
- v.AddArg(v3)
+ v3.AddArg2(v4, v5)
+ v.AddArg2(v0, v3)
return true
}
}
}
v.reset(OpRsh16Ux32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh16Ux64 x (Int64Make hi lo))
break
}
v.reset(OpRsh16Ux32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
}
v.reset(OpRsh16x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh16x64 x (Int64Make hi lo))
break
}
v.reset(OpRsh16x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
}
v.reset(OpRsh32Ux32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh32Ux64 x (Int64Make hi lo))
break
}
v.reset(OpRsh32Ux32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
}
v.reset(OpRsh32x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh32x64 x (Int64Make hi lo))
break
}
v.reset(OpRsh32x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
s := v_1
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpRsh32Ux16, typ.UInt32)
- v0.AddArg(hi)
- v0.AddArg(s)
- v.AddArg(v0)
+ v0.AddArg2(hi, s)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpRsh32Ux16, typ.UInt32)
- v3.AddArg(lo)
- v3.AddArg(s)
- v2.AddArg(v3)
+ v3.AddArg2(lo, s)
v4 := b.NewValue0(v.Pos, OpLsh32x16, typ.UInt32)
- v4.AddArg(hi)
v5 := b.NewValue0(v.Pos, OpSub16, typ.UInt16)
v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v6.AuxInt = 32
- v5.AddArg(v6)
- v5.AddArg(s)
- v4.AddArg(v5)
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v5.AddArg2(v6, s)
+ v4.AddArg2(hi, v5)
+ v2.AddArg2(v3, v4)
v7 := b.NewValue0(v.Pos, OpRsh32Ux16, typ.UInt32)
- v7.AddArg(hi)
v8 := b.NewValue0(v.Pos, OpSub16, typ.UInt16)
- v8.AddArg(s)
v9 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v9.AuxInt = 32
- v8.AddArg(v9)
- v7.AddArg(v8)
- v1.AddArg(v7)
- v.AddArg(v1)
+ v8.AddArg2(s, v9)
+ v7.AddArg2(hi, v8)
+ v1.AddArg2(v2, v7)
+ v.AddArg2(v0, v1)
return true
}
return false
s := v_1
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32)
- v0.AddArg(hi)
- v0.AddArg(s)
- v.AddArg(v0)
+ v0.AddArg2(hi, s)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32)
- v3.AddArg(lo)
- v3.AddArg(s)
- v2.AddArg(v3)
+ v3.AddArg2(lo, s)
v4 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32)
- v4.AddArg(hi)
v5 := b.NewValue0(v.Pos, OpSub32, typ.UInt32)
v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v6.AuxInt = 32
- v5.AddArg(v6)
- v5.AddArg(s)
- v4.AddArg(v5)
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v5.AddArg2(v6, s)
+ v4.AddArg2(hi, v5)
+ v2.AddArg2(v3, v4)
v7 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32)
- v7.AddArg(hi)
v8 := b.NewValue0(v.Pos, OpSub32, typ.UInt32)
- v8.AddArg(s)
v9 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v9.AuxInt = 32
- v8.AddArg(v9)
- v7.AddArg(v8)
- v1.AddArg(v7)
- v.AddArg(v1)
+ v8.AddArg2(s, v9)
+ v7.AddArg2(hi, v8)
+ v1.AddArg2(v2, v7)
+ v.AddArg2(v0, v1)
return true
}
return false
}
v.reset(OpRsh64Ux32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh64Ux64 x (Int64Make hi lo))
break
}
v.reset(OpRsh64Ux32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
s := v_1
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpRsh32Ux8, typ.UInt32)
- v0.AddArg(hi)
- v0.AddArg(s)
- v.AddArg(v0)
+ v0.AddArg2(hi, s)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpRsh32Ux8, typ.UInt32)
- v3.AddArg(lo)
- v3.AddArg(s)
- v2.AddArg(v3)
+ v3.AddArg2(lo, s)
v4 := b.NewValue0(v.Pos, OpLsh32x8, typ.UInt32)
- v4.AddArg(hi)
v5 := b.NewValue0(v.Pos, OpSub8, typ.UInt8)
v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v6.AuxInt = 32
- v5.AddArg(v6)
- v5.AddArg(s)
- v4.AddArg(v5)
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v5.AddArg2(v6, s)
+ v4.AddArg2(hi, v5)
+ v2.AddArg2(v3, v4)
v7 := b.NewValue0(v.Pos, OpRsh32Ux8, typ.UInt32)
- v7.AddArg(hi)
v8 := b.NewValue0(v.Pos, OpSub8, typ.UInt8)
- v8.AddArg(s)
v9 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v9.AuxInt = 32
- v8.AddArg(v9)
- v7.AddArg(v8)
- v1.AddArg(v7)
- v.AddArg(v1)
+ v8.AddArg2(s, v9)
+ v7.AddArg2(hi, v8)
+ v1.AddArg2(v2, v7)
+ v.AddArg2(v0, v1)
return true
}
return false
s := v_1
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpRsh32x16, typ.UInt32)
- v0.AddArg(hi)
- v0.AddArg(s)
- v.AddArg(v0)
+ v0.AddArg2(hi, s)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpRsh32Ux16, typ.UInt32)
- v3.AddArg(lo)
- v3.AddArg(s)
- v2.AddArg(v3)
+ v3.AddArg2(lo, s)
v4 := b.NewValue0(v.Pos, OpLsh32x16, typ.UInt32)
- v4.AddArg(hi)
v5 := b.NewValue0(v.Pos, OpSub16, typ.UInt16)
v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v6.AuxInt = 32
- v5.AddArg(v6)
- v5.AddArg(s)
- v4.AddArg(v5)
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v5.AddArg2(v6, s)
+ v4.AddArg2(hi, v5)
+ v2.AddArg2(v3, v4)
v7 := b.NewValue0(v.Pos, OpAnd32, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpRsh32x16, typ.UInt32)
- v8.AddArg(hi)
v9 := b.NewValue0(v.Pos, OpSub16, typ.UInt16)
- v9.AddArg(s)
v10 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v10.AuxInt = 32
- v9.AddArg(v10)
- v8.AddArg(v9)
- v7.AddArg(v8)
+ v9.AddArg2(s, v10)
+ v8.AddArg2(hi, v9)
v11 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v12 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v13 := b.NewValue0(v.Pos, OpRsh16Ux32, typ.UInt16)
- v13.AddArg(s)
v14 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v14.AuxInt = 5
- v13.AddArg(v14)
+ v13.AddArg2(s, v14)
v12.AddArg(v13)
v11.AddArg(v12)
- v7.AddArg(v11)
- v1.AddArg(v7)
- v.AddArg(v1)
+ v7.AddArg2(v8, v11)
+ v1.AddArg2(v2, v7)
+ v.AddArg2(v0, v1)
return true
}
return false
s := v_1
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpRsh32x32, typ.UInt32)
- v0.AddArg(hi)
- v0.AddArg(s)
- v.AddArg(v0)
+ v0.AddArg2(hi, s)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32)
- v3.AddArg(lo)
- v3.AddArg(s)
- v2.AddArg(v3)
+ v3.AddArg2(lo, s)
v4 := b.NewValue0(v.Pos, OpLsh32x32, typ.UInt32)
- v4.AddArg(hi)
v5 := b.NewValue0(v.Pos, OpSub32, typ.UInt32)
v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v6.AuxInt = 32
- v5.AddArg(v6)
- v5.AddArg(s)
- v4.AddArg(v5)
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v5.AddArg2(v6, s)
+ v4.AddArg2(hi, v5)
+ v2.AddArg2(v3, v4)
v7 := b.NewValue0(v.Pos, OpAnd32, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpRsh32x32, typ.UInt32)
- v8.AddArg(hi)
v9 := b.NewValue0(v.Pos, OpSub32, typ.UInt32)
- v9.AddArg(s)
v10 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v10.AuxInt = 32
- v9.AddArg(v10)
- v8.AddArg(v9)
- v7.AddArg(v8)
+ v9.AddArg2(s, v10)
+ v8.AddArg2(hi, v9)
v11 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v12 := b.NewValue0(v.Pos, OpRsh32Ux32, typ.UInt32)
- v12.AddArg(s)
v13 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v13.AuxInt = 5
- v12.AddArg(v13)
+ v12.AddArg2(s, v13)
v11.AddArg(v12)
- v7.AddArg(v11)
- v1.AddArg(v7)
- v.AddArg(v1)
+ v7.AddArg2(v8, v11)
+ v1.AddArg2(v2, v7)
+ v.AddArg2(v0, v1)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v3 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v3.AddArg(x)
v2.AddArg(v3)
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Rsh64x64 [c] x (Int64Make (Const32 [0]) lo))
}
v.reset(OpRsh64x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh64x64 x (Int64Make hi lo))
break
}
v.reset(OpRsh64x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
s := v_1
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpRsh32x8, typ.UInt32)
- v0.AddArg(hi)
- v0.AddArg(s)
- v.AddArg(v0)
+ v0.AddArg2(hi, s)
v1 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpRsh32Ux8, typ.UInt32)
- v3.AddArg(lo)
- v3.AddArg(s)
- v2.AddArg(v3)
+ v3.AddArg2(lo, s)
v4 := b.NewValue0(v.Pos, OpLsh32x8, typ.UInt32)
- v4.AddArg(hi)
v5 := b.NewValue0(v.Pos, OpSub8, typ.UInt8)
v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v6.AuxInt = 32
- v5.AddArg(v6)
- v5.AddArg(s)
- v4.AddArg(v5)
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v5.AddArg2(v6, s)
+ v4.AddArg2(hi, v5)
+ v2.AddArg2(v3, v4)
v7 := b.NewValue0(v.Pos, OpAnd32, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpRsh32x8, typ.UInt32)
- v8.AddArg(hi)
v9 := b.NewValue0(v.Pos, OpSub8, typ.UInt8)
- v9.AddArg(s)
v10 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v10.AuxInt = 32
- v9.AddArg(v10)
- v8.AddArg(v9)
- v7.AddArg(v8)
+ v9.AddArg2(s, v10)
+ v8.AddArg2(hi, v9)
v11 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v12 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v13 := b.NewValue0(v.Pos, OpRsh8Ux32, typ.UInt8)
- v13.AddArg(s)
v14 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v14.AuxInt = 5
- v13.AddArg(v14)
+ v13.AddArg2(s, v14)
v12.AddArg(v13)
v11.AddArg(v12)
- v7.AddArg(v11)
- v1.AddArg(v7)
- v.AddArg(v1)
+ v7.AddArg2(v8, v11)
+ v1.AddArg2(v2, v7)
+ v.AddArg2(v0, v1)
return true
}
return false
}
v.reset(OpRsh8Ux32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh8Ux64 x (Int64Make hi lo))
break
}
v.reset(OpRsh8Ux32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
}
v.reset(OpRsh8x32)
v.AuxInt = c
- v.AddArg(x)
- v.AddArg(lo)
+ v.AddArg2(x, lo)
return true
}
// match: (Rsh8x64 x (Int64Make hi lo))
break
}
v.reset(OpRsh8x32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpOr32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeromask, typ.UInt32)
v1.AddArg(hi)
- v0.AddArg(v1)
- v0.AddArg(lo)
- v.AddArg(v0)
+ v0.AddArg2(v1, lo)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpSignmask, typ.Int32)
v0.AddArg(x)
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpOffPtr, hi.Type.PtrTo())
v0.AuxInt = 4
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(hi)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = lo.Type
- v1.AddArg(dst)
- v1.AddArg(lo)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, lo, mem)
+ v.AddArg3(v0, hi, v1)
return true
}
// match: (Store {t} dst (Int64Make hi lo) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, lo.Type.PtrTo())
v0.AuxInt = 4
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(lo)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = hi.Type
- v1.AddArg(dst)
- v1.AddArg(hi)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(dst, hi, mem)
+ v.AddArg3(v0, lo, v1)
return true
}
return false
v0 := b.NewValue0(v.Pos, OpSub32withcarry, typ.Int32)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags)
v4 := b.NewValue0(v.Pos, OpSub32carry, types.NewTuple(typ.UInt32, types.TypeFlags))
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(x)
- v4.AddArg(v5)
v6 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v6.AddArg(y)
- v4.AddArg(v6)
+ v4.AddArg2(v5, v6)
v3.AddArg(v4)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg3(v1, v2, v3)
v7 := b.NewValue0(v.Pos, OpSelect0, typ.UInt32)
v8 := b.NewValue0(v.Pos, OpSub32carry, types.NewTuple(typ.UInt32, types.TypeFlags))
v9 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v9.AddArg(x)
- v8.AddArg(v9)
v10 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v10.AddArg(y)
- v8.AddArg(v10)
+ v8.AddArg2(v9, v10)
v7.AddArg(v8)
- v.AddArg(v7)
+ v.AddArg2(v0, v7)
return true
}
}
v0 := b.NewValue0(v.Pos, OpXor32, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpInt64Hi, typ.UInt32)
v2.AddArg(y)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpXor32, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpInt64Lo, typ.UInt32)
v5.AddArg(y)
- v3.AddArg(v5)
- v.AddArg(v3)
+ v3.AddArg2(v4, v5)
+ v.AddArg2(v0, v3)
return true
}
}
v.reset(OpInt64Make)
v0 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v0.AuxInt = 0
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpArg, typ.BytePtr)
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.Int)
v1.AuxInt = off + config.PtrSize
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, v.Type.Elem().PtrTo())
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.Int)
v1.AuxInt = off + config.PtrSize
v1.Aux = n
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpArg, typ.Int)
v2.AuxInt = off + 2*config.PtrSize
v2.Aux = n
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, typ.Uintptr)
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.BytePtr)
v1.AuxInt = off + config.PtrSize
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, typ.Float64)
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.Float64)
v1.AuxInt = off + 8
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, typ.Float32)
v0.AuxInt = off
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, typ.Float32)
v1.AuxInt = off + 4
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg <t>)
v0 := b.NewValue0(v.Pos, OpArg, t.FieldType(0))
v0.AuxInt = off + t.FieldOff(0)
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, t.FieldType(1))
v1.AuxInt = off + t.FieldOff(1)
v1.Aux = n
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (Arg <t> {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, t.FieldType(0))
v0.AuxInt = off + t.FieldOff(0)
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, t.FieldType(1))
v1.AuxInt = off + t.FieldOff(1)
v1.Aux = n
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpArg, t.FieldType(2))
v2.AuxInt = off + t.FieldOff(2)
v2.Aux = n
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (Arg <t> {n} [off])
v0 := b.NewValue0(v.Pos, OpArg, t.FieldType(0))
v0.AuxInt = off + t.FieldOff(0)
v0.Aux = n
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpArg, t.FieldType(1))
v1.AuxInt = off + t.FieldOff(1)
v1.Aux = n
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpArg, t.FieldType(2))
v2.AuxInt = off + t.FieldOff(2)
v2.Aux = n
- v.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpArg, t.FieldType(3))
v3.AuxInt = off + t.FieldOff(3)
v3.Aux = n
- v.AddArg(v3)
+ v.AddArg4(v0, v1, v2, v3)
return true
}
// match: (Arg <t>)
}
z := v_1_1
v.reset(OpMul16)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAdd16, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
continue
}
v.reset(OpAdd16)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAdd16, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
continue
}
v.reset(OpAdd16)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub16, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
break
}
v.reset(OpSub16)
v0 := b.NewValue0(v.Pos, OpAdd16, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
break
v.reset(OpAdd16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpSub16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
v.reset(OpAdd16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
}
z := v_1_1
v.reset(OpMul32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAdd32, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
continue
}
v.reset(OpAdd32)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAdd32, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
continue
}
v.reset(OpAdd32)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub32, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
break
}
v.reset(OpSub32)
v0 := b.NewValue0(v.Pos, OpAdd32, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
break
v.reset(OpAdd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpSub32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
v.reset(OpAdd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
}
z := v_1_1
v.reset(OpMul64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAdd64, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
continue
}
v.reset(OpAdd64)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAdd64, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
continue
}
v.reset(OpAdd64)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub64, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
break
}
v.reset(OpSub64)
v0 := b.NewValue0(v.Pos, OpAdd64, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
break
v.reset(OpAdd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpSub64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
v.reset(OpAdd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c - d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
}
z := v_1_1
v.reset(OpMul8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpAdd8, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
continue
}
v.reset(OpAdd8)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAdd8, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
continue
}
v.reset(OpAdd8)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub8, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
break
}
v.reset(OpSub8)
v0 := b.NewValue0(v.Pos, OpAdd8, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
break
v.reset(OpAdd8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpSub8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
v.reset(OpAdd8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
break
}
y := v_1_1
v.reset(OpAnd16)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAnd16)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAnd16, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpAnd16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c & d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
y := v_1_1
v.reset(OpAnd32)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAnd32)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAnd32, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpAnd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c & d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
y := v_1_1
v.reset(OpAnd64)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAnd64)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAnd64, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpAnd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c & d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
y := v_1_1
v.reset(OpAnd8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
continue
}
v.reset(OpAnd8)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpAnd8, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpAnd8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c & d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
for {
v.reset(OpIMake)
v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
}
v.reset(OpSliceMake)
v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo())
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConst32, typ.Int)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst32, typ.Int)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
// match: (ConstSlice)
}
v.reset(OpSliceMake)
v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo())
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConst64, typ.Int)
v1.AuxInt = 0
- v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst64, typ.Int)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg3(v0, v1, v2)
return true
}
return false
}
v.reset(OpStringMake)
v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConst32, typ.Int)
v1.AuxInt = 0
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (ConstString {s})
}
v.reset(OpStringMake)
v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpConst64, typ.Int)
v1.AuxInt = 0
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
// match: (ConstString {s})
v0.Aux = fe.StringData(s.(string))
v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpConst32, typ.Int)
v2.AuxInt = int64(len(s.(string)))
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (ConstString {s})
v0.Aux = fe.StringData(s.(string))
v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr)
v0.AddArg(v1)
- v.AddArg(v0)
v2 := b.NewValue0(v.Pos, OpConst64, typ.Int)
v2.AuxInt = int64(len(s.(string)))
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
return false
continue
}
v.reset(OpAdd64)
- v.AddArg(ptr)
- v.AddArg(off)
+ v.AddArg2(ptr, off)
return true
}
break
continue
}
v.reset(OpAdd32)
- v.AddArg(ptr)
- v.AddArg(off)
+ v.AddArg2(ptr, off)
return true
}
break
break
}
v.reset(OpRsh16Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c & 0xffff)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div16 <t> n (Const16 [c]))
}
v.reset(OpNeg16)
v0 := b.NewValue0(v.Pos, OpDiv16, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst16, t)
v1.AuxInt = -c
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
}
v.reset(OpRsh16Ux64)
v0 := b.NewValue0(v.Pos, OpAnd16, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpNeg16, t)
v1.AddArg(x)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = 15
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Div16 <t> n (Const16 [c]))
}
v.reset(OpRsh16x64)
v0 := b.NewValue0(v.Pos, OpAdd16, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t)
v2 := b.NewValue0(v.Pos, OpRsh16x64, t)
- v2.AddArg(n)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = 15
- v2.AddArg(v3)
- v1.AddArg(v2)
+ v2.AddArg2(n, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 16 - log2(c)
- v1.AddArg(v4)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(v2, v4)
+ v0.AddArg2(n, v1)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = log2(c)
- v.AddArg(v5)
+ v.AddArg2(v0, v5)
return true
}
// match: (Div16 <t> x (Const16 [c]))
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(smagic(16, c).m)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 16 + smagic(16, c).s
- v0.AddArg(v4)
- v.AddArg(v0)
+ v0.AddArg2(v1, v4)
v5 := b.NewValue0(v.Pos, OpRsh32x64, t)
v6 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v6.AddArg(x)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v7.AuxInt = 31
- v5.AddArg(v7)
- v.AddArg(v5)
+ v5.AddArg2(v6, v7)
+ v.AddArg2(v0, v5)
return true
}
return false
break
}
v.reset(OpRsh16Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c & 0xffff)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div16u x (Const16 [c]))
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(1<<16 + umagic(16, c).m)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 16 + umagic(16, c).s
- v0.AddArg(v4)
+ v0.AddArg2(v1, v4)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(1<<15 + umagic(16, c).m/2)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 16 + umagic(16, c).s - 1
- v0.AddArg(v4)
+ v0.AddArg2(v1, v4)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(1<<15 + (umagic(16, c).m+1)/2)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32)
v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = 1
- v3.AddArg(v5)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v3.AddArg2(v4, v5)
+ v1.AddArg2(v2, v3)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v6.AuxInt = 16 + umagic(16, c).s - 2
- v0.AddArg(v6)
+ v0.AddArg2(v1, v6)
v.AddArg(v0)
return true
}
v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 16
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v2.AddArg2(v3, v4)
v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v6.AuxInt = int64(umagic(16, c).m)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v7.AddArg(x)
- v5.AddArg(v7)
- v1.AddArg(v5)
- v0.AddArg(v1)
+ v5.AddArg2(v6, v7)
+ v1.AddArg2(v2, v5)
v8 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v8.AuxInt = 16 + umagic(16, c).s - 1
- v0.AddArg(v8)
+ v0.AddArg2(v1, v8)
v.AddArg(v0)
return true
}
break
}
v.reset(OpRsh32Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c & 0xffffffff)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div32 <t> n (Const32 [c]))
}
v.reset(OpNeg32)
v0 := b.NewValue0(v.Pos, OpDiv32, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst32, t)
v1.AuxInt = -c
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
}
v.reset(OpRsh32Ux64)
v0 := b.NewValue0(v.Pos, OpAnd32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpNeg32, t)
v1.AddArg(x)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = 31
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Div32 <t> n (Const32 [c]))
}
v.reset(OpRsh32x64)
v0 := b.NewValue0(v.Pos, OpAdd32, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t)
v2 := b.NewValue0(v.Pos, OpRsh32x64, t)
- v2.AddArg(n)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = 31
- v2.AddArg(v3)
- v1.AddArg(v2)
+ v2.AddArg2(n, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 32 - log2(c)
- v1.AddArg(v4)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(v2, v4)
+ v0.AddArg2(n, v1)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = log2(c)
- v.AddArg(v5)
+ v.AddArg2(v0, v5)
return true
}
// match: (Div32 <t> x (Const32 [c]))
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(smagic(32, c).m)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 32 + smagic(32, c).s
- v0.AddArg(v4)
- v.AddArg(v0)
+ v0.AddArg2(v1, v4)
v5 := b.NewValue0(v.Pos, OpRsh64x64, t)
v6 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64)
v6.AddArg(x)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v7.AuxInt = 63
- v5.AddArg(v7)
- v.AddArg(v5)
+ v5.AddArg2(v6, v7)
+ v.AddArg2(v0, v5)
return true
}
// match: (Div32 <t> x (Const32 [c]))
v1 := b.NewValue0(v.Pos, OpHmul32, t)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(smagic(32, c).m / 2))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = smagic(32, c).s - 1
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpRsh32x64, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = 31
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
// match: (Div32 <t> x (Const32 [c]))
v2 := b.NewValue0(v.Pos, OpHmul32, t)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(int32(smagic(32, c).m))
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v2.AddArg2(v3, x)
+ v1.AddArg2(v2, x)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = smagic(32, c).s
- v0.AddArg(v4)
- v.AddArg(v0)
+ v0.AddArg2(v1, v4)
v5 := b.NewValue0(v.Pos, OpRsh32x64, t)
- v5.AddArg(x)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v6.AuxInt = 31
- v5.AddArg(v6)
- v.AddArg(v5)
+ v5.AddArg2(x, v6)
+ v.AddArg2(v0, v5)
return true
}
return false
break
}
v.reset(OpMul32F)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst32F, t)
v0.AuxInt = auxFrom32F(1 / auxTo32F(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpRsh32Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c & 0xffffffff)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div32u x (Const32 [c]))
v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v1.AuxInt = int64(int32(1<<31 + umagic(32, c).m/2))
- v0.AddArg(v1)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(v1, x)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = umagic(32, c).s - 1
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Div32u x (Const32 [c]))
v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v1.AuxInt = int64(int32(1<<31 + (umagic(32, c).m+1)/2))
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = 1
- v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v2.AddArg2(x, v3)
+ v0.AddArg2(v1, v2)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = umagic(32, c).s - 2
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
// match: (Div32u x (Const32 [c]))
v.reset(OpRsh32Ux64)
v.Type = typ.UInt32
v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(umagic(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(v2, x)
+ v0.AddArg2(x, v1)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = umagic(32, c).s - 1
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
// match: (Div32u x (Const32 [c]))
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(1<<31 + umagic(32, c).m/2)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 32 + umagic(32, c).s - 1
- v0.AddArg(v4)
+ v0.AddArg2(v1, v4)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(1<<31 + (umagic(32, c).m+1)/2)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64)
v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v4.AddArg(x)
- v3.AddArg(v4)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = 1
- v3.AddArg(v5)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v3.AddArg2(v4, v5)
+ v1.AddArg2(v2, v3)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v6.AuxInt = 32 + umagic(32, c).s - 2
- v0.AddArg(v6)
+ v0.AddArg2(v1, v6)
v.AddArg(v0)
return true
}
v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64)
v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v3.AddArg(x)
- v2.AddArg(v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 32
- v2.AddArg(v4)
- v1.AddArg(v2)
+ v2.AddArg2(v3, v4)
v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32)
v6.AuxInt = int64(umagic(32, c).m)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64)
v7.AddArg(x)
- v5.AddArg(v7)
- v1.AddArg(v5)
- v0.AddArg(v1)
+ v5.AddArg2(v6, v7)
+ v1.AddArg2(v2, v5)
v8 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v8.AuxInt = 32 + umagic(32, c).s - 1
- v0.AddArg(v8)
+ v0.AddArg2(v1, v8)
v.AddArg(v0)
return true
}
break
}
v.reset(OpRsh64Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div64 n (Const64 [-1<<63]))
}
v.reset(OpNeg64)
v0 := b.NewValue0(v.Pos, OpDiv64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = -c
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
}
v.reset(OpRsh64Ux64)
v0 := b.NewValue0(v.Pos, OpAnd64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpNeg64, t)
v1.AddArg(x)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = 63
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Div64 <t> n (Const64 [c]))
}
v.reset(OpRsh64x64)
v0 := b.NewValue0(v.Pos, OpAdd64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t)
v2 := b.NewValue0(v.Pos, OpRsh64x64, t)
- v2.AddArg(n)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = 63
- v2.AddArg(v3)
- v1.AddArg(v2)
+ v2.AddArg2(n, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 64 - log2(c)
- v1.AddArg(v4)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(v2, v4)
+ v0.AddArg2(n, v1)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = log2(c)
- v.AddArg(v5)
+ v.AddArg2(v0, v5)
return true
}
// match: (Div64 <t> x (Const64 [c]))
v1 := b.NewValue0(v.Pos, OpHmul64, t)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(smagic(64, c).m / 2)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = smagic(64, c).s - 1
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpRsh64x64, t)
- v4.AddArg(x)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = 63
- v4.AddArg(v5)
- v.AddArg(v4)
+ v4.AddArg2(x, v5)
+ v.AddArg2(v0, v4)
return true
}
// match: (Div64 <t> x (Const64 [c]))
v2 := b.NewValue0(v.Pos, OpHmul64, t)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = int64(smagic(64, c).m)
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v2.AddArg2(v3, x)
+ v1.AddArg2(v2, x)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = smagic(64, c).s
- v0.AddArg(v4)
- v.AddArg(v0)
+ v0.AddArg2(v1, v4)
v5 := b.NewValue0(v.Pos, OpRsh64x64, t)
- v5.AddArg(x)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v6.AuxInt = 63
- v5.AddArg(v6)
- v.AddArg(v5)
+ v5.AddArg2(x, v6)
+ v.AddArg2(v0, v5)
return true
}
return false
break
}
v.reset(OpMul64F)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64F, t)
v0.AuxInt = auxFrom64F(1 / auxTo64F(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpRsh64Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div64u n (Const64 [-1<<63]))
break
}
v.reset(OpRsh64Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = 63
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div64u x (Const64 [c]))
v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v1.AuxInt = int64(1<<63 + umagic(64, c).m/2)
- v0.AddArg(v1)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(v1, x)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = umagic(64, c).s - 1
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Div64u x (Const64 [c]))
v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64)
v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v1.AuxInt = int64(1<<63 + (umagic(64, c).m+1)/2)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64)
- v2.AddArg(x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = 1
- v2.AddArg(v3)
- v0.AddArg(v2)
- v.AddArg(v0)
+ v2.AddArg2(x, v3)
+ v0.AddArg2(v1, v2)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = umagic(64, c).s - 2
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
// match: (Div64u x (Const64 [c]))
v.reset(OpRsh64Ux64)
v.Type = typ.UInt64
v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(umagic(64, c).m)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(v2, x)
+ v0.AddArg2(x, v1)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = umagic(64, c).s - 1
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
return false
break
}
v.reset(OpRsh8Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c & 0xff)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div8 <t> n (Const8 [c]))
}
v.reset(OpNeg8)
v0 := b.NewValue0(v.Pos, OpDiv8, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst8, t)
v1.AuxInt = -c
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
}
v.reset(OpRsh8Ux64)
v0 := b.NewValue0(v.Pos, OpAnd8, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpNeg8, t)
v1.AddArg(x)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = 7
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
// match: (Div8 <t> n (Const8 [c]))
}
v.reset(OpRsh8x64)
v0 := b.NewValue0(v.Pos, OpAdd8, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t)
v2 := b.NewValue0(v.Pos, OpRsh8x64, t)
- v2.AddArg(n)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = 7
- v2.AddArg(v3)
- v1.AddArg(v2)
+ v2.AddArg2(n, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 8 - log2(c)
- v1.AddArg(v4)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg2(v2, v4)
+ v0.AddArg2(n, v1)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = log2(c)
- v.AddArg(v5)
+ v.AddArg2(v0, v5)
return true
}
// match: (Div8 <t> x (Const8 [c]))
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(smagic(8, c).m)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 8 + smagic(8, c).s
- v0.AddArg(v4)
- v.AddArg(v0)
+ v0.AddArg2(v1, v4)
v5 := b.NewValue0(v.Pos, OpRsh32x64, t)
v6 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v6.AddArg(x)
- v5.AddArg(v6)
v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v7.AuxInt = 31
- v5.AddArg(v7)
- v.AddArg(v5)
+ v5.AddArg2(v6, v7)
+ v.AddArg2(v0, v5)
return true
}
return false
break
}
v.reset(OpRsh8Ux64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c & 0xff)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Div8u x (Const8 [c]))
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(1<<8 + umagic(8, c).m)
- v1.AddArg(v2)
v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v3.AddArg(x)
- v1.AddArg(v3)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = 8 + umagic(8, c).s
- v0.AddArg(v4)
+ v0.AddArg2(v1, v4)
v.AddArg(v0)
return true
}
v.reset(OpEq16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = c & 0xffff
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
break
v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32)
v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32)
v2.AuxInt = c
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
break
v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16)
v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v2.AuxInt = int64(int16(udivisible(16, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v3.AuxInt = int64(16 - udivisible(16, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v4.AuxInt = int64(int16(udivisible(16, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16)
v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v2.AuxInt = int64(int16(udivisible(16, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v3.AuxInt = int64(16 - udivisible(16, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v4.AuxInt = int64(int16(udivisible(16, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16)
v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v2.AuxInt = int64(int16(udivisible(16, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v3.AuxInt = int64(16 - udivisible(16, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v4.AuxInt = int64(int16(udivisible(16, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16)
v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v2.AuxInt = int64(int16(udivisible(16, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v3.AuxInt = int64(16 - udivisible(16, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v4.AuxInt = int64(int16(udivisible(16, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16)
v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v3.AuxInt = int64(int16(sdivisible(16, c).m))
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v4.AuxInt = int64(int16(sdivisible(16, c).a))
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v5.AuxInt = int64(16 - sdivisible(16, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16)
v6.AuxInt = int64(int16(sdivisible(16, c).max))
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
}
v.reset(OpEq16)
v0 := b.NewValue0(v.Pos, OpAnd16, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst16, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst16, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpEq16)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpNeq16)
v0 := b.NewValue0(v.Pos, OpAnd16, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst16, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst16, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpEq32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(udivisible(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(32 - udivisible(32, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(udivisible(32, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(udivisible(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(32 - udivisible(32, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(udivisible(32, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(udivisible(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(32 - udivisible(32, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(udivisible(32, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(udivisible(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(32 - udivisible(32, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(udivisible(32, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(udivisible(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(32 - udivisible(32, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(udivisible(32, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = int64(int32(udivisible(32, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(32 - udivisible(32, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(udivisible(32, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(int32(sdivisible(32, c).m))
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(sdivisible(32, c).a))
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v5.AuxInt = int64(32 - sdivisible(32, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v6.AuxInt = int64(int32(sdivisible(32, c).max))
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(int32(sdivisible(32, c).m))
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(sdivisible(32, c).a))
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v5.AuxInt = int64(32 - sdivisible(32, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v6.AuxInt = int64(int32(sdivisible(32, c).max))
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = int64(int32(sdivisible(32, c).m))
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v4.AuxInt = int64(int32(sdivisible(32, c).a))
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v5.AuxInt = int64(32 - sdivisible(32, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v6.AuxInt = int64(int32(sdivisible(32, c).max))
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
}
v.reset(OpEq32)
v0 := b.NewValue0(v.Pos, OpAnd32, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst32, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpEq32)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpNeq32)
v0 := b.NewValue0(v.Pos, OpAnd32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst32, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpEq64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c - d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(udivisible(64, c).m)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = int64(64 - udivisible(64, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = int64(udivisible(64, c).max)
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(udivisible(64, c).m)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = int64(64 - udivisible(64, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = int64(udivisible(64, c).max)
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v2.AuxInt = int64(udivisible(64, c).m)
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = int64(64 - udivisible(64, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = int64(udivisible(64, c).max)
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = int64(sdivisible(64, c).m)
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = int64(sdivisible(64, c).a)
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = int64(64 - sdivisible(64, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v6.AuxInt = int64(sdivisible(64, c).max)
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64)
v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v3.AuxInt = int64(sdivisible(64, c).m)
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v4.AuxInt = int64(sdivisible(64, c).a)
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v5.AuxInt = int64(64 - sdivisible(64, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v6.AuxInt = int64(sdivisible(64, c).max)
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
}
v.reset(OpEq64)
v0 := b.NewValue0(v.Pos, OpAnd64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpEq64)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpNeq64)
v0 := b.NewValue0(v.Pos, OpAnd64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpEq8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32)
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v2.AuxInt = c & 0xff
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
break
v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32)
v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32)
v1.AddArg(x)
- v0.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32)
v2.AuxInt = c
- v0.AddArg(v2)
- v.AddArg(v0)
+ v0.AddArg2(v1, v2)
v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32)
v3.AuxInt = 0
- v.AddArg(v3)
+ v.AddArg2(v0, v3)
return true
}
break
v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8)
v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v2.AuxInt = int64(int8(udivisible(8, c).m))
- v1.AddArg(v2)
- v1.AddArg(x)
- v0.AddArg(v1)
+ v1.AddArg2(v2, x)
v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v3.AuxInt = int64(8 - udivisible(8, c).k)
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v4.AuxInt = int64(int8(udivisible(8, c).max))
- v.AddArg(v4)
+ v.AddArg2(v0, v4)
return true
}
}
v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8)
v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v3.AuxInt = int64(int8(sdivisible(8, c).m))
- v2.AddArg(v3)
- v2.AddArg(x)
- v1.AddArg(v2)
+ v2.AddArg2(v3, x)
v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v4.AuxInt = int64(int8(sdivisible(8, c).a))
- v1.AddArg(v4)
- v0.AddArg(v1)
+ v1.AddArg2(v2, v4)
v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v5.AuxInt = int64(8 - sdivisible(8, c).k)
- v0.AddArg(v5)
- v.AddArg(v0)
+ v0.AddArg2(v1, v5)
v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8)
v6.AuxInt = int64(int8(sdivisible(8, c).max))
- v.AddArg(v6)
+ v.AddArg2(v0, v6)
return true
}
}
}
v.reset(OpEq8)
v0 := b.NewValue0(v.Pos, OpAnd8, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst8, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst8, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpEq8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpNeq8)
v0 := b.NewValue0(v.Pos, OpAnd8, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst8, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst8, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpEqPtr)
v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpEqPtr)
v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
}
val := v_1.Args[0]
v.reset(OpIMake)
- v.AddArg(typ)
- v.AddArg(val)
+ v.AddArg2(typ, val)
return true
}
// match: (IMake typ (ArrayMake1 val))
}
val := v_1.Args[0]
v.reset(OpIMake)
- v.AddArg(typ)
- v.AddArg(val)
+ v.AddArg2(typ, val)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type)
v1.AuxInt = o1
v1.AddArg(p3)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (Load <t1> op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _))))
v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type)
v1.AuxInt = o1
v1.AddArg(p4)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (Load <t1> op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _)))))
v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type)
v1.AuxInt = o1
v1.AddArg(p5)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (Load <t1> op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _))))))
v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type)
v1.AuxInt = o1
v1.AddArg(p6)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (Load <t1> (OffPtr [o] p1) (Zero [n] p2 _))
v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v1.AuxInt = 0
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
v.AddArg(v0)
return true
}
v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v1.AuxInt = 0
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(v1, mem)
v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1))
v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v3.AuxInt = t.FieldOff(1)
v3.AddArg(ptr)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg2(v3, mem)
+ v.AddArg2(v0, v2)
return true
}
// match: (Load <t> ptr mem)
v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v1.AuxInt = 0
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(v1, mem)
v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1))
v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v3.AuxInt = t.FieldOff(1)
v3.AddArg(ptr)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg2(v3, mem)
v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2))
v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo())
v5.AuxInt = t.FieldOff(2)
v5.AddArg(ptr)
- v4.AddArg(v5)
- v4.AddArg(mem)
- v.AddArg(v4)
+ v4.AddArg2(v5, mem)
+ v.AddArg3(v0, v2, v4)
return true
}
// match: (Load <t> ptr mem)
v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v1.AuxInt = 0
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg2(v1, mem)
v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1))
v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v3.AuxInt = t.FieldOff(1)
v3.AddArg(ptr)
- v2.AddArg(v3)
- v2.AddArg(mem)
- v.AddArg(v2)
+ v2.AddArg2(v3, mem)
v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2))
v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo())
v5.AuxInt = t.FieldOff(2)
v5.AddArg(ptr)
- v4.AddArg(v5)
- v4.AddArg(mem)
- v.AddArg(v4)
+ v4.AddArg2(v5, mem)
v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3))
v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo())
v7.AuxInt = t.FieldOff(3)
v7.AddArg(ptr)
- v6.AddArg(v7)
- v6.AddArg(mem)
- v.AddArg(v6)
+ v6.AddArg2(v7, mem)
+ v.AddArg4(v0, v2, v4, v6)
return true
}
// match: (Load <t> _ _)
}
v.reset(OpArrayMake1)
v0 := b.NewValue0(v.Pos, OpLoad, t.Elem())
- v0.AddArg(ptr)
- v0.AddArg(mem)
+ v0.AddArg2(ptr, mem)
v.AddArg(v0)
return true
}
}
c := v_1.AuxInt
v.reset(OpLsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh16x16 (Const16 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh16x32 (Const16 [0]) _)
break
}
v.reset(OpLsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpLsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpLsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh16x8 (Const16 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh32x16 (Const32 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh32x32 (Const32 [0]) _)
break
}
v.reset(OpLsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpLsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpLsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh32x8 (Const32 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh64x16 (Const64 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh64x32 (Const64 [0]) _)
break
}
v.reset(OpLsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpLsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpLsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh64x8 (Const64 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh8x16 (Const8 [0]) _)
}
c := v_1.AuxInt
v.reset(OpLsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh8x32 (Const8 [0]) _)
break
}
v.reset(OpLsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpLsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpLsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Lsh8x8 (Const8 [0]) _)
break
}
v.reset(OpAnd16)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = (c & 0xffff) - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod16 <t> n (Const16 [c]))
}
v.reset(OpMod16)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = -c
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod16 <t> x (Const16 [c]))
break
}
v.reset(OpSub16)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul16, t)
v1 := b.NewValue0(v.Pos, OpDiv16, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst16, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst16, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd16)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = (c & 0xffff) - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod16u <t> x (Const16 [c]))
break
}
v.reset(OpSub16)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul16, t)
v1 := b.NewValue0(v.Pos, OpDiv16u, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst16, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst16, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd32)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = (c & 0xffffffff) - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod32 <t> n (Const32 [c]))
}
v.reset(OpMod32)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = -c
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod32 <t> x (Const32 [c]))
break
}
v.reset(OpSub32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul32, t)
v1 := b.NewValue0(v.Pos, OpDiv32, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst32, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd32)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = (c & 0xffffffff) - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod32u <t> x (Const32 [c]))
break
}
v.reset(OpSub32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul32, t)
v1 := b.NewValue0(v.Pos, OpDiv32u, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst32, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod64 n (Const64 [-1<<63]))
}
v.reset(OpMod64)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = -c
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod64 <t> x (Const64 [c]))
break
}
v.reset(OpSub64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul64, t)
v1 := b.NewValue0(v.Pos, OpDiv64, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod64u <t> n (Const64 [-1<<63]))
break
}
v.reset(OpAnd64)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 1<<63 - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod64u <t> x (Const64 [c]))
break
}
v.reset(OpSub64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul64, t)
v1 := b.NewValue0(v.Pos, OpDiv64u, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst64, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd8)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = (c & 0xff) - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod8 <t> n (Const8 [c]))
}
v.reset(OpMod8)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = -c
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod8 <t> x (Const8 [c]))
break
}
v.reset(OpSub8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul8, t)
v1 := b.NewValue0(v.Pos, OpDiv8, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst8, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst8, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
break
}
v.reset(OpAnd8)
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = (c & 0xff) - 1
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
// match: (Mod8u <t> x (Const8 [c]))
break
}
v.reset(OpSub8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpMul8, t)
v1 := b.NewValue0(v.Pos, OpDiv8u, t)
- v1.AddArg(x)
v2 := b.NewValue0(v.Pos, OpConst8, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v0.AddArg(v1)
+ v1.AddArg2(x, v2)
v3 := b.NewValue0(v.Pos, OpConst8, t)
v3.AuxInt = c
- v0.AddArg(v3)
- v.AddArg(v0)
+ v0.AddArg2(v1, v3)
+ v.AddArg2(x, v0)
return true
}
return false
v.reset(OpZero)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(mem)
+ v.AddArg2(dst1, mem)
return true
}
// match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _)))
v.reset(OpZero)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(mem)
+ v.AddArg2(dst1, mem)
return true
}
// match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem))
v.reset(OpMove)
v.AuxInt = n
v.Aux = t1
- v.AddArg(dst1)
- v.AddArg(src1)
- v.AddArg(mem)
+ v.AddArg3(dst1, src1, mem)
return true
}
// match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem))
v.reset(OpMove)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(src1)
- v.AddArg(mem)
+ v.AddArg3(dst1, src1, mem)
return true
}
// match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem)))
v.reset(OpMove)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(src1)
v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem)
v0.Aux = x
v0.AddArg(mem)
- v.AddArg(v0)
+ v.AddArg3(dst1, src1, v0)
return true
}
// match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem))
v.reset(OpMove)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(src1)
- v.AddArg(mem)
+ v.AddArg3(dst1, src1, mem)
return true
}
// match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem)))
v.reset(OpMove)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(src1)
v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem)
v0.Aux = x
v0.AddArg(mem)
- v.AddArg(v0)
+ v.AddArg3(dst1, src1, v0)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [0] p3) d2 _)))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = 0
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(v2, d2, mem)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [0] p4) d3 _))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = 0
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(v4, d3, mem)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [o4] p4) d3 (Store {t5} op5:(OffPtr <tt5> [0] p5) d4 _)))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = o4
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = t5
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = 0
v6.AddArg(dst)
- v5.AddArg(v6)
- v5.AddArg(d4)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(v6, d4, mem)
+ v3.AddArg3(v4, d3, v5)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [0] p3) d2 _))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = 0
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(v2, d2, mem)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [0] p4) d3 _)))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = 0
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(v4, d3, mem)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [o4] p4) d3 (Store {t5} op5:(OffPtr <tt5> [0] p5) d4 _))))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = o4
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = t5
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = 0
v6.AddArg(dst)
- v5.AddArg(v6)
- v5.AddArg(d4)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(v6, d4, mem)
+ v3.AddArg3(v4, d3, v5)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Zero {t3} [n] p3 _)))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v1.AuxInt = n
v1.Aux = t1
- v1.AddArg(dst)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(dst, mem)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Zero {t4} [n] p4 _))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v3.AuxInt = n
v3.Aux = t1
- v3.AddArg(dst)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg2(dst, mem)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Zero {t5} [n] p5 _)))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = o4
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v5.AuxInt = n
v5.Aux = t1
- v5.AddArg(dst)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg2(dst, mem)
+ v3.AddArg3(v4, d3, v5)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Store {t5} (OffPtr <tt5> [o5] p5) d4 (Zero {t6} [n] p6 _))))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = o4
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = t5
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = o5
v6.AddArg(dst)
- v5.AddArg(v6)
- v5.AddArg(d4)
v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v7.AuxInt = n
v7.Aux = t1
- v7.AddArg(dst)
- v7.AddArg(mem)
- v5.AddArg(v7)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v7.AddArg2(dst, mem)
+ v5.AddArg3(v6, d4, v7)
+ v3.AddArg3(v4, d3, v5)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Zero {t3} [n] p3 _))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v1.AuxInt = n
v1.Aux = t1
- v1.AddArg(dst)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg2(dst, mem)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Zero {t4} [n] p4 _)))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v3.AuxInt = n
v3.Aux = t1
- v3.AddArg(dst)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg2(dst, mem)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Zero {t5} [n] p5 _))))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = o4
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v5.AuxInt = n
v5.Aux = t1
- v5.AddArg(dst)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg2(dst, mem)
+ v3.AddArg3(v4, d3, v5)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Store {t5} (OffPtr <tt5> [o5] p5) d4 (Zero {t6} [n] p6 _)))))))
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = o2
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(d1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = o3
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(d2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t4
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = o4
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(d3)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = t5
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = o5
v6.AddArg(dst)
- v5.AddArg(v6)
- v5.AddArg(d4)
v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v7.AuxInt = n
v7.Aux = t1
- v7.AddArg(dst)
- v7.AddArg(mem)
- v5.AddArg(v7)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v7.AddArg2(dst, mem)
+ v5.AddArg3(v6, d4, v7)
+ v3.AddArg3(v4, d3, v5)
+ v1.AddArg3(v2, d2, v3)
+ v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _))
v.reset(OpMove)
v.AuxInt = s
v.Aux = t1
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(midmem)
+ v.AddArg3(dst, src, midmem)
return true
}
// match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _)))
v.reset(OpMove)
v.AuxInt = s
v.Aux = t1
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(midmem)
+ v.AddArg3(dst, src, midmem)
return true
}
// match: (Move dst src mem)
}
v.reset(OpLsh16x64)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
break
}
v.reset(OpNeg16)
v0 := b.NewValue0(v.Pos, OpLsh16x64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v1.AuxInt = log2(-c)
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
v.reset(OpMul16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c * d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpLsh32x64)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
break
}
v.reset(OpNeg32)
v0 := b.NewValue0(v.Pos, OpLsh32x64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v1.AuxInt = log2(-c)
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
v.reset(OpAdd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c * d))
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMul32, t)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(v2, x)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMul32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c * d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpAdd32F)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
break
}
v.reset(OpLsh64x64)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
break
}
v.reset(OpNeg64)
v0 := b.NewValue0(v.Pos, OpLsh64x64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v1.AuxInt = log2(-c)
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
v.reset(OpAdd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c * d
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpMul64, t)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = c
- v1.AddArg(v2)
- v1.AddArg(x)
- v.AddArg(v1)
+ v1.AddArg2(v2, x)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpMul64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c * d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpAdd64F)
- v.AddArg(x)
- v.AddArg(x)
+ v.AddArg2(x, x)
return true
}
break
}
v.reset(OpLsh8x64)
v.Type = t
- v.AddArg(n)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = log2(c)
- v.AddArg(v0)
+ v.AddArg2(n, v0)
return true
}
break
}
v.reset(OpNeg8)
v0 := b.NewValue0(v.Pos, OpLsh8x64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v1.AuxInt = log2(-c)
- v0.AddArg(v1)
+ v0.AddArg2(n, v1)
v.AddArg(v0)
return true
}
v.reset(OpMul8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c * d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpSub16)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Neg16 (Neg16 x))
v.reset(OpAdd16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpSub32)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Neg32 (Neg32 x))
v.reset(OpAdd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpSub64)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Neg64 (Neg64 x))
v.reset(OpAdd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpSub8)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Neg8 (Neg8 x))
v.reset(OpAdd8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = 1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
v.reset(OpNeq16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpNeq16)
v0 := b.NewValue0(v.Pos, OpAnd16, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst16, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst16, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpNeq16)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpEq16)
v0 := b.NewValue0(v.Pos, OpAnd16, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst16, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst16, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpNeq32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpNeq32)
v0 := b.NewValue0(v.Pos, OpAnd32, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst32, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpNeq32)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpEq32)
v0 := b.NewValue0(v.Pos, OpAnd32, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst32, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst32, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpNeq64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c - d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpNeq64)
v0 := b.NewValue0(v.Pos, OpAnd64, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpNeq64)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpEq64)
v0 := b.NewValue0(v.Pos, OpAnd64, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst64, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst64, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
v.reset(OpNeq8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
v.reset(OpNeq8)
v0 := b.NewValue0(v.Pos, OpAnd8, t)
- v0.AddArg(n)
v1 := b.NewValue0(v.Pos, OpConst8, t)
v1.AuxInt = int64(1<<uint(k) - 1)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(n, v1)
v2 := b.NewValue0(v.Pos, OpConst8, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
continue
}
v.reset(OpNeq8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
}
v.reset(OpEq8)
v0 := b.NewValue0(v.Pos, OpAnd8, t)
- v0.AddArg(x)
v1 := b.NewValue0(v.Pos, OpConst8, t)
v1.AuxInt = y
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(x, v1)
v2 := b.NewValue0(v.Pos, OpConst8, t)
v2.AuxInt = 0
- v.AddArg(v2)
+ v.AddArg2(v0, v2)
return true
}
}
}
y := v_1.Args[0]
v.reset(OpNeqB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
break
v.reset(OpNeqPtr)
v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
v.reset(OpNeqPtr)
v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr)
v0.AddArg(x)
- v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr)
v1.AddArg(y)
- v.AddArg(v1)
+ v.AddArg2(v0, v1)
return true
}
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeq64)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Eq32 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeq32)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Eq16 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeq16)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Eq8 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeq8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (EqB x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeqB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (EqPtr x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeqPtr)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Eq64F x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeq64F)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Eq32F x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpNeq32F)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Neq64 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEq64)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Neq32 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEq32)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Neq16 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEq16)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Neq8 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEq8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (NeqB x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEqB)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (NeqPtr x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEqPtr)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Neq64F x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEq64F)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Neq32F x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpEq32F)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
// match: (Not (Less64 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq64)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less32 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq32)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less16 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq16)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less8 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq8)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less64U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq64U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less32U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq32U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less16U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq16U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Less8U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLeq8U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq64 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess64)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq32 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess32)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq16 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess16)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq8 x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess8)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq64U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess64U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq32U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess32U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq16U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess16U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
// match: (Not (Leq8U x y))
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(OpLess8U)
- v.AddArg(y)
- v.AddArg(x)
+ v.AddArg2(y, x)
return true
}
return false
}
y := v_1_1
v.reset(OpOr16)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = c1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpOr16)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpOr16, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpOr16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c | d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
y := v_1_1
v.reset(OpOr32)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
v.reset(OpOr32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = c1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpOr32)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpOr32, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpOr32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c | d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
y := v_1_1
v.reset(OpOr64)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
v.reset(OpOr64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpOr64)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpOr64, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpOr64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c | d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
}
y := v_1_1
v.reset(OpOr8)
- v.AddArg(x)
- v.AddArg(y)
+ v.AddArg2(x, y)
return true
}
}
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = c1
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpOr8)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpOr8, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpOr8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c | d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
break
}
v.reset(OpAddPtr)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMul32, typ.Int)
- v0.AddArg(idx)
v1 := b.NewValue0(v.Pos, OpConst32, typ.Int)
v1.AuxInt = t.Elem().Size()
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(idx, v1)
+ v.AddArg2(ptr, v0)
return true
}
// match: (PtrIndex <t> ptr idx)
break
}
v.reset(OpAddPtr)
- v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMul64, typ.Int)
- v0.AddArg(idx)
v1 := b.NewValue0(v.Pos, OpConst64, typ.Int)
v1.AuxInt = t.Elem().Size()
- v0.AddArg(v1)
- v.AddArg(v0)
+ v0.AddArg2(idx, v1)
+ v.AddArg2(ptr, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpRsh16Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16Ux16 (Const16 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh16Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16Ux32 (Const16 [0]) _)
break
}
v.reset(OpRsh16Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 <t> [15]))
break
}
v.reset(OpRsh16Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 15
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpRsh16Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8]))
}
c := v_1.AuxInt
v.reset(OpRsh16Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16Ux8 (Const16 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x16 (Const16 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x32 (Const16 [0]) _)
break
}
v.reset(OpRsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8]))
}
c := v_1.AuxInt
v.reset(OpRsh16x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh16x8 (Const16 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh32Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux16 (Const32 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh32Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux32 (Const32 [0]) _)
break
}
v.reset(OpRsh32Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 <t> [31]))
break
}
v.reset(OpRsh32Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 31
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpRsh32Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24]))
}
c := v_1.AuxInt
v.reset(OpRsh32Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32Ux8 (Const32 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x16 (Const32 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x32 (Const32 [0]) _)
break
}
v.reset(OpRsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24]))
}
c := v_1.AuxInt
v.reset(OpRsh32x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh32x8 (Const32 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh64Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux16 (Const64 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh64Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux32 (Const64 [0]) _)
break
}
v.reset(OpRsh64Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 <t> [63]))
break
}
v.reset(OpRsh64Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 63
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpRsh64Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56]))
}
c := v_1.AuxInt
v.reset(OpRsh64Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64Ux8 (Const64 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x16 (Const64 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x32 (Const64 [0]) _)
break
}
v.reset(OpRsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56]))
}
c := v_1.AuxInt
v.reset(OpRsh64x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh64x8 (Const64 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh8Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8Ux16 (Const8 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh8Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8Ux32 (Const8 [0]) _)
break
}
v.reset(OpRsh8Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 <t> [7] ))
break
}
v.reset(OpRsh8Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = 7
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
break
}
v.reset(OpRsh8Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64)
v0.AuxInt = c1 - c2 + c3
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpRsh8Ux64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8Ux8 (Const8 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint16(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x16 (Const8 [0]) _)
}
c := v_1.AuxInt
v.reset(OpRsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint32(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x32 (Const8 [0]) _)
break
}
v.reset(OpRsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
return false
}
c := v_1.AuxInt
v.reset(OpRsh8x64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = int64(uint8(c))
- v.AddArg(v0)
+ v.AddArg2(x, v0)
return true
}
// match: (Rsh8x8 (Const8 [0]) _)
}
lo := v_0.Args[1]
v.reset(OpDiv64u)
- v.AddArg(lo)
- v.AddArg(y)
+ v.AddArg2(lo, y)
return true
}
return false
}
lo := v_0.Args[1]
v.reset(OpMod64u)
- v.AddArg(lo)
- v.AddArg(y)
+ v.AddArg2(lo, y)
return true
}
return false
v.reset(OpMove)
v.AuxInt = sz
v.Aux = t.(*types.Type).Elem()
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))
v.reset(OpMove)
v.AuxInt = sz
v.Aux = t.(*types.Type).Elem()
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (StaticCall {sym} x)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v0.AuxInt = 0
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(f0)
- v.AddArg(mem)
+ v.AddArg3(v0, f0, mem)
return true
}
// match: (Store dst (StructMake2 <t> f0 f1) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v0.AuxInt = t.FieldOff(1)
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(f1)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t.FieldType(0)
v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v2.AuxInt = 0
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(f0)
- v1.AddArg(mem)
- v.AddArg(v1)
+ v1.AddArg3(v2, f0, mem)
+ v.AddArg3(v0, f1, v1)
return true
}
// match: (Store dst (StructMake3 <t> f0 f1 f2) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo())
v0.AuxInt = t.FieldOff(2)
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(f2)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t.FieldType(1)
v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v2.AuxInt = t.FieldOff(1)
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(f1)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t.FieldType(0)
v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v4.AuxInt = 0
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(f0)
- v3.AddArg(mem)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v3.AddArg3(v4, f0, mem)
+ v1.AddArg3(v2, f1, v3)
+ v.AddArg3(v0, f2, v1)
return true
}
// match: (Store dst (StructMake4 <t> f0 f1 f2 f3) mem)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo())
v0.AuxInt = t.FieldOff(3)
v0.AddArg(dst)
- v.AddArg(v0)
- v.AddArg(f3)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t.FieldType(2)
v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo())
v2.AuxInt = t.FieldOff(2)
v2.AddArg(dst)
- v1.AddArg(v2)
- v1.AddArg(f2)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = t.FieldType(1)
v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v4.AuxInt = t.FieldOff(1)
v4.AddArg(dst)
- v3.AddArg(v4)
- v3.AddArg(f1)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = t.FieldType(0)
v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v6.AuxInt = 0
v6.AddArg(dst)
- v5.AddArg(v6)
- v5.AddArg(f0)
- v5.AddArg(mem)
- v3.AddArg(v5)
- v1.AddArg(v3)
- v.AddArg(v1)
+ v5.AddArg3(v6, f0, mem)
+ v3.AddArg3(v4, f1, v5)
+ v1.AddArg3(v2, f2, v3)
+ v.AddArg3(v0, f3, v1)
return true
}
// match: (Store {t} dst (Load src mem) mem)
v.reset(OpMove)
v.AuxInt = sizeof(t)
v.Aux = t
- v.AddArg(dst)
- v.AddArg(src)
- v.AddArg(mem)
+ v.AddArg3(dst, src, mem)
return true
}
// match: (Store {t} dst (Load src mem) (VarDef {x} mem))
v.reset(OpMove)
v.AuxInt = sizeof(t)
v.Aux = t
- v.AddArg(dst)
- v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem)
v0.Aux = x
v0.AddArg(mem)
- v.AddArg(v0)
+ v.AddArg3(dst, src, v0)
return true
}
// match: (Store _ (ArrayMake0) mem)
mem := v_2
v.reset(OpStore)
v.Aux = e.Type
- v.AddArg(dst)
- v.AddArg(e)
- v.AddArg(mem)
+ v.AddArg3(dst, e, mem)
return true
}
// match: (Store (Load (OffPtr [c] (SP)) mem) x mem)
}
v.reset(OpStore)
v.Aux = t1
- v.AddArg(op1)
- v.AddArg(d1)
v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v0.Aux = t2
- v0.AddArg(op2)
- v0.AddArg(d2)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(op2, d2, mem)
+ v.AddArg3(op1, d1, v0)
return true
}
// match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem))))
}
v.reset(OpStore)
v.Aux = t1
- v.AddArg(op1)
- v.AddArg(d1)
v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v0.Aux = t2
- v0.AddArg(op2)
- v0.AddArg(d2)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
- v1.AddArg(op3)
- v1.AddArg(d3)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg3(op3, d3, mem)
+ v0.AddArg3(op2, d2, v1)
+ v.AddArg3(op1, d1, v0)
return true
}
// match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem)))))
}
v.reset(OpStore)
v.Aux = t1
- v.AddArg(op1)
- v.AddArg(d1)
v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v0.Aux = t2
- v0.AddArg(op2)
- v0.AddArg(d2)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
- v1.AddArg(op3)
- v1.AddArg(d3)
v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v2.Aux = t4
- v2.AddArg(op4)
- v2.AddArg(d4)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v2.AddArg3(op4, d4, mem)
+ v1.AddArg3(op3, d3, v2)
+ v0.AddArg3(op2, d2, v1)
+ v.AddArg3(op1, d1, v0)
return true
}
// match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem)))
}
v.reset(OpStore)
v.Aux = t1
- v.AddArg(op1)
- v.AddArg(d1)
v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v0.Aux = t2
- v0.AddArg(op2)
- v0.AddArg(d2)
- v0.AddArg(mem)
- v.AddArg(v0)
+ v0.AddArg3(op2, d2, mem)
+ v.AddArg3(op1, d1, v0)
return true
}
// match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem))))
}
v.reset(OpStore)
v.Aux = t1
- v.AddArg(op1)
- v.AddArg(d1)
v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v0.Aux = t2
- v0.AddArg(op2)
- v0.AddArg(d2)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
- v1.AddArg(op3)
- v1.AddArg(d3)
- v1.AddArg(mem)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v1.AddArg3(op3, d3, mem)
+ v0.AddArg3(op2, d2, v1)
+ v.AddArg3(op1, d1, v0)
return true
}
// match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem)))))
}
v.reset(OpStore)
v.Aux = t1
- v.AddArg(op1)
- v.AddArg(d1)
v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v0.Aux = t2
- v0.AddArg(op2)
- v0.AddArg(d2)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = t3
- v1.AddArg(op3)
- v1.AddArg(d3)
v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v2.Aux = t4
- v2.AddArg(op4)
- v2.AddArg(d4)
- v2.AddArg(mem)
- v1.AddArg(v2)
- v0.AddArg(v1)
- v.AddArg(v0)
+ v2.AddArg3(op4, d4, mem)
+ v1.AddArg3(op3, d3, v2)
+ v0.AddArg3(op2, d2, v1)
+ v.AddArg3(op1, d1, v0)
return true
}
return false
v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo())
v1.AuxInt = t.FieldOff(int(i))
v1.AddArg(ptr)
- v0.AddArg(v1)
- v0.AddArg(mem)
+ v0.AddArg2(v1, mem)
return true
}
// match: (StructSelect [0] (IData x))
v.reset(OpAdd16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(-c))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub16 <t> (Mul16 x y) (Mul16 x z))
}
z := v_1_1
v.reset(OpMul16)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpSub16, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
}
v.reset(OpSub16)
v0 := b.NewValue0(v.Pos, OpAdd16, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
// match: (Sub16 x (Sub16 z i:(Const16 <t>)))
break
}
v.reset(OpAdd16)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub16, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
// match: (Sub16 (Const16 <t> [c]) (Sub16 x (Const16 <t> [d])))
v.reset(OpSub16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub16 (Const16 <t> [c]) (Sub16 (Const16 <t> [d]) x))
v.reset(OpAdd16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
v.reset(OpAdd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(-c))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub32 <t> (Mul32 x y) (Mul32 x z))
}
z := v_1_1
v.reset(OpMul32)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpSub32, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
}
v.reset(OpSub32)
v0 := b.NewValue0(v.Pos, OpAdd32, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
// match: (Sub32 x (Sub32 z i:(Const32 <t>)))
break
}
v.reset(OpAdd32)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub32, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
// match: (Sub32 (Const32 <t> [c]) (Sub32 x (Const32 <t> [d])))
v.reset(OpSub32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub32 (Const32 <t> [c]) (Sub32 (Const32 <t> [d]) x))
v.reset(OpAdd32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
v.reset(OpAdd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = -c
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub64 <t> (Mul64 x y) (Mul64 x z))
}
z := v_1_1
v.reset(OpMul64)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpSub64, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
}
v.reset(OpSub64)
v0 := b.NewValue0(v.Pos, OpAdd64, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
// match: (Sub64 x (Sub64 z i:(Const64 <t>)))
break
}
v.reset(OpAdd64)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub64, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
// match: (Sub64 (Const64 <t> [c]) (Sub64 x (Const64 <t> [d])))
v.reset(OpSub64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c + d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub64 (Const64 <t> [c]) (Sub64 (Const64 <t> [d]) x))
v.reset(OpAdd64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c - d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
v.reset(OpAdd8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(-c))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub8 <t> (Mul8 x y) (Mul8 x z))
}
z := v_1_1
v.reset(OpMul8)
- v.AddArg(x)
v0 := b.NewValue0(v.Pos, OpSub8, t)
- v0.AddArg(y)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(y, z)
+ v.AddArg2(x, v0)
return true
}
}
}
v.reset(OpSub8)
v0 := b.NewValue0(v.Pos, OpAdd8, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
- v.AddArg(i)
+ v0.AddArg2(x, z)
+ v.AddArg2(v0, i)
return true
}
// match: (Sub8 x (Sub8 z i:(Const8 <t>)))
break
}
v.reset(OpAdd8)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpSub8, t)
- v0.AddArg(x)
- v0.AddArg(z)
- v.AddArg(v0)
+ v0.AddArg2(x, z)
+ v.AddArg2(i, v0)
return true
}
// match: (Sub8 (Const8 <t> [c]) (Sub8 x (Const8 <t> [d])))
v.reset(OpSub8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c + d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
// match: (Sub8 (Const8 <t> [c]) (Sub8 (Const8 <t> [d]) x))
v.reset(OpAdd8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c - d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
return false
continue
}
v.reset(OpXor16)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpXor16, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpXor16)
v0 := b.NewValue0(v.Pos, OpConst16, t)
v0.AuxInt = int64(int16(c ^ d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpXor32)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpXor32, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpXor32)
v0 := b.NewValue0(v.Pos, OpConst32, t)
v0.AuxInt = int64(int32(c ^ d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpXor64)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpXor64, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpXor64)
v0 := b.NewValue0(v.Pos, OpConst64, t)
v0.AuxInt = c ^ d
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
continue
}
v.reset(OpXor8)
- v.AddArg(i)
v0 := b.NewValue0(v.Pos, OpXor8, t)
- v0.AddArg(z)
- v0.AddArg(x)
- v.AddArg(v0)
+ v0.AddArg2(z, x)
+ v.AddArg2(i, v0)
return true
}
}
v.reset(OpXor8)
v0 := b.NewValue0(v.Pos, OpConst8, t)
v0.AuxInt = int64(int8(c ^ d))
- v.AddArg(v0)
- v.AddArg(x)
+ v.AddArg2(v0, x)
return true
}
}
v.reset(OpZero)
v.AuxInt = n
v.Aux = t1
- v.AddArg(p1)
- v.AddArg(mem)
+ v.AddArg2(p1, mem)
return true
}
// match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem))
v.reset(OpZero)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
- v.AddArg(mem)
+ v.AddArg2(dst1, mem)
return true
}
// match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem)))
v.reset(OpZero)
v.AuxInt = n
v.Aux = t
- v.AddArg(dst1)
v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem)
v0.Aux = x
v0.AddArg(mem)
- v.AddArg(v0)
+ v.AddArg2(dst1, v0)
return true
}
return false
v.Args = append(v.Args, w)
w.Uses++
}
+
+//go:noinline
+func (v *Value) AddArg2(w1, w2 *Value) {
+ if v.Args == nil {
+ v.resetArgs() // use argstorage
+ }
+ v.Args = append(v.Args, w1, w2)
+ w1.Uses++
+ w2.Uses++
+}
+
+//go:noinline
+func (v *Value) AddArg3(w1, w2, w3 *Value) {
+ if v.Args == nil {
+ v.resetArgs() // use argstorage
+ }
+ v.Args = append(v.Args, w1, w2, w3)
+ w1.Uses++
+ w2.Uses++
+ w3.Uses++
+}
+
+//go:noinline
+func (v *Value) AddArg4(w1, w2, w3, w4 *Value) {
+ v.Args = append(v.Args, w1, w2, w3, w4)
+ w1.Uses++
+ w2.Uses++
+ w3.Uses++
+ w4.Uses++
+}
+
+//go:noinline
+func (v *Value) AddArg5(w1, w2, w3, w4, w5 *Value) {
+ v.Args = append(v.Args, w1, w2, w3, w4, w5)
+ w1.Uses++
+ w2.Uses++
+ w3.Uses++
+ w4.Uses++
+ w5.Uses++
+}
+
+//go:noinline
+func (v *Value) AddArg6(w1, w2, w3, w4, w5, w6 *Value) {
+ v.Args = append(v.Args, w1, w2, w3, w4, w5, w6)
+ w1.Uses++
+ w2.Uses++
+ w3.Uses++
+ w4.Uses++
+ w5.Uses++
+ w6.Uses++
+}
+
func (v *Value) AddArgs(a ...*Value) {
if v.Args == nil {
v.resetArgs() // use argstorage