(MULLWconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADDW (SLWconst <v.Type> [log2(c-1)] x) x)
// Fold ADD into MOVDaddr. Odd offsets from SB shouldn't be folded (LARL can't handle them).
-(ADDconst [c] (MOVDaddr [d] {s} x)) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
-(MOVDaddr [c] {s} (ADDconst [d] x)) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
-(ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
-(MOVDaddr [c] {s} (ADDconst [d] x)) && x.Op != OpSB && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
-(MOVDaddr [c] {s} (ADD x y)) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y)
+(ADDconst [c] (MOVDaddr [d] {s} x:(SB))) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
+(ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is20Bit(c+d) -> (MOVDaddr [c+d] {s} x)
(ADD x (MOVDaddr [c] {s} y)) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y)
(ADD (MOVDaddr [c] {s} x) y) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y)
// fold ADDconst into MOVDaddrx
-(ADDconst [c] (MOVDaddridx [d] {s} x y)) && is32Bit(c+d) -> (MOVDaddridx [c+d] {s} x y)
-(MOVDaddridx [c] {s} (ADDconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
-(MOVDaddridx [c] {s} x (ADDconst [d] y)) && is32Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
+(ADDconst [c] (MOVDaddridx [d] {s} x y)) && is20Bit(c+d) -> (MOVDaddridx [c+d] {s} x y)
+(MOVDaddridx [c] {s} (ADDconst [d] x) y) && is20Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
+(MOVDaddridx [c] {s} x (ADDconst [d] y)) && is20Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
// reverse ordering of compare instruction
(MOVDLT x y (InvertFlags cmp)) -> (MOVDGT x y cmp)
// the ADDconst get eliminated, we still have to compute the ADDconst and we now
// have potentially two live values (ptr and (ADDconst [off] ptr)) instead of one.
// Nevertheless, let's do it!
-(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
-(MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem)
-(MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem)
-(MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem)
-(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem)
-(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem)
-
-(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem)
-(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem)
-(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem)
-(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem)
-(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem)
-(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem)
+(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
+(MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem)
+(MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem)
+(MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem)
+(MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem)
+(MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem)
+(MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem)
+(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem)
+(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem)
+
+(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem)
+(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem)
+(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem)
+(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem)
+(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem)
+(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem)
// Fold constants into stores.
(MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && validValAndOff(c,off) && int64(int16(c)) == c && ptr.Op != OpSB ->
(FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
(FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
-// fold MOVDaddrs together
-(MOVDaddr [off1] {sym1} (MOVDaddr [off2] {sym2} x)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
- (MOVDaddr [off1+off2] {mergeSym(sym1,sym2)} x)
-
// MOVDaddr into MOVDaddridx
(MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
(MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
(MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB ->
(MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
-// MOVDaddridx into MOVDaddr
-(MOVDaddr [off1] {sym1} (MOVDaddridx [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
- (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
-
// Absorb InvertFlags into branches.
(LT (InvertFlags cmp) yes no) -> (GT cmp yes no)
(GT (InvertFlags cmp) yes no) -> (LT cmp yes no)
return rewriteValueS390X_OpS390XMOVDLT(v, config)
case OpS390XMOVDNE:
return rewriteValueS390X_OpS390XMOVDNE(v, config)
- case OpS390XMOVDaddr:
- return rewriteValueS390X_OpS390XMOVDaddr(v, config)
case OpS390XMOVDaddridx:
return rewriteValueS390X_OpS390XMOVDaddridx(v, config)
case OpS390XMOVDload:
func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (ADDconst [c] (MOVDaddr [d] {s} x))
+ // match: (ADDconst [c] (MOVDaddr [d] {s} x:(SB)))
// cond: ((c+d)&1 == 0) && is32Bit(c+d)
// result: (MOVDaddr [c+d] {s} x)
for {
d := v_0.AuxInt
s := v_0.Aux
x := v_0.Args[0]
+ if x.Op != OpSB {
+ break
+ }
if !(((c+d)&1 == 0) && is32Bit(c+d)) {
break
}
return true
}
// match: (ADDconst [c] (MOVDaddr [d] {s} x))
- // cond: x.Op != OpSB && is32Bit(c+d)
+ // cond: x.Op != OpSB && is20Bit(c+d)
// result: (MOVDaddr [c+d] {s} x)
for {
c := v.AuxInt
d := v_0.AuxInt
s := v_0.Aux
x := v_0.Args[0]
- if !(x.Op != OpSB && is32Bit(c+d)) {
+ if !(x.Op != OpSB && is20Bit(c+d)) {
break
}
v.reset(OpS390XMOVDaddr)
return true
}
// match: (ADDconst [c] (MOVDaddridx [d] {s} x y))
- // cond: is32Bit(c+d)
+ // cond: is20Bit(c+d)
// result: (MOVDaddridx [c+d] {s} x y)
for {
c := v.AuxInt
s := v_0.Aux
x := v_0.Args[0]
y := v_0.Args[1]
- if !(is32Bit(c + d)) {
+ if !(is20Bit(c + d)) {
break
}
v.reset(OpS390XMOVDaddridx)
func rewriteValueS390X_OpS390XFMOVDload(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
- // cond: is32Bit(off1+off2)
+ // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
+ // cond: is20Bit(off1+off2)
// result: (FMOVDload [off1+off2] {sym} ptr mem)
for {
off1 := v.AuxInt
off2 := v_0.AuxInt
ptr := v_0.Args[0]
mem := v.Args[1]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XFMOVDload)
b := v.Block
_ = b
// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is32Bit(off1+off2)
+ // cond: is20Bit(off1+off2)
// result: (FMOVDstore [off1+off2] {sym} ptr val mem)
for {
off1 := v.AuxInt
ptr := v_0.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XFMOVDstore)
func rewriteValueS390X_OpS390XFMOVSload(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
- // cond: is32Bit(off1+off2)
+ // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
+ // cond: is20Bit(off1+off2)
// result: (FMOVSload [off1+off2] {sym} ptr mem)
for {
off1 := v.AuxInt
off2 := v_0.AuxInt
ptr := v_0.Args[0]
mem := v.Args[1]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XFMOVSload)
b := v.Block
_ = b
// match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is32Bit(off1+off2)
+ // cond: is20Bit(off1+off2)
// result: (FMOVSstore [off1+off2] {sym} ptr val mem)
for {
off1 := v.AuxInt
ptr := v_0.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XFMOVSstore)
return true
}
// match: (MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem)
- // cond: is32Bit(off1+off2)
- // result: (MOVBZload [off1+off2] {sym} ptr mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVBZload [off1+off2] {sym} ptr mem)
for {
off1 := v.AuxInt
sym := v.Aux
off2 := v_0.AuxInt
ptr := v_0.Args[0]
mem := v.Args[1]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVBZload)
func rewriteValueS390X_OpS390XMOVBload(v *Value, config *Config) bool {
b := v.Block
_ = b
+ // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVBload [off1+off2] {sym} ptr mem)
+ for {
+ off1 := v.AuxInt
+ sym := v.Aux
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ off2 := v_0.AuxInt
+ ptr := v_0.Args[0]
+ mem := v.Args[1]
+ if !(is20Bit(off1 + off2)) {
+ break
+ }
+ v.reset(OpS390XMOVBload)
+ v.AuxInt = off1 + off2
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(mem)
+ return true
+ }
// match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
return true
}
// match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is32Bit(off1+off2)
+ // cond: is20Bit(off1+off2)
// result: (MOVBstore [off1+off2] {sym} ptr val mem)
for {
off1 := v.AuxInt
ptr := v_0.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVBstore)
}
return false
}
-func rewriteValueS390X_OpS390XMOVDaddr(v *Value, config *Config) bool {
- b := v.Block
- _ = b
- // match: (MOVDaddr [c] {s} (ADDconst [d] x))
- // cond: ((c+d)&1 == 0) && is32Bit(c+d)
- // result: (MOVDaddr [c+d] {s} x)
- for {
- c := v.AuxInt
- s := v.Aux
- v_0 := v.Args[0]
- if v_0.Op != OpS390XADDconst {
- break
- }
- d := v_0.AuxInt
- x := v_0.Args[0]
- if !(((c+d)&1 == 0) && is32Bit(c+d)) {
- break
- }
- v.reset(OpS390XMOVDaddr)
- v.AuxInt = c + d
- v.Aux = s
- v.AddArg(x)
- return true
- }
- // match: (MOVDaddr [c] {s} (ADDconst [d] x))
- // cond: x.Op != OpSB && is32Bit(c+d)
- // result: (MOVDaddr [c+d] {s} x)
- for {
- c := v.AuxInt
- s := v.Aux
- v_0 := v.Args[0]
- if v_0.Op != OpS390XADDconst {
- break
- }
- d := v_0.AuxInt
- x := v_0.Args[0]
- if !(x.Op != OpSB && is32Bit(c+d)) {
- break
- }
- v.reset(OpS390XMOVDaddr)
- v.AuxInt = c + d
- v.Aux = s
- v.AddArg(x)
- return true
- }
- // match: (MOVDaddr [c] {s} (ADD x y))
- // cond: x.Op != OpSB && y.Op != OpSB
- // result: (MOVDaddridx [c] {s} x y)
- for {
- c := v.AuxInt
- s := v.Aux
- v_0 := v.Args[0]
- if v_0.Op != OpS390XADD {
- break
- }
- x := v_0.Args[0]
- y := v_0.Args[1]
- if !(x.Op != OpSB && y.Op != OpSB) {
- break
- }
- v.reset(OpS390XMOVDaddridx)
- v.AuxInt = c
- v.Aux = s
- v.AddArg(x)
- v.AddArg(y)
- return true
- }
- // match: (MOVDaddr [off1] {sym1} (MOVDaddr [off2] {sym2} x))
- // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
- // result: (MOVDaddr [off1+off2] {mergeSym(sym1,sym2)} x)
- for {
- off1 := v.AuxInt
- sym1 := v.Aux
- v_0 := v.Args[0]
- if v_0.Op != OpS390XMOVDaddr {
- break
- }
- off2 := v_0.AuxInt
- sym2 := v_0.Aux
- x := v_0.Args[0]
- if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
- break
- }
- v.reset(OpS390XMOVDaddr)
- v.AuxInt = off1 + off2
- v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- return true
- }
- // match: (MOVDaddr [off1] {sym1} (MOVDaddridx [off2] {sym2} x y))
- // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
- // result: (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
- for {
- off1 := v.AuxInt
- sym1 := v.Aux
- v_0 := v.Args[0]
- if v_0.Op != OpS390XMOVDaddridx {
- break
- }
- off2 := v_0.AuxInt
- sym2 := v_0.Aux
- x := v_0.Args[0]
- y := v_0.Args[1]
- if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
- break
- }
- v.reset(OpS390XMOVDaddridx)
- v.AuxInt = off1 + off2
- v.Aux = mergeSym(sym1, sym2)
- v.AddArg(x)
- v.AddArg(y)
- return true
- }
- return false
-}
func rewriteValueS390X_OpS390XMOVDaddridx(v *Value, config *Config) bool {
b := v.Block
_ = b
// match: (MOVDaddridx [c] {s} (ADDconst [d] x) y)
- // cond: is32Bit(c+d) && x.Op != OpSB
+ // cond: is20Bit(c+d) && x.Op != OpSB
// result: (MOVDaddridx [c+d] {s} x y)
for {
c := v.AuxInt
d := v_0.AuxInt
x := v_0.Args[0]
y := v.Args[1]
- if !(is32Bit(c+d) && x.Op != OpSB) {
+ if !(is20Bit(c+d) && x.Op != OpSB) {
break
}
v.reset(OpS390XMOVDaddridx)
return true
}
// match: (MOVDaddridx [c] {s} x (ADDconst [d] y))
- // cond: is32Bit(c+d) && y.Op != OpSB
+ // cond: is20Bit(c+d) && y.Op != OpSB
// result: (MOVDaddridx [c+d] {s} x y)
for {
c := v.AuxInt
}
d := v_1.AuxInt
y := v_1.Args[0]
- if !(is32Bit(c+d) && y.Op != OpSB) {
+ if !(is20Bit(c+d) && y.Op != OpSB) {
break
}
v.reset(OpS390XMOVDaddridx)
v.AddArg(x)
return true
}
- // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
- // cond: is32Bit(off1+off2)
+ // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
+ // cond: is20Bit(off1+off2)
// result: (MOVDload [off1+off2] {sym} ptr mem)
for {
off1 := v.AuxInt
off2 := v_0.AuxInt
ptr := v_0.Args[0]
mem := v.Args[1]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVDload)
b := v.Block
_ = b
// match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is32Bit(off1+off2)
+ // cond: is20Bit(off1+off2)
// result: (MOVDstore [off1+off2] {sym} ptr val mem)
for {
off1 := v.AuxInt
ptr := v_0.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVDstore)
return true
}
// match: (MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem)
- // cond: is32Bit(off1+off2)
- // result: (MOVHZload [off1+off2] {sym} ptr mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVHZload [off1+off2] {sym} ptr mem)
for {
off1 := v.AuxInt
sym := v.Aux
off2 := v_0.AuxInt
ptr := v_0.Args[0]
mem := v.Args[1]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVHZload)
func rewriteValueS390X_OpS390XMOVHload(v *Value, config *Config) bool {
b := v.Block
_ = b
+ // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVHload [off1+off2] {sym} ptr mem)
+ for {
+ off1 := v.AuxInt
+ sym := v.Aux
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ off2 := v_0.AuxInt
+ ptr := v_0.Args[0]
+ mem := v.Args[1]
+ if !(is20Bit(off1 + off2)) {
+ break
+ }
+ v.reset(OpS390XMOVHload)
+ v.AuxInt = off1 + off2
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(mem)
+ return true
+ }
// match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
// result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem)
return true
}
// match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is32Bit(off1+off2)
+ // cond: is20Bit(off1+off2)
// result: (MOVHstore [off1+off2] {sym} ptr val mem)
for {
off1 := v.AuxInt
ptr := v_0.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVHstore)
return true
}
// match: (MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem)
- // cond: is32Bit(off1+off2)
- // result: (MOVWZload [off1+off2] {sym} ptr mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVWZload [off1+off2] {sym} ptr mem)
for {
off1 := v.AuxInt
sym := v.Aux
off2 := v_0.AuxInt
ptr := v_0.Args[0]
mem := v.Args[1]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVWZload)
func rewriteValueS390X_OpS390XMOVWload(v *Value, config *Config) bool {
b := v.Block
_ = b
+ // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem)
+ // cond: is20Bit(off1+off2)
+ // result: (MOVWload [off1+off2] {sym} ptr mem)
+ for {
+ off1 := v.AuxInt
+ sym := v.Aux
+ v_0 := v.Args[0]
+ if v_0.Op != OpS390XADDconst {
+ break
+ }
+ off2 := v_0.AuxInt
+ ptr := v_0.Args[0]
+ mem := v.Args[1]
+ if !(is20Bit(off1 + off2)) {
+ break
+ }
+ v.reset(OpS390XMOVWload)
+ v.AuxInt = off1 + off2
+ v.Aux = sym
+ v.AddArg(ptr)
+ v.AddArg(mem)
+ return true
+ }
// match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
return true
}
// match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem)
- // cond: is32Bit(off1+off2)
+ // cond: is20Bit(off1+off2)
// result: (MOVWstore [off1+off2] {sym} ptr val mem)
for {
off1 := v.AuxInt
ptr := v_0.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32Bit(off1 + off2)) {
+ if !(is20Bit(off1 + off2)) {
break
}
v.reset(OpS390XMOVWstore)