// laid out the instruction
switch inst.Op {
default: // dst, sA, sB, ...
- if len(args) == 0 {
+ switch len(args) {
+ case 0:
return op
- } else if len(args) == 1 {
+ case 1:
return fmt.Sprintf("%s %s", op, args[0])
+ case 2:
+ if inst.Op == COPY || inst.Op == PASTECC || inst.Op == FCMPO || inst.Op == FCMPU {
+ return op + " " + args[0] + "," + args[1]
+ }
+ return op + " " + args[1] + "," + args[0]
+ case 3:
+ if reverseOperandOrder(inst.Op) {
+ return op + " " + args[2] + "," + args[1] + "," + args[0]
+ }
+ case 4:
+ if reverseMiddleOps(inst.Op) {
+ return op + " " + args[1] + "," + args[3] + "," + args[2] + "," + args[0]
+ }
}
args = append(args, args[0])
return op + " " + strings.Join(args[1:], ",")
STH, STHU,
STW, STWU,
STD, STDU,
- STQ:
+ STQ, STFD, STFDU, STFS, STFSU:
return op + " " + strings.Join(args, ",")
case CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
return "ADDIS $0," + args[1] + "," + args[0]
// store instructions with index registers
case STBX, STBUX, STHX, STHUX, STWX, STWUX, STDX, STDUX,
- STHBRX, STWBRX, STDBRX, STSWX, STFSX, STFSUX, STFDX, STFDUX, STFIWX, STFDPX:
+ STHBRX, STWBRX, STDBRX, STSWX, STFIWX:
return "MOV" + op[2:len(op)-1] + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
- case STXVD2X, STXVW4X:
+ case STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
- // load instructions with index registers
- case LBZX, LBZUX, LHZX, LHZUX, LWZX, LWZUX, LDX, LDUX,
- LHBRX, LWBRX, LDBRX, LSWX, LFSX, LFSUX, LFDX, LFDUX, LFIWAX, LFIWZX:
- return "MOV" + op[1:len(op)-1] + " (" + args[2] + ")(" + args[1] + ")," + args[0]
+ case STXV:
+ return op + " " + args[0] + "," + args[1]
+
+ case STXVL, STXVLL:
+ return op + " " + args[0] + "," + args[1] + "," + args[2]
- case LDARX, LWARX, LHARX, LBARX:
+ case LWAX, LWAUX, LWZX, LHZX, LBZX, LDX, LHAX, LHAUX, LDARX, LWARX, LHARX, LBARX, LFDX, LFDUX, LFSX, LFSUX, LDBRX, LWBRX, LHBRX, LDUX, LWZUX, LHZUX, LBZUX:
+ if args[1] == "0" {
+ return op + " (" + args[2] + ")," + args[0]
+ }
return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
- case LXVD2X, LXVW4X:
+ case LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
- case DCBT, DCBTST, DCBZ, DCBST:
- return op + " (" + args[1] + ")"
+ case LXV:
+ return op + " " + args[1] + "," + args[0]
+
+ case LXVL, LXVLL:
+ return op + " " + args[1] + "," + args[2] + "," + args[0]
+
+ case DCBT, DCBTST, DCBZ, DCBST, DCBI, ICBI:
+ if args[0] == "0" || args[0] == "R0" {
+ return op + " (" + args[1] + ")"
+ }
+ return op + " (" + args[1] + ")(" + args[0] + ")"
// branch instructions needs additional handling
case BCLR:
if inst.Op == ISEL {
return fmt.Sprintf("$%d", (arg - Cond0LT))
}
- if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
+ if arg == CR0 && (strings.HasPrefix(inst.Op.String(), "cmp") || strings.HasPrefix(inst.Op.String(), "fcmp")) {
return "" // don't show cr0 for cmp instructions
} else if arg >= CR0 {
return fmt.Sprintf("CR%d", int(arg-CR0))
}
bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4]
+ if strings.HasPrefix(inst.Op.String(), "cr") {
+ return fmt.Sprintf("CR%d%s", int(arg-Cond0LT)/4, bit)
+ }
if arg <= Cond0SO {
return bit
}
return fmt.Sprintf("???(%v)", arg)
}
+func reverseMiddleOps(op Op) bool {
+ switch op {
+ case FMADD, FMADDCC, FMADDS, FMADDSCC, FMSUB, FMSUBCC, FMSUBS, FMSUBSCC, FNMADD, FNMADDCC, FNMADDS, FNMADDSCC, FNMSUB, FNMSUBCC, FNMSUBS, FNMSUBSCC, FSEL, FSELCC:
+ return true
+ }
+ return false
+}
+
+func reverseOperandOrder(op Op) bool {
+ switch op {
+ // Special case for SUBF, SUBFC: not reversed
+ case ADD, ADDC, ADDE, ADDCC, ADDCCC:
+ return true
+ case MULLW, MULLWCC, MULHW, MULHWCC, MULLD, MULLDCC, MULHD, MULHDCC, MULLWO, MULLWOCC, MULHWU, MULHWUCC, MULLDO, MULLDOCC:
+ return true
+ case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
+ return true
+ case MODUD, MODSD, MODUW, MODSW:
+ return true
+ case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC:
+ return true
+ case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
+ return true
+ case OR, ORC, AND, ANDC, XOR, NAND, EQV, NOR, ANDCC, ORCC, XORCC, EQVCC, NORCC, NANDCC:
+ return true
+ case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
+ return true
+ }
+ return false
+}
+
// revCondMap maps a conditional register bit to its inverse, if possible.
var revCondMap = map[string]string{
"LT": "GE", "GT": "LE", "EQ": "NE",
// plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics.
var plan9OpMap = map[Op]string{
- LWARX: "LWAR",
- LDARX: "LDAR",
- LHARX: "LHAR",
- LBARX: "LBAR",
- ADDI: "ADD",
- SRADI: "SRAD",
- SUBF: "SUB",
- LI: "MOVD",
- LBZ: "MOVBZ", STB: "MOVB",
+ LWARX: "LWAR",
+ LDARX: "LDAR",
+ LHARX: "LHAR",
+ LBARX: "LBAR",
+ LWAX: "MOVW",
+ LHAX: "MOVH",
+ LWAUX: "MOVWU",
+ LHAU: "MOVHU",
+ LHAUX: "MOVHU",
+ LDX: "MOVD",
+ LDUX: "MOVDU",
+ LWZX: "MOVWZ",
+ LWZUX: "MOVWZU",
+ LHZX: "MOVHZ",
+ LHZUX: "MOVHZU",
+ LBZX: "MOVBZ",
+ LBZUX: "MOVBZU",
+ LDBRX: "MOVDBR",
+ LWBRX: "MOVWBR",
+ LHBRX: "MOVHBR",
+ MCRF: "MOVFL",
+ XORI: "XOR",
+ ORI: "OR",
+ ANDICC: "ANDCC",
+ ANDC: "ANDN",
+ ADDEO: "ADDEV",
+ ADDEOCC: "ADDEVCC",
+ ADDO: "ADDV",
+ ADDOCC: "ADDVCC",
+ ADDMEO: "ADDMEV",
+ ADDMEOCC: "ADDMEVCC",
+ ADDCO: "ADDCV",
+ ADDCOCC: "ADDCVCC",
+ ADDZEO: "ADDZEV",
+ ADDZEOCC: "ADDZEVCC",
+ SUBFME: "SUBME",
+ SUBFMECC: "SUBMECC",
+ SUBFZE: "SUBZE",
+ SUBFZECC: "SUBZECC",
+ SUBFZEO: "SUBZEV",
+ SUBFZEOCC: "SUBZEVCC",
+ SUBFC: "SUBC",
+ ORC: "ORN",
+ MULLWO: "MULLWV",
+ MULLWOCC: "MULLWVCC",
+ MULLDO: "MULLDV",
+ MULLDOCC: "MULLDVCC",
+ DIVDO: "DIVDV",
+ DIVDOCC: "DIVDVCC",
+ DIVDUO: "DIVDUV",
+ DIVDUOCC: "DIVDUVCC",
+ ADDI: "ADD",
+ SRADI: "SRAD",
+ SUBF: "SUB",
+ STBCXCC: "STBCCC",
+ STWCXCC: "STWCCC",
+ STDCXCC: "STDCCC",
+ LI: "MOVD",
+ LBZ: "MOVBZ", STB: "MOVB",
LBZU: "MOVBZU", STBU: "MOVBU",
LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
LHZU: "MOVHZU", STHU: "MOVHU",
LWZU: "MOVWZU", STWU: "MOVWU",
LD: "MOVD", STD: "MOVD",
LDU: "MOVDU", STDU: "MOVDU",
+ LFD: "FMOVD", STFD: "FMOVD",
+ LFS: "FMOVS", STFS: "FMOVS",
+ LFDX: "FMOVD", STFDX: "FMOVD",
+ LFDU: "FMOVDU", STFDU: "FMOVDU",
+ LFDUX: "FMOVDU", STFDUX: "FMOVDU",
+ LFSX: "FMOVS", STFSX: "FMOVS",
+ LFSU: "FMOVSU", STFSU: "FMOVSU",
+ LFSUX: "FMOVSU", STFSUX: "FMOVSU",
CMPD: "CMP", CMPDI: "CMP",
CMPW: "CMPW", CMPWI: "CMPW",
CMPLD: "CMPU", CMPLDI: "CMPU",
DIVDEUCC
DIVDEUO
DIVDEUOCC
+ MODSD
+ MODUD
+ MODSW
+ MODUW
CMPWI
CMPDI
CMPW
VSPLTISH
VSPLTISW
VPERM
+ VPERMR
VSEL
VSL
VSLDOI
VMSUMSHS
VMSUMUHM
VMSUMUHS
+ VMSUMUDM
VSUMSWS
VSUM2SWS
VSUM4SBS
VCMPEQUWCC
VCMPEQUD
VCMPEQUDCC
+ VCMPNEB
+ VCMPNEBCC
+ VCMPNEZB
+ VCMPNEZBCC
+ VCMPNEH
+ VCMPNEHCC
+ VCMPNEZH
+ VCMPNEZHCC
+ VCMPNEW
+ VCMPNEWCC
+ VCMPNEZW
+ VCMPNEZWCC
VCMPGTSB
VCMPGTSBCC
VCMPGTSD
VPOPCNTH
VPOPCNTW
VBPERMQ
+ VBPERMD
BCDADDCC
BCDSUBCC
MTVSCR
LXVD2X
LXVDSX
LXVW4X
+ LXV
+ LXVL
+ LXVLL
STXSDX
STXSIWX
STXSSPX
STXVD2X
STXVW4X
+ STXV
+ STXVL
+ STXVLL
XSABSDP
XSADDDP
XSADDSP
XXMRGHW
XXMRGLW
XXPERMDI
+ XXPERM
XXSEL
XXSLDWI
XXSPLTW
DIVDEUCC: "divdeu.",
DIVDEUO: "divdeuo",
DIVDEUOCC: "divdeuo.",
+ MODSD: "modsd",
+ MODUD: "modud",
+ MODSW: "modsw",
+ MODUW: "moduw",
CMPWI: "cmpwi",
CMPDI: "cmpdi",
CMPW: "cmpw",
VSPLTISH: "vspltish",
VSPLTISW: "vspltisw",
VPERM: "vperm",
+ VPERMR: "vpermr",
VSEL: "vsel",
VSL: "vsl",
VSLDOI: "vsldoi",
VMSUMSHS: "vmsumshs",
VMSUMUHM: "vmsumuhm",
VMSUMUHS: "vmsumuhs",
+ VMSUMUDM: "vmsumudm",
VSUMSWS: "vsumsws",
VSUM2SWS: "vsum2sws",
VSUM4SBS: "vsum4sbs",
VCMPEQUWCC: "vcmpequw.",
VCMPEQUD: "vcmpequd",
VCMPEQUDCC: "vcmpequd.",
+ VCMPNEB: "vcmpneb",
+ VCMPNEBCC: "vcmpneb.",
+ VCMPNEZB: "vcmpnezb",
+ VCMPNEZBCC: "vcmpnezb.",
+ VCMPNEH: "vcmpneh",
+ VCMPNEHCC: "vcmpneh.",
+ VCMPNEZH: "vcmpnezh",
+ VCMPNEZHCC: "vcmpnezh.",
+ VCMPNEW: "vcmpnew",
+ VCMPNEWCC: "vcmpnew.",
+ VCMPNEZW: "vcmpnezw",
+ VCMPNEZWCC: "vcmpnezw.",
VCMPGTSB: "vcmpgtsb",
VCMPGTSBCC: "vcmpgtsb.",
VCMPGTSD: "vcmpgtsd",
VPOPCNTH: "vpopcnth",
VPOPCNTW: "vpopcntw",
VBPERMQ: "vbpermq",
+ VBPERMD: "vbpermd",
BCDADDCC: "bcdadd.",
BCDSUBCC: "bcdsub.",
MTVSCR: "mtvscr",
LXVD2X: "lxvd2x",
LXVDSX: "lxvdsx",
LXVW4X: "lxvw4x",
+ LXV: "lxv",
+ LXVL: "lxvl",
+ LXVLL: "lxvll",
STXSDX: "stxsdx",
STXSIWX: "stxsiwx",
STXSSPX: "stxsspx",
STXVD2X: "stxvd2x",
STXVW4X: "stxvw4x",
+ STXV: "stxv",
+ STXVL: "stxvl",
+ STXVLL: "stxvll",
XSABSDP: "xsabsdp",
XSADDDP: "xsadddp",
XSADDSP: "xsaddsp",
XXMRGHW: "xxmrghw",
XXMRGLW: "xxmrglw",
XXPERMDI: "xxpermdi",
+ XXPERM: "xxperm",
XXSEL: "xxsel",
XXSLDWI: "xxsldwi",
XXSPLTW: "xxspltw",
ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
+ ap_VecSReg_28_28_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {6, 5}}}
ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {MODSD, 0xfc0007fe, 0x7c000612, 0x1, // Modulo Signed Doubleword X-form (modsd RT,RA,RB)
+ [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {MODUD, 0xfc0007fe, 0x7c000212, 0x1, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB)
+ [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {MODSW, 0xfc0007fe, 0x7c000616, 0x1, // Modulo Signed Word X-form (modsw RT,RA,RB)
+ [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {MODUW, 0xfc0007fe, 0x7c000216, 0x1, // Modulo Unsigned Word X-form (moduw RT,RA,RB)
+ [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
{CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI)
[5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
{VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+ {VPERMR, 0xfc00003f, 0x1000003b, 0x0, // Vector Permute Right-indexed VA-form (vpermr VRT,VRA,VRB,VRC)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
{VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
{VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
{VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+ {VMSUMUDM, 0xfc00003f, 0x10000023, 0x0, // Vector Multiply-Sum Unsigned Doubleword Modulo VA-form (vmsumudm VRT,VRA,VRB,VRC)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
{VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VCMPEQUDCC, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEB, 0xfc0007ff, 0x10000007, 0x0, // Vector Compare Not Equal Byte VX-form (vcmpneb VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEBCC, 0xfc0007ff, 0x10000407, 0x0, // Vector Compare Not Equal Byte VX-form (vcmpneb. VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEZB, 0xfc0007ff, 0x10000107, 0x0, // Vector Compare Not Equal or Zero Byte VX-form (vcmpnezb VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEZBCC, 0xfc0007ff, 0x10000507, 0x0, // Vector Compare Not Equal or Zero Byte VX-form (vcmpnezb. VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEH, 0xfc0007ff, 0x10000047, 0x0, // Vector Compare Not Equal Halfword VX-form (vcmpneh VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEHCC, 0xfc0007ff, 0x10000447, 0x0, // Vector Compare Not Equal Halfword VX-form (vcmpneh. VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEZH, 0xfc0007ff, 0x10000147, 0x0, // Vector Compare Not Equal or Zero Halfword VX-form (vcmpnezh VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEZHCC, 0xfc0007ff, 0x10000547, 0x0, // Vector Compare Not Equal or Zero Halfword VX-form (vcmpnezh. VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEW, 0xfc0007ff, 0x10000087, 0x0, // Vector Compare Not Equal Word VX-form (vcmpnew VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEWCC, 0xfc0007ff, 0x10000487, 0x0, // Vector Compare Not Equal Word VX-form (vcmpnew. VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEZW, 0xfc0007ff, 0x10000187, 0x0, // Vector Compare Not Equal or Zero Word VX-form (vcmpnezw VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VCMPNEZWCC, 0xfc0007ff, 0x10000587, 0x0, // Vector Compare Not Equal or Zero Word VX-form (vcmpnezw. VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VCMPGTSBCC, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+ {VBPERMD, 0xfc0007ff, 0x100005cc, 0x0, // Vector Bit Permute Doubleword VX-form (vbpermd VRT,VRA,VRB)
+ [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{BCDADDCC, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
{BCDSUBCC, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {LXV, 0xfc000007, 0xf4000001, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
+ [5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+ {LXVL, 0xfc0007fe, 0x7c00021a, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
+ [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB)
+ [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {STXV, 0xfc000007, 0xf4000005, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
+ [5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+ {STXVL, 0xfc0007fe, 0x7c00031a, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
+ [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+ {STXVLL, 0xfc0007fe, 0x7c00035a, 0x0, // Store VSX Vector Left-justified with Length X-form (stxvll XS,RA,RB)
+ [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB)
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
{XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
{XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM)
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
+ {XXPERM, 0xfc0007f8, 0xf00000d0, 0x0, // VSX Permute XX3-form (xxperm XT,XA,XB)
+ [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
{XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC)
[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}},
{XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW)