args = append(args, "-compiling-runtime")
}
+ if cfg.Goarch == "386" {
+ // Define GO386_value from cfg.GO386.
+ args = append(args, "-D", "GO386_"+cfg.GO386)
+ }
+
if cfg.Goarch == "mips" || cfg.Goarch == "mipsle" {
// Define GOMIPS_value from cfg.GOMIPS.
args = append(args, "-D", "GOMIPS_"+cfg.GOMIPS)
// Offsets into internal/cpu records for use in assembly.
const (
- offsetX86HasSSE2 = unsafe.Offsetof(cpu.X86.HasSSE2)
offsetX86HasSSE42 = unsafe.Offsetof(cpu.X86.HasSSE42)
offsetX86HasAVX2 = unsafe.Offsetof(cpu.X86.HasAVX2)
offsetX86HasPOPCNT = unsafe.Offsetof(cpu.X86.HasPOPCNT)
JEQ allsame
CMPL BP, $4
JB small
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE mediumloop
+#ifdef GO386_softfloat
+ JMP mediumloop
+#endif
largeloop:
CMPL BP, $16
JB mediumloop
hugeloop:
CMPL BX, $64
JB bigloop
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE bigloop
+#ifdef GO386_softfloat
+ JMP bigloop
+#endif
MOVOU (SI), X0
MOVOU (DI), X1
MOVOU 16(SI), X2
HasPCLMULQDQ bool
HasPOPCNT bool
HasRDTSCP bool
- HasSSE2 bool
HasSSE3 bool
HasSSSE3 bool
HasSSE41 bool
+++ /dev/null
-// Copyright 2018 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-package cpu
-
-const GOARCH = "386"
+++ /dev/null
-// Copyright 2018 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-package cpu
-
-const GOARCH = "amd64"
{Name: "sse41", Feature: &X86.HasSSE41},
{Name: "sse42", Feature: &X86.HasSSE42},
{Name: "ssse3", Feature: &X86.HasSSSE3},
-
- // These capabilities should always be enabled on amd64:
- {Name: "sse2", Feature: &X86.HasSSE2, Required: GOARCH == "amd64"},
}
maxID, _, _, _ := cpuid(0, 0)
maxExtendedFunctionInformation, _, _, _ = cpuid(0x80000000, 0)
- _, _, ecx1, edx1 := cpuid(1, 0)
- X86.HasSSE2 = isSet(edx1, cpuid_SSE2)
+ _, _, ecx1, _ := cpuid(1, 0)
X86.HasSSE3 = isSet(ecx1, cpuid_SSE3)
X86.HasPCLMULQDQ = isSet(ecx1, cpuid_PCLMULQDQ)
import (
. "internal/cpu"
"os"
- "runtime"
"testing"
)
}
}
-func TestDisableSSE2(t *testing.T) {
- runDebugOptionsTest(t, "TestSSE2DebugOption", "cpu.sse2=off")
-}
-
-func TestSSE2DebugOption(t *testing.T) {
- MustHaveDebugOptionsSupport(t)
-
- if os.Getenv("GODEBUG") != "cpu.sse2=off" {
- t.Skipf("skipping test: GODEBUG=cpu.sse2=off not set")
- }
-
- want := runtime.GOARCH != "386" // SSE2 can only be disabled on 386.
- if got := X86.HasSSE2; got != want {
- t.Errorf("X86.HasSSE2 on %s expected %v, got %v", runtime.GOARCH, want, got)
- }
-}
-
func TestDisableSSE3(t *testing.T) {
runDebugOptionsTest(t, "TestSSE3DebugOption", "cpu.sse3=off")
}
// When no SSE2 support is present do not enforce any serialization
// since using CPUID to serialize the instruction stream is
// very costly.
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE rdtsc
+#ifdef GO386_softfloat
+ JMP rdtsc // no fence instructions available
+#endif
CMPB internal∕cpu·X86+const_offsetX86HasRDTSCP(SB), $1
JNE fences
// Instruction stream serializing RDTSCP is supported.
offsetX86HasAVX2 = unsafe.Offsetof(cpu.X86.HasAVX2)
offsetX86HasERMS = unsafe.Offsetof(cpu.X86.HasERMS)
offsetX86HasRDTSCP = unsafe.Offsetof(cpu.X86.HasRDTSCP)
- offsetX86HasSSE2 = unsafe.Offsetof(cpu.X86.HasSSE2)
offsetARMHasIDIVA = unsafe.Offsetof(cpu.ARM.HasIDIVA)
JBE _5through8
CMPL BX, $16
JBE _9through16
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE nosse2
+#ifdef GO386_softfloat
+ JMP nosse2
+#endif
PXOR X0, X0
CMPL BX, $32
JBE _17through32
JBE move_5through8
CMPL BX, $16
JBE move_9through16
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE nosse2
+#ifdef GO386_softfloat
+ JMP nosse2
+#endif
CMPL BX, $32
JBE move_17through32
CMPL BX, $64
l.add("MOVL", reg, 4)
}
+ softfloat := "GO386_softfloat"
+
// Save SSE state only if supported.
lSSE := layout{stack: l.stack, sp: "SP"}
for i := 0; i < 8; i++ {
p("ADJSP $%d", lSSE.stack)
p("NOP SP")
l.save()
- p("CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1\nJNE nosse")
+ p("#ifndef %s", softfloat)
lSSE.save()
- label("nosse:")
+ p("#endif")
p("CALL ·asyncPreempt2(SB)")
- p("CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1\nJNE nosse2")
+ p("#ifndef %s", softfloat)
lSSE.restore()
- label("nosse2:")
+ p("#endif")
l.restore()
p("ADJSP $%d", -lSSE.stack)
MOVL BP, 16(SP)
MOVL SI, 20(SP)
MOVL DI, 24(SP)
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE nosse
+ #ifndef GO386_softfloat
MOVUPS X0, 28(SP)
MOVUPS X1, 44(SP)
MOVUPS X2, 60(SP)
MOVUPS X5, 108(SP)
MOVUPS X6, 124(SP)
MOVUPS X7, 140(SP)
-nosse:
+ #endif
CALL ·asyncPreempt2(SB)
- CMPB internal∕cpu·X86+const_offsetX86HasSSE2(SB), $1
- JNE nosse2
+ #ifndef GO386_softfloat
MOVUPS 140(SP), X7
MOVUPS 124(SP), X6
MOVUPS 108(SP), X5
MOVUPS 60(SP), X2
MOVUPS 44(SP), X1
MOVUPS 28(SP), X0
-nosse2:
+ #endif
MOVL 24(SP), DI
MOVL 20(SP), SI
MOVL 16(SP), BP