gc.Thearch.REGRETURN = arm64.REG_R0
gc.Thearch.REGMIN = arm64.REG_R0
gc.Thearch.REGMAX = arm64.REG_R31
+ gc.Thearch.REGZERO = arm64.REGZERO
gc.Thearch.FREGMIN = arm64.REG_F0
gc.Thearch.FREGMAX = arm64.REG_F31
gc.Thearch.MAXWIDTH = MAXWIDTH
}
} else {
// When zeroing, prepare a register containing zero.
- var tmp Node
- Nodconst(&tmp, nl.Type, 0)
+ if Thearch.REGZERO != 0 {
+ // cpu has a dedicated zero register
+ Nodreg(&nodr, Types[TUINT], Thearch.REGZERO)
+ } else {
+ // no dedicated zero register
+ var tmp Node
+ Nodconst(&tmp, nl.Type, 0)
- Regalloc(&nodr, Types[TUINT], nil)
- Thearch.Gmove(&tmp, &nodr)
- defer Regfree(&nodr)
+ Regalloc(&nodr, Types[TUINT], nil)
+ Thearch.Gmove(&tmp, &nodr)
+ defer Regfree(&nodr)
+ }
}
// nl and nr are 'cadable' which basically means they are names (variables) now.