return &inst{0x53, 0x0, 0x0, 0x0, 384, 0xc}
case AFENCE:
return &inst{0xf, 0x0, 0x0, 0x0, 0, 0x0}
- case AFENCETSO:
- return &inst{0xf, 0x0, 0x0, 0x13, -1997, 0x41}
case AFEQD:
return &inst{0x53, 0x2, 0x0, 0x0, -1504, 0x51}
case AFEQQ:
return &inst{0x53, 0x0, 0x0, 0x0, 256, 0x8}
case AFMVDX:
return &inst{0x53, 0x0, 0x0, 0x0, -224, 0x79}
- case AFMVSX:
- return &inst{0x53, 0x0, 0x0, 0x0, -256, 0x78}
case AFMVWX:
return &inst{0x53, 0x0, 0x0, 0x0, -256, 0x78}
case AFMVXD:
return &inst{0x53, 0x0, 0x0, 0x0, -480, 0x71}
- case AFMVXS:
- return &inst{0x53, 0x0, 0x0, 0x0, -512, 0x70}
case AFMVXW:
return &inst{0x53, 0x0, 0x0, 0x0, -512, 0x70}
case AFNMADDD:
return &inst{0x4b, 0x0, 0x0, 0x0, 96, 0x3}
case AFNMSUBS:
return &inst{0x4b, 0x0, 0x0, 0x0, 0, 0x0}
- case AFRCSR:
- return &inst{0x73, 0x2, 0x0, 0x3, 3, 0x0}
- case AFRFLAGS:
- return &inst{0x73, 0x2, 0x0, 0x1, 1, 0x0}
- case AFRRM:
- return &inst{0x73, 0x2, 0x0, 0x2, 2, 0x0}
- case AFSCSR:
- return &inst{0x73, 0x1, 0x0, 0x3, 3, 0x0}
case AFSD:
return &inst{0x27, 0x3, 0x0, 0x0, 0, 0x0}
- case AFSFLAGS:
- return &inst{0x73, 0x1, 0x0, 0x1, 1, 0x0}
- case AFSFLAGSI:
- return &inst{0x73, 0x5, 0x0, 0x1, 1, 0x0}
case AFSGNJD:
return &inst{0x53, 0x0, 0x0, 0x0, 544, 0x11}
case AFSGNJQ:
return &inst{0x53, 0x0, 0x0, 0x0, 1504, 0x2f}
case AFSQRTS:
return &inst{0x53, 0x0, 0x0, 0x0, 1408, 0x2c}
- case AFSRM:
- return &inst{0x73, 0x1, 0x0, 0x2, 2, 0x0}
- case AFSRMI:
- return &inst{0x73, 0x5, 0x0, 0x2, 2, 0x0}
case AFSUBD:
return &inst{0x53, 0x0, 0x0, 0x0, 160, 0x5}
case AFSUBQ:
return &inst{0x13, 0x6, 0x0, 0x0, 0, 0x0}
case AORN:
return &inst{0x33, 0x6, 0x0, 0x0, 1024, 0x20}
- case APAUSE:
- return &inst{0xf, 0x0, 0x0, 0x10, 16, 0x0}
- case ARDCYCLE:
- return &inst{0x73, 0x2, 0x0, 0x0, -1024, 0x60}
- case ARDCYCLEH:
- return &inst{0x73, 0x2, 0x0, 0x0, -896, 0x64}
- case ARDINSTRET:
- return &inst{0x73, 0x2, 0x0, 0x2, -1022, 0x60}
- case ARDINSTRETH:
- return &inst{0x73, 0x2, 0x0, 0x2, -894, 0x64}
- case ARDTIME:
- return &inst{0x73, 0x2, 0x0, 0x1, -1023, 0x60}
- case ARDTIMEH:
- return &inst{0x73, 0x2, 0x0, 0x1, -895, 0x64}
case AREM:
return &inst{0x33, 0x6, 0x0, 0x0, 32, 0x1}
case AREMU:
return &inst{0x3b, 0x5, 0x0, 0x0, 1536, 0x30}
case ASB:
return &inst{0x23, 0x0, 0x0, 0x0, 0, 0x0}
- case ASBREAK:
- return &inst{0x73, 0x0, 0x0, 0x1, 1, 0x0}
case ASCD:
return &inst{0x2f, 0x3, 0x0, 0x0, 384, 0xc}
case ASCW:
return &inst{0x2f, 0x2, 0x0, 0x0, 384, 0xc}
- case ASCALL:
- return &inst{0x73, 0x0, 0x0, 0x0, 0, 0x0}
case ASD:
return &inst{0x23, 0x3, 0x0, 0x0, 0, 0x0}
case ASEXTB:
case obj.AUNDEF:
p.As = AEBREAK
+ case AFMVXS:
+ // FMVXS is the old name for FMVXW.
+ p.As = AFMVXW
+
+ case AFMVSX:
+ // FMVSX is the old name for FMVWX.
+ p.As = AFMVWX
+
case ASCALL:
// SCALL is the old name for ECALL.
p.As = AECALL
ALD & obj.AMask: iIIEncoding,
ASD & obj.AMask: sIEncoding,
+ // 7.1: CSR Instructions
+ ACSRRS & obj.AMask: iIIEncoding,
+
// 7.1: Multiplication Operations
AMUL & obj.AMask: rIIIEncoding,
AMULH & obj.AMask: rIIIEncoding,
AAMOMINUW & obj.AMask: rIIIEncoding,
AAMOMINUD & obj.AMask: rIIIEncoding,
- // 10.1: Base Counters and Timers
- ARDCYCLE & obj.AMask: iIIEncoding,
- ARDTIME & obj.AMask: iIIEncoding,
- ARDINSTRET & obj.AMask: iIIEncoding,
-
// 11.5: Single-Precision Load and Store Instructions
AFLW & obj.AMask: iFEncoding,
AFSW & obj.AMask: sFEncoding,
AFSGNJS & obj.AMask: rFFFEncoding,
AFSGNJNS & obj.AMask: rFFFEncoding,
AFSGNJXS & obj.AMask: rFFFEncoding,
- AFMVXS & obj.AMask: rFIEncoding,
- AFMVSX & obj.AMask: rIFEncoding,
AFMVXW & obj.AMask: rFIEncoding,
AFMVWX & obj.AMask: rIFEncoding,
ins.funct7 = 3
ins.rd, ins.rs1, ins.rs2 = uint32(p.RegTo2), uint32(p.To.Reg), uint32(p.From.Reg)
- case AECALL, AEBREAK, ARDCYCLE, ARDTIME, ARDINSTRET:
+ case AECALL, AEBREAK:
insEnc := encode(p.As)
if p.To.Type == obj.TYPE_NONE {
ins.rd = REG_ZERO
ins.rs1 = REG_ZERO
ins.imm = insEnc.csr
+ case ARDCYCLE, ARDTIME, ARDINSTRET:
+ ins.as = ACSRRS
+ if p.To.Type == obj.TYPE_NONE {
+ ins.rd = REG_ZERO
+ }
+ ins.rs1 = REG_ZERO
+ switch p.As {
+ case ARDCYCLE:
+ ins.imm = -1024
+ case ARDTIME:
+ ins.imm = -1023
+ case ARDINSTRET:
+ ins.imm = -1022
+ }
+
case AFENCE:
ins.rd, ins.rs1, ins.rs2 = REG_ZERO, REG_ZERO, obj.REG_NONE
ins.imm = 0x0ff