cmd/asm: remove X27 and S11 register names on riscv64

The X27 register (known as S11 via its ABI name) is the g register on riscv64.
Prevent assembly from referring to it by either of these names.

Change-Id: Iba389eb8e44e097c0142c5b3d92e72bcae8a244a
Reviewed-on: https://go-review.googlesource.com/c/go/+/265519
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>

diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go
index 2e5d0ff9911d3000e7162516c2fd02568dd487a9..a62e55191e6898d43efc4aef5030bf9df5aea1ac 100644 (file)
--- a/src/cmd/asm/internal/arch/arch.go
+++ b/src/cmd/asm/internal/arch/arch.go
@@ -535,6 +535,9 @@ func archRISCV64() *Arch {
 
        // Standard register names.
        for i := riscv.REG_X0; i <= riscv.REG_X31; i++ {
+               if i == riscv.REG_G {
+                       continue
+               }
                name := fmt.Sprintf("X%d", i-riscv.REG_X0)
                register[name] = int16(i)
        }
@@ -571,7 +574,7 @@ func archRISCV64() *Arch {
        register["S8"] = riscv.REG_S8
        register["S9"] = riscv.REG_S9
        register["S10"] = riscv.REG_S10
-       register["S11"] = riscv.REG_S11
+       // Skip S11 as it is the g register.
        register["T3"] = riscv.REG_T3
        register["T4"] = riscv.REG_T4
        register["T5"] = riscv.REG_T5