p.Reg = v.Args[0].Reg()
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
- case ssa.OpARM64LoweredMuluhilo:
- r0 := v.Args[0].Reg()
- r1 := v.Args[1].Reg()
- p := s.Prog(arm64.AUMULH)
- p.From.Type = obj.TYPE_REG
- p.From.Reg = r1
- p.Reg = r0
- p.To.Type = obj.TYPE_REG
- p.To.Reg = v.Reg0()
- p1 := s.Prog(arm64.AMUL)
- p1.From.Type = obj.TYPE_REG
- p1.From.Reg = r1
- p1.Reg = r0
- p1.To.Type = obj.TYPE_REG
- p1.To.Reg = v.Reg1()
case ssa.OpARM64LoweredAtomicExchange64,
ssa.OpARM64LoweredAtomicExchange32:
// LDAXR (Rarg0), Rout
(Hmul64u ...) => (UMULH ...)
(Hmul32 x y) => (SRAconst (MULL <typ.Int64> x y) [32])
(Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
-(Mul64uhilo ...) => (LoweredMuluhilo ...)
+(Select0 (Mul64uhilo x y)) => (UMULH x y)
+(Select1 (Mul64uhilo x y)) => (MUL x y)
(Div64 [false] x y) => (DIV x y)
(Div64u ...) => (UDIV ...)
// runtime/internal/math.MulUintptr intrinsics
(Select0 (Mul64uover x y)) => (MUL x y)
-(Select1 (Mul64uover x y)) => (NotEqual (CMPconst (UMULH <typ.UInt64> x y) [0]))
\ No newline at end of file
+(Select1 (Mul64uover x y)) => (NotEqual (CMPconst (UMULH <typ.UInt64> x y) [0]))
gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}}
gp2flags1flags = regInfo{inputs: []regMask{gp, gp, 0}, outputs: []regMask{gp, 0}}
gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
- gp22 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}}
gp31 = regInfo{inputs: []regMask{gpg, gpg, gpg}, outputs: []regMask{gp}}
gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
{name: "EON", argLength: 2, reg: gp21, asm: "EON"}, // arg0 ^ ^arg1
{name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0 | ^arg1
- {name: "LoweredMuluhilo", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, returns (hi, lo)
-
// unary ops
{name: "MVN", argLength: 1, reg: gp11, asm: "MVN"}, // ^arg0
{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0
OpARM64BIC
OpARM64EON
OpARM64ORN
- OpARM64LoweredMuluhilo
OpARM64MVN
OpARM64NEG
OpARM64NEGSflags
},
},
},
- {
- name: "LoweredMuluhilo",
- argLen: 2,
- resultNotInArgs: true,
- reg: regInfo{
- inputs: []inputInfo{
- {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
- {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
- },
- outputs: []outputInfo{
- {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
- {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
- },
- },
- },
{
name: "MVN",
argLen: 1,
case OpMul64F:
v.Op = OpARM64FMULD
return true
- case OpMul64uhilo:
- v.Op = OpARM64LoweredMuluhilo
- return true
case OpMul8:
v.Op = OpARM64MULW
return true
v_0 := v.Args[0]
b := v.Block
typ := &b.Func.Config.Types
+ // match: (Select0 (Mul64uhilo x y))
+ // result: (UMULH x y)
+ for {
+ if v_0.Op != OpMul64uhilo {
+ break
+ }
+ y := v_0.Args[1]
+ x := v_0.Args[0]
+ v.reset(OpARM64UMULH)
+ v.AddArg2(x, y)
+ return true
+ }
// match: (Select0 (Add64carry x y c))
// result: (Select0 <typ.UInt64> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c))))
for {
v_0 := v.Args[0]
b := v.Block
typ := &b.Func.Config.Types
+ // match: (Select1 (Mul64uhilo x y))
+ // result: (MUL x y)
+ for {
+ if v_0.Op != OpMul64uhilo {
+ break
+ }
+ y := v_0.Args[1]
+ x := v_0.Args[0]
+ v.reset(OpARM64MUL)
+ v.AddArg2(x, y)
+ return true
+ }
// match: (Select1 (Add64carry x y c))
// result: (ADCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c)))))
for {
return bits.Mul64(x, y)
}
+func Mul64HiOnly(x, y uint64) uint64 {
+ // arm64:"UMULH",-"MUL"
+ hi, _ := bits.Mul64(x, y)
+ return hi
+}
+
+func Mul64LoOnly(x, y uint64) uint64 {
+ // arm64:"MUL",-"UMULH"
+ _, lo := bits.Mul64(x, y)
+ return lo
+}
+
// --------------- //
// bits.Div* //
// --------------- //