p1.To.Reg = ah.Reg
p1.To.Offset = int64(al.Reg)
- //print("%P\n", p1);
+ //print("%v\n", p1);
// bl * ch + ah -> ah
p1 = gins(arm.AMULA, nil, nil)
p1.To.Reg = ah.Reg
p1.To.Offset = int64(ah.Reg)
- //print("%P\n", p1);
+ //print("%v\n", p1);
// bh * cl + ah -> ah
p1 = gins(arm.AMULA, nil, nil)
p1.To.Reg = ah.Reg
p1.To.Offset = int64(ah.Reg)
- //print("%P\n", p1);
+ //print("%v\n", p1);
gc.Regfree(&bh)
p.To.Offset = 4
p.Scond |= arm.C_PBIT
- //print("1. %P\n", p);
+ //print("1. %v\n", p);
q--
}
}
p.To.Offset = 1
p.Scond |= arm.C_PBIT
- //print("2. %P\n", p);
+ //print("2. %v\n", p);
c--
}
p1.From.Offset = 2<<5 | 31<<7 | int64(r1.Reg)&15 // r1->31
p1.From.Reg = 0
- //print("gmove: %P\n", p1);
+ //print("gmove: %v\n", p1);
gins(arm.AMOVW, &r1, &tlo)
gins(arm.AMOVW, &r2, &thi)
Fatal("fnil %v / %v", p, p.To.Val.(*obj.Prog))
}
if f1 == f {
- //fatal("self loop %P", p);
+ //fatal("self loop %v", p);
continue
}
}
if(f1->p1 == nil && f1->p2 == nil) {
- print("lost pred for %P\n", fcheck->prog);
+ print("lost pred for %v\n", fcheck->prog);
for(f1=f0; f1!=nil; f1=f1->p1) {
thearch.proginfo(&info, f1->prog);
- print("\t%P %d %d %D %D\n", r1->prog, info.flags&RightWrite, thearch.sameaddr(&f1->prog->to, &fcheck->prog->from), &f1->prog->to, &fcheck->prog->from);
+ print("\t%v %d %d %D %D\n", r1->prog, info.flags&RightWrite, thearch.sameaddr(&f1->prog->to, &fcheck->prog->from), &f1->prog->to, &fcheck->prog->from);
}
fatal("lost pred trail");
}
bflag = 1
}
- //print("%P pc changed %d to %d in iter. %d\n", p, opc, (int32)p->pc, times);
+ //print("%v pc changed %d to %d in iter. %d\n", p, opc, (int32)p->pc, times);
c = int32(p.Pc + int64(m))
if m%4 != 0 || p.Pc%4 != 0 {
mangle(pn)
}
if ctxt.Enforce_data_order != 0 && off < int32(len(s.P)) {
- ctxt.Diag("data out of order (already have %d)\n%P", len(s.P), p)
+ ctxt.Diag("data out of order (already have %d)\n%v", len(s.P), p)
}
Symgrow(ctxt, s, int64(off+siz))
switch int(p.To.Type) {
default:
- ctxt.Diag("bad data: %P", p)
+ ctxt.Diag("bad data: %v", p)
case TYPE_FCONST:
switch siz {
var f *LSym
linkgetline(ctxt, p.Lineno, &f, &l)
if f == nil {
- // print("getline failed for %s %P\n", ctxt->cursym->name, p);
+ // print("getline failed for %s %v\n", ctxt->cursym->name, p);
return oldval
}
a2 = C_REG
}
- //print("oplook %P %d %d %d %d\n", p, a1, a2, a3, a4);
+ //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4);
r0 := p.As & obj.AMask
o := oprange[r0].start
o4 := uint32(0)
o5 := uint32(0)
- //print("%P => case %d\n", p, o->type);
+ //print("%v => case %d\n", p, o->type);
switch o.type_ {
default:
ctxt.Diag("unknown type %d", o.type_)
* qc has already complained.
*
if(v < 0 || v > 31)
- ctxt->diag("illegal shift %ld\n%P", v, p);
+ ctxt->diag("illegal shift %ld\n%v", v, p);
*/
if v < 0 {
v = 0
l = int(v >> 32)
if l == 0 && rel.Siz != 8 {
//p->mark |= 0100;
- //print("zero: %llux %P\n", v, p);
+ //print("zero: %llux %v\n", v, p);
ctxt.Rexflag &^= (0x40 | Rxw)
ctxt.Rexflag |= regrex[p.To.Reg] & Rxb
} else if l == -1 && uint64(v)&(uint64(1)<<31) != 0 { /* sign extend */
//p->mark |= 0100;
- //print("sign: %llux %P\n", v, p);
+ //print("sign: %llux %v\n", v, p);
ctxt.Andptr[0] = 0xc7
ctxt.Andptr = ctxt.Andptr[1:]
asmando(ctxt, p, &p.To, 0)
put4(ctxt, int32(v)) /* need all 8 */
} else {
- //print("all: %llux %P\n", v, p);
+ //print("all: %llux %v\n", v, p);
ctxt.Rexflag |= regrex[p.To.Reg] & Rxb
ctxt.Andptr[0] = byte(op + reg[p.To.Reg])