VFWREDUSUMVS V1, V2, V3 // d79120c6
VFWREDUSUMVS V1, V2, V0, V3 // d79120c4
+ // 31.15: Vector Mask Instructions
+ VMANDMM V1, V2, V3 // d7a12066
+ VMNANDMM V1, V2, V3 // d7a12076
+ VMANDNMM V1, V2, V3 // d7a12062
+ VMXORMM V1, V2, V3 // d7a1206e
+ VMORMM V1, V2, V3 // d7a1206a
+ VMNORMM V1, V2, V3 // d7a1207a
+ VMORNMM V1, V2, V3 // d7a12072
+ VMXNORMM V1, V2, V3 // d7a1207e
+ VMMVM V2, V3 // d7212166
+ VMCLRM V3 // d7a1316e
+ VMSETM V3 // d7a1317e
+ VMNOTM V2, V3 // d7212176
+ VCPOPM V2, X10 // 57252842
+ VCPOPM V2, V0, X10 // 57252840
+ VFIRSTM V2, X10 // 57a52842
+ VFIRSTM V2, V0, X10 // 57a52840
+ VMSBFM V2, V3 // d7a12052
+ VMSBFM V2, V0, V3 // d7a12050
+ VMSIFM V2, V3 // d7a12152
+ VMSIFM V2, V0, V3 // d7a12150
+ VMSOFM V2, V3 // d7212152
+ VMSOFM V2, V0, V3 // d7212150
+ VIOTAM V2, V3 // d7212852
+ VIOTAM V2, V0, V3 // d7212850
+ VIDV V3 // d7a10852
+ VIDV V0, V3 // d7a10850
+
//
// Privileged ISA
//
VFREDMINVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFWREDOSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFWREDUSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMANDMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMNANDMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMANDNMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMXORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMNORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMORNMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMXNORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
+ VMMVM V3, X10 // ERROR "expected vector register in vd position"
+ VMNOTM V3, X10 // ERROR "expected vector register in vd position"
+ VCPOPM V2, V1 // ERROR "expected integer register in rd position"
+ VCPOPM X11, X10 // ERROR "expected vector register in vs2 position"
+ VFIRSTM V2, V1 // ERROR "expected integer register in rd position"
+ VFIRSTM X11, X10 // ERROR "expected vector register in vs2 position"
+ VMSBFM X10, V3 // ERROR "expected vector register in vs2 position"
+ VMSIFM X10, V3 // ERROR "expected vector register in vs2 position"
+ VMSOFM X10, V3 // ERROR "expected vector register in vs2 position"
+ VIOTAM X10, V3 // ERROR "expected vector register in vs2 position"
+ VIDV X10 // ERROR "expected vector register in vd position"
RET
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
}
+func validateRVI(ctxt *obj.Link, ins *instruction) {
+ wantIntReg(ctxt, ins, "rd", ins.rd)
+ wantNoneReg(ctxt, ins, "rs1", ins.rs1)
+ wantVectorReg(ctxt, ins, "vs2", ins.rs2)
+ wantNoneReg(ctxt, ins, "rs3", ins.rs3)
+}
+
func validateRVIV(ctxt *obj.Link, ins *instruction) {
wantVectorReg(ctxt, ins, "vd", ins.rd)
wantIntReg(ctxt, ins, "rs1", ins.rs1)
return encodeR(ins.as, regF(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7)
}
+func encodeRVI(ins *instruction) uint32 {
+ return encodeR(ins.as, 0, regV(ins.rs2), regI(ins.rd), ins.funct3, ins.funct7)
+}
+
func encodeRVIV(ins *instruction) uint32 {
return encodeR(ins.as, regI(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7)
}
rIFEncoding = encoding{encode: encodeRIF, validate: validateRIF, length: 4}
rFFEncoding = encoding{encode: encodeRFF, validate: validateRFF, length: 4}
rVFVEncoding = encoding{encode: encodeRVFV, validate: validateRVFV, length: 4}
+ rVIEncoding = encoding{encode: encodeRVI, validate: validateRVI, length: 4}
rVIVEncoding = encoding{encode: encodeRVIV, validate: validateRVIV, length: 4}
rVVEncoding = encoding{encode: encodeRVV, validate: validateRVV, length: 4}
rVViEncoding = encoding{encode: encodeRVVi, validate: validateRVVi, length: 4}
AVFWREDOSUMVS & obj.AMask: {enc: rVVVEncoding},
AVFWREDUSUMVS & obj.AMask: {enc: rVVVEncoding},
+ // 31.15: Vector Mask Instructions
+ AVMANDMM & obj.AMask: {enc: rVVVEncoding},
+ AVMNANDMM & obj.AMask: {enc: rVVVEncoding},
+ AVMANDNMM & obj.AMask: {enc: rVVVEncoding},
+ AVMXORMM & obj.AMask: {enc: rVVVEncoding},
+ AVMORMM & obj.AMask: {enc: rVVVEncoding},
+ AVMNORMM & obj.AMask: {enc: rVVVEncoding},
+ AVMORNMM & obj.AMask: {enc: rVVVEncoding},
+ AVMXNORMM & obj.AMask: {enc: rVVVEncoding},
+ AVCPOPM & obj.AMask: {enc: rVIEncoding},
+ AVFIRSTM & obj.AMask: {enc: rVIEncoding},
+ AVMSBFM & obj.AMask: {enc: rVVEncoding},
+ AVMSIFM & obj.AMask: {enc: rVVEncoding},
+ AVMSOFM & obj.AMask: {enc: rVVEncoding},
+ AVIOTAM & obj.AMask: {enc: rVVEncoding},
+ AVIDV & obj.AMask: {enc: rVVEncoding},
+
//
// Privileged ISA
//
ins.as = AVFSGNJNVV
}
ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)
+
+ case AVMANDMM, AVMNANDMM, AVMANDNMM, AVMXORMM, AVMORMM, AVMNORMM, AVMORNMM, AVMXNORMM, AVMMVM, AVMNOTM:
+ ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)
+ switch ins.as {
+ case AVMMVM:
+ ins.as, ins.rs2 = AVMANDMM, ins.rs1
+ case AVMNOTM:
+ ins.as, ins.rs2 = AVMNANDMM, ins.rs1
+ }
+
+ case AVMCLRM, AVMSETM:
+ ins.rd, ins.rs1, ins.rs2 = uint32(p.From.Reg), uint32(p.From.Reg), uint32(p.From.Reg)
+ switch ins.as {
+ case AVMCLRM:
+ ins.as = AVMXORMM
+ case AVMSETM:
+ ins.as = AVMXNORMM
+ }
+
+ case AVCPOPM, AVFIRSTM, AVMSBFM, AVMSIFM, AVMSOFM, AVIOTAM:
+ // Set mask bit
+ switch {
+ case ins.rs1 == obj.REG_NONE:
+ ins.funct7 |= 1 // unmasked
+ case ins.rs1 != REG_V0:
+ p.Ctxt.Diag("%v: invalid vector mask register", p)
+ }
+ ins.rs1 = obj.REG_NONE
+
+ case AVIDV:
+ // Set mask bit
+ switch {
+ case ins.rd == obj.REG_NONE:
+ ins.funct7 |= 1 // unmasked
+ case ins.rd != obj.REG_NONE && ins.rs2 != REG_V0:
+ p.Ctxt.Diag("%v: invalid vector mask register", p)
+ }
+ if ins.rd == obj.REG_NONE {
+ ins.rd = uint32(p.From.Reg)
+ }
+ ins.rs1, ins.rs2 = obj.REG_NONE, REG_V0
}
for _, ins := range inss {