(MOV(H|W)reg (SRAWconst [c] (MOVHreg x))) => (SRAWconst [c] (MOVHreg x))
(MOVWreg (SRAWconst [c] (MOVWreg x))) => (SRAWconst [c] (MOVWreg x))
-(MOV(WZ|W)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) <= 32 => (S(R|RA)Wconst [c] x)
-(MOV(HZ|H)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) <= 16 => (S(R|RA)Wconst [c] x)
-(MOV(BZ|B)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) == 8 => (S(R|RA)Wconst [c] x)
+(MOV(WZ|W)reg (S(R|RA)Wconst [c] x)) && x.Type.Size() <= 32 => (S(R|RA)Wconst [c] x)
+(MOV(HZ|H)reg (S(R|RA)Wconst [c] x)) && x.Type.Size() <= 16 => (S(R|RA)Wconst [c] x)
+(MOV(BZ|B)reg (S(R|RA)Wconst [c] x)) && x.Type.Size() == 8 => (S(R|RA)Wconst [c] x)
// initial right shift will handle sign/zero extend
(MOVBZreg (SRDconst [c] x)) && c>=56 => (SRDconst [c] x)
=> x
// Pass constants through math.Float{32,64}bits and math.Float{32,64}frombits
-(Load <t1> p1 (Store {t2} p2 (Const64 [x]) _)) && isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) => (Const64F [math.Float64frombits(uint64(x))])
-(Load <t1> p1 (Store {t2} p2 (Const32 [x]) _)) && isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) => (Const32F [math.Float32frombits(uint32(x))])
-(Load <t1> p1 (Store {t2} p2 (Const64F [x]) _)) && isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) => (Const64 [int64(math.Float64bits(x))])
-(Load <t1> p1 (Store {t2} p2 (Const32F [x]) _)) && isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) => (Const32 [int32(math.Float32bits(x))])
+(Load <t1> p1 (Store {t2} p2 (Const64 [x]) _)) && isSamePtr(p1,p2) && t2.Size() == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) => (Const64F [math.Float64frombits(uint64(x))])
+(Load <t1> p1 (Store {t2} p2 (Const32 [x]) _)) && isSamePtr(p1,p2) && t2.Size() == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) => (Const32F [math.Float32frombits(uint32(x))])
+(Load <t1> p1 (Store {t2} p2 (Const64F [x]) _)) && isSamePtr(p1,p2) && t2.Size() == 8 && is64BitInt(t1) => (Const64 [int64(math.Float64bits(x))])
+(Load <t1> p1 (Store {t2} p2 (Const32F [x]) _)) && isSamePtr(p1,p2) && t2.Size() == 4 && is32BitInt(t1) => (Const32 [int32(math.Float32bits(x))])
// Float Loads up to Zeros so they can be constant folded.
(Load <t1> op:(OffPtr [o1] p1)
return false
}
-func areAdjacentOffsets(off1, off2, size int64) bool {
- return off1+size == off2 || off1 == off2+size
-}
-
// check if value zeroes out upper 32-bit of 64-bit register.
// depth limits recursion depth. In AMD64.rules 3 is used as limit,
// because it catches same amount of cases as 4.
return nto(shiftedMask)
}
-// sizeof returns the size of t in bytes.
-// It will panic if t is not a *types.Type.
-func sizeof(t interface{}) int64 {
- return t.(*types.Type).Size()
-}
-
// registerizable reports whether t is a primitive type that fits in
// a register. It assumes float64 values will always fit into registers
// even if that isn't strictly true.
return true
}
// match: (MOVBZreg (SRWconst [c] x))
- // cond: sizeof(x.Type) == 8
+ // cond: x.Type.Size() == 8
// result: (SRWconst [c] x)
for {
if v_0.Op != OpPPC64SRWconst {
}
c := auxIntToInt64(v_0.AuxInt)
x := v_0.Args[0]
- if !(sizeof(x.Type) == 8) {
+ if !(x.Type.Size() == 8) {
break
}
v.reset(OpPPC64SRWconst)
return true
}
// match: (MOVBreg (SRAWconst [c] x))
- // cond: sizeof(x.Type) == 8
+ // cond: x.Type.Size() == 8
// result: (SRAWconst [c] x)
for {
if v_0.Op != OpPPC64SRAWconst {
}
c := auxIntToInt64(v_0.AuxInt)
x := v_0.Args[0]
- if !(sizeof(x.Type) == 8) {
+ if !(x.Type.Size() == 8) {
break
}
v.reset(OpPPC64SRAWconst)
return true
}
// match: (MOVHZreg (SRWconst [c] x))
- // cond: sizeof(x.Type) <= 16
+ // cond: x.Type.Size() <= 16
// result: (SRWconst [c] x)
for {
if v_0.Op != OpPPC64SRWconst {
}
c := auxIntToInt64(v_0.AuxInt)
x := v_0.Args[0]
- if !(sizeof(x.Type) <= 16) {
+ if !(x.Type.Size() <= 16) {
break
}
v.reset(OpPPC64SRWconst)
return true
}
// match: (MOVHreg (SRAWconst [c] x))
- // cond: sizeof(x.Type) <= 16
+ // cond: x.Type.Size() <= 16
// result: (SRAWconst [c] x)
for {
if v_0.Op != OpPPC64SRAWconst {
}
c := auxIntToInt64(v_0.AuxInt)
x := v_0.Args[0]
- if !(sizeof(x.Type) <= 16) {
+ if !(x.Type.Size() <= 16) {
break
}
v.reset(OpPPC64SRAWconst)
return true
}
// match: (MOVWZreg (SRWconst [c] x))
- // cond: sizeof(x.Type) <= 32
+ // cond: x.Type.Size() <= 32
// result: (SRWconst [c] x)
for {
if v_0.Op != OpPPC64SRWconst {
}
c := auxIntToInt64(v_0.AuxInt)
x := v_0.Args[0]
- if !(sizeof(x.Type) <= 32) {
+ if !(x.Type.Size() <= 32) {
break
}
v.reset(OpPPC64SRWconst)
return true
}
// match: (MOVWreg (SRAWconst [c] x))
- // cond: sizeof(x.Type) <= 32
+ // cond: x.Type.Size() <= 32
// result: (SRAWconst [c] x)
for {
if v_0.Op != OpPPC64SRAWconst {
}
c := auxIntToInt64(v_0.AuxInt)
x := v_0.Args[0]
- if !(sizeof(x.Type) <= 32) {
+ if !(x.Type.Size() <= 32) {
break
}
v.reset(OpPPC64SRAWconst)
return true
}
// match: (Load <t1> p1 (Store {t2} p2 (Const64 [x]) _))
- // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))
+ // cond: isSamePtr(p1,p2) && t2.Size() == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))
// result: (Const64F [math.Float64frombits(uint64(x))])
for {
t1 := v.Type
break
}
x := auxIntToInt64(v_1_1.AuxInt)
- if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))) {
+ if !(isSamePtr(p1, p2) && t2.Size() == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))) {
break
}
v.reset(OpConst64F)
return true
}
// match: (Load <t1> p1 (Store {t2} p2 (Const32 [x]) _))
- // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))
+ // cond: isSamePtr(p1,p2) && t2.Size() == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))
// result: (Const32F [math.Float32frombits(uint32(x))])
for {
t1 := v.Type
break
}
x := auxIntToInt32(v_1_1.AuxInt)
- if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))) {
+ if !(isSamePtr(p1, p2) && t2.Size() == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))) {
break
}
v.reset(OpConst32F)
return true
}
// match: (Load <t1> p1 (Store {t2} p2 (Const64F [x]) _))
- // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1)
+ // cond: isSamePtr(p1,p2) && t2.Size() == 8 && is64BitInt(t1)
// result: (Const64 [int64(math.Float64bits(x))])
for {
t1 := v.Type
break
}
x := auxIntToFloat64(v_1_1.AuxInt)
- if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) {
+ if !(isSamePtr(p1, p2) && t2.Size() == 8 && is64BitInt(t1)) {
break
}
v.reset(OpConst64)
return true
}
// match: (Load <t1> p1 (Store {t2} p2 (Const32F [x]) _))
- // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1)
+ // cond: isSamePtr(p1,p2) && t2.Size() == 4 && is32BitInt(t1)
// result: (Const32 [int32(math.Float32bits(x))])
for {
t1 := v.Type
break
}
x := auxIntToFloat32(v_1_1.AuxInt)
- if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) {
+ if !(isSamePtr(p1, p2) && t2.Size() == 4 && is32BitInt(t1)) {
break
}
v.reset(OpConst32)