sync/atomic: add memory barriers to Load/StoreInt32 on darwin/arm

After switching to an iPhone 5 for the darwin/arm builds,
TestStoreLoadRelAcq32 started to timeout on every builder run.
Adding the same memory barriers as armLoadUint64 and armStoreUint64
makes the test complete successfully.

Fixes sync/atomic tests on the darwin/arm builder.

Change-Id: Id73de31679304e259bdbd7f2f94383ae7fd70ee4
Reviewed-on: https://go-review.googlesource.com/67390
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Dmitry Vyukov <dvyukov@google.com>

diff --git a/src/sync/atomic/asm_darwin_arm.s b/src/sync/atomic/asm_darwin_arm.s
index c64336034d7911674d2f7a7ba264b8d3f4e43cb8..226822926f5f2bf2b0ac89ecb153bea4ec593cf2 100644 (file)
--- a/src/sync/atomic/asm_darwin_arm.s
+++ b/src/sync/atomic/asm_darwin_arm.s
@@ -6,6 +6,12 @@
 
 // Darwin/ARM atomic operations.
 
+#define DMB_ISHST_7 \
+    WORD    $0xf57ff05a // dmb ishst
+
+#define DMB_ISH_7 \
+    WORD    $0xf57ff05b // dmb ish
+
 TEXT ·CompareAndSwapInt32(SB),NOSPLIT,$0
        B ·CompareAndSwapUint32(SB)
 
@@ -58,9 +64,11 @@ TEXT ·LoadUint32(SB),NOSPLIT,$0-8
        MOVW addr+0(FP), R1
 load32loop:
        LDREX (R1), R2          // loads R2
+       DMB_ISHST_7
        STREX R2, (R1), R0      // stores R2
        CMP $0, R0
        BNE load32loop
+       DMB_ISH_7
        MOVW R2, val+4(FP)
        RET
 
@@ -84,9 +92,11 @@ TEXT ·StoreUint32(SB),NOSPLIT,$0-8
        MOVW val+4(FP), R2
 storeloop:
        LDREX (R1), R4          // loads R4
+       DMB_ISHST_7
        STREX R2, (R1), R0      // stores R2
        CMP $0, R0
        BNE storeloop
+       DMB_ISH_7
        RET
 
 TEXT ·StoreInt64(SB),NOSPLIT,$0