cmd/compile: add DWARF register mappings for ARM64.

Add DWARF register mappings for ARM64, so that that arch will become
usable with "-dwarflocationlists". [NB: I've plugged in a set of
numbers from the doc, but this will require additional manual testing.]

Change-Id: Id9aa63857bc8b4f5c825f49274101cf372e9e856
Reviewed-on: https://go-review.googlesource.com/82515
Reviewed-by: Heschi Kreinick <heschi@google.com>

diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index 3bb897c7a8541081d72a7595cf4b7a39684c7c12..b70426af2dec276b19af36d588c828ca6e49b787 100644 (file)
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -261,6 +261,109 @@ const (
        FREGEXT = REG_F26 // first external register
 )
 
+// http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
+var ARM64DWARFRegisters = map[int16]int16{
+       REG_R0:  0,
+       REG_R1:  1,
+       REG_R2:  2,
+       REG_R3:  3,
+       REG_R4:  4,
+       REG_R5:  5,
+       REG_R6:  6,
+       REG_R7:  7,
+       REG_R8:  8,
+       REG_R9:  9,
+       REG_R10: 10,
+       REG_R11: 11,
+       REG_R12: 12,
+       REG_R13: 13,
+       REG_R14: 14,
+       REG_R15: 15,
+       REG_R16: 16,
+       REG_R17: 17,
+       REG_R18: 18,
+       REG_R19: 19,
+       REG_R20: 20,
+       REG_R21: 21,
+       REG_R22: 22,
+       REG_R23: 23,
+       REG_R24: 24,
+       REG_R25: 25,
+       REG_R26: 26,
+       REG_R27: 27,
+       REG_R28: 28,
+       REG_R29: 29,
+       REG_R30: 30,
+
+       // floating point
+       REG_F0:  64,
+       REG_F1:  65,
+       REG_F2:  66,
+       REG_F3:  67,
+       REG_F4:  68,
+       REG_F5:  69,
+       REG_F6:  70,
+       REG_F7:  71,
+       REG_F8:  72,
+       REG_F9:  73,
+       REG_F10: 74,
+       REG_F11: 75,
+       REG_F12: 76,
+       REG_F13: 77,
+       REG_F14: 78,
+       REG_F15: 79,
+       REG_F16: 80,
+       REG_F17: 81,
+       REG_F18: 82,
+       REG_F19: 83,
+       REG_F20: 84,
+       REG_F21: 85,
+       REG_F22: 86,
+       REG_F23: 87,
+       REG_F24: 88,
+       REG_F25: 89,
+       REG_F26: 90,
+       REG_F27: 91,
+       REG_F28: 92,
+       REG_F29: 93,
+       REG_F30: 94,
+       REG_F31: 95,
+
+       // SIMD
+       REG_V0:  64,
+       REG_V1:  65,
+       REG_V2:  66,
+       REG_V3:  67,
+       REG_V4:  68,
+       REG_V5:  69,
+       REG_V6:  70,
+       REG_V7:  71,
+       REG_V8:  72,
+       REG_V9:  73,
+       REG_V10: 74,
+       REG_V11: 75,
+       REG_V12: 76,
+       REG_V13: 77,
+       REG_V14: 78,
+       REG_V15: 79,
+       REG_V16: 80,
+       REG_V17: 81,
+       REG_V18: 82,
+       REG_V19: 83,
+       REG_V20: 84,
+       REG_V21: 85,
+       REG_V22: 86,
+       REG_V23: 87,
+       REG_V24: 88,
+       REG_V25: 89,
+       REG_V26: 90,
+       REG_V27: 91,
+       REG_V28: 92,
+       REG_V29: 93,
+       REG_V30: 94,
+       REG_V31: 95,
+}
+
 const (
        BIG = 2048 - 8
 )

diff --git a/src/cmd/internal/obj/arm64/obj7.go b/src/cmd/internal/obj/arm64/obj7.go
index 71fc523fe030f68bf0c0bb414ba33189f610547a..1bd4a5d7b16dbf71f615fb0c5cd305d85c2cf567 100644 (file)
--- a/src/cmd/internal/obj/arm64/obj7.go
+++ b/src/cmd/internal/obj/arm64/obj7.go
@@ -838,10 +838,11 @@ var unaryDst = map[obj.As]bool{
 }
 
 var Linkarm64 = obj.LinkArch{
-       Arch:       sys.ArchARM64,
-       Init:       buildop,
-       Preprocess: preprocess,
-       Assemble:   span7,
-       Progedit:   progedit,
-       UnaryDst:   unaryDst,
+       Arch:           sys.ArchARM64,
+       Init:           buildop,
+       Preprocess:     preprocess,
+       Assemble:       span7,
+       Progedit:       progedit,
+       UnaryDst:       unaryDst,
+       DWARFRegisters: ARM64DWARFRegisters,
 }