cmd/compile,bytealg: change context register on riscv64

The register ABI will use X8-X23 (CL 356519),
this CL changes context register from X20(S4) to X26(S10) to meet the
prerequisite.

Update #40724

Change-Id: I93d51d22fe7b3ea5ceffe96dff93e3af60fbe7f6
Reviewed-on: https://go-review.googlesource.com/c/go/+/357974
Trust: mzh <mzh@golangcn.org>
Run-TryBot: mzh <mzh@golangcn.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>

diff --git a/src/cmd/compile/internal/riscv64/ssa.go b/src/cmd/compile/internal/riscv64/ssa.go
index 1359b6a0c388b416dbcda35ef746d0c88497ef44..fc52e9427d61f31f9f9eb5f4b62930f0b8ea9001 100644 (file)
--- a/src/cmd/compile/internal/riscv64/ssa.go
+++ b/src/cmd/compile/internal/riscv64/ssa.go
@@ -648,7 +648,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
                }
 
        case ssa.OpRISCV64LoweredGetClosurePtr:
-               // Closure pointer is S4 (riscv.REG_CTXT).
+               // Closure pointer is S10 (riscv.REG_CTXT).
                ssagen.CheckLoweredGetClosurePtr(v)
 
        case ssa.OpRISCV64LoweredGetCallerSP:

diff --git a/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go b/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
index 076919773b47a3deb19862f5ebf74e6b5e79fa65..09a8bb38c9ab9f193c2bef8b696975b6728e188e 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
@@ -26,7 +26,7 @@ import (
 
 const (
        riscv64REG_G    = 27
-       riscv64REG_CTXT = 20
+       riscv64REG_CTXT = 26
        riscv64REG_LR   = 1
        riscv64REG_SP   = 2
        riscv64REG_GP   = 3
@@ -115,7 +115,7 @@ func init() {
                panic("Too many RISCV64 registers")
        }
 
-       regCtxt := regNamed["X20"]
+       regCtxt := regNamed["X26"]
        callerSave := gpMask | fpMask | regNamed["g"]
 
        var (

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 81fe5d4c23cbc6d99054e54f7e2c95688a465063..6f0eb4501487d89418240fe2a3d3a278ea3e6742 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -28898,7 +28898,7 @@ var opcodeTable = [...]opInfo{
                call:    true,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {1, 524288},     // X20
+                               {1, 33554432},   // X26
                                {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
                        },
                        clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -29189,7 +29189,7 @@ var opcodeTable = [...]opInfo{
                argLen: 0,
                reg: regInfo{
                        outputs: []outputInfo{
-                               {0, 524288}, // X20
+                               {0, 33554432}, // X26
                        },
                },
        },

diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index d9434e74158ba8daeed3768333836ac260ea0296..8c2daf6e5bd9122a4230f6b40c78f89884189f11 100644 (file)
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -125,13 +125,13 @@ const (
        REG_A7   = REG_X17
        REG_S2   = REG_X18
        REG_S3   = REG_X19
-       REG_S4   = REG_X20 // aka REG_CTXT
+       REG_S4   = REG_X20
        REG_S5   = REG_X21
        REG_S6   = REG_X22
        REG_S7   = REG_X23
        REG_S8   = REG_X24
        REG_S9   = REG_X25
-       REG_S10  = REG_X26
+       REG_S10  = REG_X26 // aka REG_CTXT
        REG_S11  = REG_X27 // aka REG_G
        REG_T3   = REG_X28
        REG_T4   = REG_X29
@@ -139,8 +139,8 @@ const (
        REG_T6   = REG_X31 // aka REG_TMP
 
        // Go runtime register names.
+       REG_CTXT = REG_S10 // Context for closures.
        REG_G    = REG_S11 // G pointer.
-       REG_CTXT = REG_S4  // Context for closures.
        REG_LR   = REG_RA  // Link register.
        REG_TMP  = REG_T6  // Reserved for assembler use.
 

diff --git a/src/internal/bytealg/equal_riscv64.s b/src/internal/bytealg/equal_riscv64.s
index 959a996f81ea9b4d0d5d68a03d49a17d5165d4c4..5dd13beb5552de196fed663f4a361c7b7af2e86a 100644 (file)
--- a/src/internal/bytealg/equal_riscv64.s
+++ b/src/internal/bytealg/equal_riscv64.s
@@ -5,7 +5,7 @@
 #include "go_asm.h"
 #include "textflag.h"
 
-#define        CTXT    S4
+#define        CTXT    S10
 
 // func memequal(a, b unsafe.Pointer, size uintptr) bool
 TEXT runtime·memequal(SB),NOSPLIT|NOFRAME,$0-25