No change in semantics, just removing an unneeded helper.
Also align rules a bit.
Change-Id: Ie4dabb99392315a7700c645b3d0931eb8766a5fa
Reviewed-on: https://go-review.googlesource.com/c/go/+/483439
Reviewed-by: David Chase <drchase@google.com>
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@google.com>
(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
// Lowering stores
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
// Lowering stores
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
// loads
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zero instructions
(Zero [0] _ mem) => mem
// loads
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
// zeroing
(Zero [0] _ mem) => mem
// loads
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zeroing
(Zero [0] _ mem) => mem
// loads
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zero instructions
(Zero [0] _ mem) => mem
// loads
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
-(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
+(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
// zeroing
(Zero [0] _ mem) => mem
(ZeroExt16to(32|64) ...) => (MOVHZreg ...)
(ZeroExt32to64 ...) => (MOVWZreg ...)
-(Trunc(16|32|64)to8 <t> x) && isSigned(t) => (MOVBreg x)
+(Trunc(16|32|64)to8 <t> x) && t.IsSigned() => (MOVBreg x)
(Trunc(16|32|64)to8 x) => (MOVBZreg x)
-(Trunc(32|64)to16 <t> x) && isSigned(t) => (MOVHreg x)
+(Trunc(32|64)to16 <t> x) && t.IsSigned() => (MOVHreg x)
(Trunc(32|64)to16 x) => (MOVHZreg x)
-(Trunc64to32 <t> x) && isSigned(t) => (MOVWreg x)
+(Trunc64to32 <t> x) && t.IsSigned() => (MOVWreg x)
(Trunc64to32 x) => (MOVWZreg x)
// Lowering constants
// Lowering comparisons
(EqB x y) => (Select0 <typ.Int> (ANDCCconst [1] (EQV x y)))
// Sign extension dependence on operand sign sets up for sign/zero-extension elision later
-(Eq(8|16) x y) && isSigned(x.Type) && isSigned(y.Type) => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
+(Eq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
(Eq(8|16) x y) => (Equal (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
(Eq(32|64|Ptr) x y) => (Equal ((CMPW|CMP|CMP) x y))
(Eq(32|64)F x y) => (Equal (FCMPU x y))
(NeqB ...) => (XOR ...)
// Like Eq8 and Eq16, prefer sign extension likely to enable later elision.
-(Neq(8|16) x y) && isSigned(x.Type) && isSigned(y.Type) => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
+(Neq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
(Neq(8|16) x y) => (NotEqual (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
(Neq(32|64|Ptr) x y) => (NotEqual ((CMPW|CMP|CMP) x y))
(Neq(32|64)F x y) => (NotEqual (FCMPU x y))
// Lowering loads
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
-(Load <t> ptr mem) && is32BitInt(t) && isSigned(t) => (MOVWload ptr mem)
-(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) => (MOVWZload ptr mem)
-(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) => (MOVHload ptr mem)
-(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) => (MOVHZload ptr mem)
+(Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
+(Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
+(Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
+(Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
(Load <t> ptr mem) && t.IsBoolean() => (MOVBZload ptr mem)
-(Load <t> ptr mem) && is8BitInt(t) && isSigned(t) => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
-(Load <t> ptr mem) && is8BitInt(t) && !isSigned(t) => (MOVBZload ptr mem)
+(Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
+(Load <t> ptr mem) && is8BitInt(t) && !t.IsSigned() => (MOVBZload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
(MOV(B|W)Zreg x:(Select0 (LoweredAtomicLoad(8|32) _ _))) => x
// don't extend if argument is already extended
-(MOVBreg x:(Arg <t>)) && is8BitInt(t) && isSigned(t) => x
-(MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !isSigned(t) => x
-(MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && isSigned(t) => x
-(MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) => x
-(MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) => x
-(MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) => x
+(MOVBreg x:(Arg <t>)) && is8BitInt(t) && t.IsSigned() => x
+(MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !t.IsSigned() => x
+(MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && t.IsSigned() => x
+(MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !t.IsSigned() => x
+(MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned() => x
+(MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned() => x
(MOVBZreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
(MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
(Neq32F ...) => (FNES ...)
// Loads
-(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
-(Load <t> ptr mem) && ( is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
-(Load <t> ptr mem) && ( is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
-(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
-(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
-(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
-(Load <t> ptr mem) && is32BitFloat(t) => (FMOVWload ptr mem)
-(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
+(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
+(Load <t> ptr mem) && ( is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
+(Load <t> ptr mem) && ( is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
+(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
+(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
+(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
+(Load <t> ptr mem) && is32BitFloat(t) => (FMOVWload ptr mem)
+(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
// Stores
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
// Lowering loads
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
-(Load <t> ptr mem) && is32BitInt(t) && isSigned(t) => (MOVWload ptr mem)
-(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) => (MOVWZload ptr mem)
-(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) => (MOVHload ptr mem)
-(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) => (MOVHZload ptr mem)
-(Load <t> ptr mem) && is8BitInt(t) && isSigned(t) => (MOVBload ptr mem)
-(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) => (MOVBZload ptr mem)
+(Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
+(Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
+(Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
+(Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
+(Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBload ptr mem)
+(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !t.IsSigned())) => (MOVBZload ptr mem)
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
// Lowering stores
-(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
-(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
return t.IsPtrShaped()
}
-func isSigned(t *types.Type) bool {
- return t.IsSigned()
-}
-
// mergeSym merges two symbolic offsets. There is no real merging of
// offsets, we just pick the non-nil one.
func mergeSym(x, y Sym) Sym {
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && isSigned(t))
+ // cond: (is8BitInt(t) && t.IsSigned())
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpARMMOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && !isSigned(t))
+ // cond: (is8BitInt(t) && !t.IsSigned())
// result: (MOVBUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpARMMOVBUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && isSigned(t))
+ // cond: (is16BitInt(t) && t.IsSigned())
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpARMMOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && !isSigned(t))
+ // cond: (is16BitInt(t) && !t.IsSigned())
// result: (MOVHUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpARMMOVHUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && isSigned(t))
+ // cond: (is8BitInt(t) && t.IsSigned())
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpARM64MOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && !isSigned(t))
+ // cond: (is8BitInt(t) && !t.IsSigned())
// result: (MOVBUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpARM64MOVBUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && isSigned(t))
+ // cond: (is16BitInt(t) && t.IsSigned())
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpARM64MOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && !isSigned(t))
+ // cond: (is16BitInt(t) && !t.IsSigned())
// result: (MOVHUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpARM64MOVHUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && isSigned(t))
+ // cond: (is32BitInt(t) && t.IsSigned())
// result: (MOVWload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && isSigned(t)) {
+ if !(is32BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpARM64MOVWload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && !isSigned(t))
+ // cond: (is32BitInt(t) && !t.IsSigned())
// result: (MOVWUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && !isSigned(t)) {
+ if !(is32BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpARM64MOVWUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && isSigned(t))
+ // cond: (is8BitInt(t) && t.IsSigned())
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpLOONG64MOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && !isSigned(t))
+ // cond: (is8BitInt(t) && !t.IsSigned())
// result: (MOVBUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpLOONG64MOVBUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && isSigned(t))
+ // cond: (is16BitInt(t) && t.IsSigned())
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpLOONG64MOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && !isSigned(t))
+ // cond: (is16BitInt(t) && !t.IsSigned())
// result: (MOVHUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpLOONG64MOVHUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && isSigned(t))
+ // cond: (is32BitInt(t) && t.IsSigned())
// result: (MOVWload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && isSigned(t)) {
+ if !(is32BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpLOONG64MOVWload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && !isSigned(t))
+ // cond: (is32BitInt(t) && !t.IsSigned())
// result: (MOVWUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && !isSigned(t)) {
+ if !(is32BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpLOONG64MOVWUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && isSigned(t))
+ // cond: (is8BitInt(t) && t.IsSigned())
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpMIPSMOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && !isSigned(t))
+ // cond: (is8BitInt(t) && !t.IsSigned())
// result: (MOVBUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpMIPSMOVBUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && isSigned(t))
+ // cond: (is16BitInt(t) && t.IsSigned())
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpMIPSMOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && !isSigned(t))
+ // cond: (is16BitInt(t) && !t.IsSigned())
// result: (MOVHUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpMIPSMOVHUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && isSigned(t))
+ // cond: (is8BitInt(t) && t.IsSigned())
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpMIPS64MOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is8BitInt(t) && !isSigned(t))
+ // cond: (is8BitInt(t) && !t.IsSigned())
// result: (MOVBUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpMIPS64MOVBUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && isSigned(t))
+ // cond: (is16BitInt(t) && t.IsSigned())
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpMIPS64MOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && !isSigned(t))
+ // cond: (is16BitInt(t) && !t.IsSigned())
// result: (MOVHUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpMIPS64MOVHUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && isSigned(t))
+ // cond: (is32BitInt(t) && t.IsSigned())
// result: (MOVWload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && isSigned(t)) {
+ if !(is32BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpMIPS64MOVWload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && !isSigned(t))
+ // cond: (is32BitInt(t) && !t.IsSigned())
// result: (MOVWUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && !isSigned(t)) {
+ if !(is32BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpMIPS64MOVWUload)
b := v.Block
typ := &b.Func.Config.Types
// match: (Eq16 x y)
- // cond: isSigned(x.Type) && isSigned(y.Type)
+ // cond: x.Type.IsSigned() && y.Type.IsSigned()
// result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y)))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
y := v_1
- if !(isSigned(x.Type) && isSigned(y.Type)) {
+ if !(x.Type.IsSigned() && y.Type.IsSigned()) {
continue
}
v.reset(OpPPC64Equal)
b := v.Block
typ := &b.Func.Config.Types
// match: (Eq8 x y)
- // cond: isSigned(x.Type) && isSigned(y.Type)
+ // cond: x.Type.IsSigned() && y.Type.IsSigned()
// result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y)))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
y := v_1
- if !(isSigned(x.Type) && isSigned(y.Type)) {
+ if !(x.Type.IsSigned() && y.Type.IsSigned()) {
continue
}
v.reset(OpPPC64Equal)
return true
}
// match: (Load <t> ptr mem)
- // cond: is32BitInt(t) && isSigned(t)
+ // cond: is32BitInt(t) && t.IsSigned()
// result: (MOVWload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && isSigned(t)) {
+ if !(is32BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpPPC64MOVWload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is32BitInt(t) && !isSigned(t)
+ // cond: is32BitInt(t) && !t.IsSigned()
// result: (MOVWZload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && !isSigned(t)) {
+ if !(is32BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpPPC64MOVWZload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is16BitInt(t) && isSigned(t)
+ // cond: is16BitInt(t) && t.IsSigned()
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpPPC64MOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is16BitInt(t) && !isSigned(t)
+ // cond: is16BitInt(t) && !t.IsSigned()
// result: (MOVHZload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpPPC64MOVHZload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is8BitInt(t) && isSigned(t)
+ // cond: is8BitInt(t) && t.IsSigned()
// result: (MOVBreg (MOVBZload ptr mem))
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpPPC64MOVBreg)
return true
}
// match: (Load <t> ptr mem)
- // cond: is8BitInt(t) && !isSigned(t)
+ // cond: is8BitInt(t) && !t.IsSigned()
// result: (MOVBZload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpPPC64MOVBZload)
b := v.Block
typ := &b.Func.Config.Types
// match: (Neq16 x y)
- // cond: isSigned(x.Type) && isSigned(y.Type)
+ // cond: x.Type.IsSigned() && y.Type.IsSigned()
// result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y)))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
y := v_1
- if !(isSigned(x.Type) && isSigned(y.Type)) {
+ if !(x.Type.IsSigned() && y.Type.IsSigned()) {
continue
}
v.reset(OpPPC64NotEqual)
b := v.Block
typ := &b.Func.Config.Types
// match: (Neq8 x y)
- // cond: isSigned(x.Type) && isSigned(y.Type)
+ // cond: x.Type.IsSigned() && y.Type.IsSigned()
// result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y)))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
x := v_0
y := v_1
- if !(isSigned(x.Type) && isSigned(y.Type)) {
+ if !(x.Type.IsSigned() && y.Type.IsSigned()) {
continue
}
v.reset(OpPPC64NotEqual)
return true
}
// match: (MOVBZreg x:(Arg <t>))
- // cond: is8BitInt(t) && !isSigned(t)
+ // cond: is8BitInt(t) && !t.IsSigned()
// result: x
for {
x := v_0
break
}
t := x.Type
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.copyOf(x)
return true
}
// match: (MOVBreg x:(Arg <t>))
- // cond: is8BitInt(t) && isSigned(t)
+ // cond: is8BitInt(t) && t.IsSigned()
// result: x
for {
x := v_0
break
}
t := x.Type
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.copyOf(x)
return true
}
// match: (MOVHZreg x:(Arg <t>))
- // cond: (is8BitInt(t) || is16BitInt(t)) && !isSigned(t)
+ // cond: (is8BitInt(t) || is16BitInt(t)) && !t.IsSigned()
// result: x
for {
x := v_0
break
}
t := x.Type
- if !((is8BitInt(t) || is16BitInt(t)) && !isSigned(t)) {
+ if !((is8BitInt(t) || is16BitInt(t)) && !t.IsSigned()) {
break
}
v.copyOf(x)
return true
}
// match: (MOVHreg x:(Arg <t>))
- // cond: (is8BitInt(t) || is16BitInt(t)) && isSigned(t)
+ // cond: (is8BitInt(t) || is16BitInt(t)) && t.IsSigned()
// result: x
for {
x := v_0
break
}
t := x.Type
- if !((is8BitInt(t) || is16BitInt(t)) && isSigned(t)) {
+ if !((is8BitInt(t) || is16BitInt(t)) && t.IsSigned()) {
break
}
v.copyOf(x)
return true
}
// match: (MOVWZreg x:(Arg <t>))
- // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t)
+ // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned()
// result: x
for {
x := v_0
break
}
t := x.Type
- if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t)) {
+ if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned()) {
break
}
v.copyOf(x)
return true
}
// match: (MOVWreg x:(Arg <t>))
- // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t)
+ // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned()
// result: x
for {
x := v_0
break
}
t := x.Type
- if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t)) {
+ if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned()) {
break
}
v.copyOf(x)
func rewriteValuePPC64_OpTrunc16to8(v *Value) bool {
v_0 := v.Args[0]
// match: (Trunc16to8 <t> x)
- // cond: isSigned(t)
+ // cond: t.IsSigned()
// result: (MOVBreg x)
for {
t := v.Type
x := v_0
- if !(isSigned(t)) {
+ if !(t.IsSigned()) {
break
}
v.reset(OpPPC64MOVBreg)
func rewriteValuePPC64_OpTrunc32to16(v *Value) bool {
v_0 := v.Args[0]
// match: (Trunc32to16 <t> x)
- // cond: isSigned(t)
+ // cond: t.IsSigned()
// result: (MOVHreg x)
for {
t := v.Type
x := v_0
- if !(isSigned(t)) {
+ if !(t.IsSigned()) {
break
}
v.reset(OpPPC64MOVHreg)
func rewriteValuePPC64_OpTrunc32to8(v *Value) bool {
v_0 := v.Args[0]
// match: (Trunc32to8 <t> x)
- // cond: isSigned(t)
+ // cond: t.IsSigned()
// result: (MOVBreg x)
for {
t := v.Type
x := v_0
- if !(isSigned(t)) {
+ if !(t.IsSigned()) {
break
}
v.reset(OpPPC64MOVBreg)
func rewriteValuePPC64_OpTrunc64to16(v *Value) bool {
v_0 := v.Args[0]
// match: (Trunc64to16 <t> x)
- // cond: isSigned(t)
+ // cond: t.IsSigned()
// result: (MOVHreg x)
for {
t := v.Type
x := v_0
- if !(isSigned(t)) {
+ if !(t.IsSigned()) {
break
}
v.reset(OpPPC64MOVHreg)
func rewriteValuePPC64_OpTrunc64to32(v *Value) bool {
v_0 := v.Args[0]
// match: (Trunc64to32 <t> x)
- // cond: isSigned(t)
+ // cond: t.IsSigned()
// result: (MOVWreg x)
for {
t := v.Type
x := v_0
- if !(isSigned(t)) {
+ if !(t.IsSigned()) {
break
}
v.reset(OpPPC64MOVWreg)
func rewriteValuePPC64_OpTrunc64to8(v *Value) bool {
v_0 := v.Args[0]
// match: (Trunc64to8 <t> x)
- // cond: isSigned(t)
+ // cond: t.IsSigned()
// result: (MOVBreg x)
for {
t := v.Type
x := v_0
- if !(isSigned(t)) {
+ if !(t.IsSigned()) {
break
}
v.reset(OpPPC64MOVBreg)
return true
}
// match: (Load <t> ptr mem)
- // cond: ( is8BitInt(t) && isSigned(t))
+ // cond: ( is8BitInt(t) && t.IsSigned())
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpRISCV64MOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: ( is8BitInt(t) && !isSigned(t))
+ // cond: ( is8BitInt(t) && !t.IsSigned())
// result: (MOVBUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && !isSigned(t)) {
+ if !(is8BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpRISCV64MOVBUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && isSigned(t))
+ // cond: (is16BitInt(t) && t.IsSigned())
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpRISCV64MOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is16BitInt(t) && !isSigned(t))
+ // cond: (is16BitInt(t) && !t.IsSigned())
// result: (MOVHUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpRISCV64MOVHUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && isSigned(t))
+ // cond: (is32BitInt(t) && t.IsSigned())
// result: (MOVWload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && isSigned(t)) {
+ if !(is32BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpRISCV64MOVWload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (is32BitInt(t) && !isSigned(t))
+ // cond: (is32BitInt(t) && !t.IsSigned())
// result: (MOVWUload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && !isSigned(t)) {
+ if !(is32BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpRISCV64MOVWUload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is32BitInt(t) && isSigned(t)
+ // cond: is32BitInt(t) && t.IsSigned()
// result: (MOVWload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && isSigned(t)) {
+ if !(is32BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpS390XMOVWload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is32BitInt(t) && !isSigned(t)
+ // cond: is32BitInt(t) && !t.IsSigned()
// result: (MOVWZload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is32BitInt(t) && !isSigned(t)) {
+ if !(is32BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpS390XMOVWZload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is16BitInt(t) && isSigned(t)
+ // cond: is16BitInt(t) && t.IsSigned()
// result: (MOVHload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && isSigned(t)) {
+ if !(is16BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpS390XMOVHload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is16BitInt(t) && !isSigned(t)
+ // cond: is16BitInt(t) && !t.IsSigned()
// result: (MOVHZload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is16BitInt(t) && !isSigned(t)) {
+ if !(is16BitInt(t) && !t.IsSigned()) {
break
}
v.reset(OpS390XMOVHZload)
return true
}
// match: (Load <t> ptr mem)
- // cond: is8BitInt(t) && isSigned(t)
+ // cond: is8BitInt(t) && t.IsSigned()
// result: (MOVBload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(is8BitInt(t) && isSigned(t)) {
+ if !(is8BitInt(t) && t.IsSigned()) {
break
}
v.reset(OpS390XMOVBload)
return true
}
// match: (Load <t> ptr mem)
- // cond: (t.IsBoolean() || (is8BitInt(t) && !isSigned(t)))
+ // cond: (t.IsBoolean() || (is8BitInt(t) && !t.IsSigned()))
// result: (MOVBZload ptr mem)
for {
t := v.Type
ptr := v_0
mem := v_1
- if !(t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) {
+ if !(t.IsBoolean() || (is8BitInt(t) && !t.IsSigned())) {
break
}
v.reset(OpS390XMOVBZload)