cmd/compile: remove carriage returns from AMD64latelower.rules

AMD64latelower.rules currently has Windows style line endings,
rather than Unix style line endings. Correct this.

Change-Id: Ie068dc6c64bd51cf2aa5bd192839fca4f28f40b8
Reviewed-on: https://go-review.googlesource.com/c/go/+/651818
Auto-Submit: Keith Randall <khr@golang.org>
Reviewed-by: Keith Randall <khr@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Keith Randall <khr@golang.org>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>

diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules
index 1dd804577aeafacb704c3ee28e134f6105cc8a3e..ead4ec45f1e28f7bc64e500b0b3a6fc95d8cb19e 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules
+++ b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules
@@ -1,13 +1,13 @@
-// Copyright 2022 The Go Authors. All rights reserved.\r
-// Use of this source code is governed by a BSD-style\r
-// license that can be found in the LICENSE file.\r
-\r
-// Prefer SARX/SHLX/SHRX instruction because it has less register restriction on the shift input.\r
-(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y)\r
-(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y)\r
-(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y)\r
-\r
-// See comments in ARM64latelower.rules for why these are here.\r
-(MOVLQZX x) && zeroUpper32Bits(x,3) => x\r
-(MOVWQZX x) && zeroUpper48Bits(x,3) => x\r
-(MOVBQZX x) && zeroUpper56Bits(x,3) => x\r
+// Copyright 2022 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Prefer SARX/SHLX/SHRX instruction because it has less register restriction on the shift input.
+(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y)
+(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y)
+(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y)
+
+// See comments in ARM64latelower.rules for why these are here.
+(MOVLQZX x) && zeroUpper32Bits(x,3) => x
+(MOVWQZX x) && zeroUpper48Bits(x,3) => x
+(MOVBQZX x) && zeroUpper56Bits(x,3) => x