cmd/asm: restore supporting of *1 scaling on ARM64

On ARM64, instruction like "MOVD (R1)(R2*1), R3" is accepted and
assembles correctly with Go 1.16, but errors out on tip with
"arm64 doesn't support scaled register format", since CL 289589.

"MOVD (R1)(R2), R3" is the preferred form. But the *1 form works
before and assembles correctly. Keep supporting it.

Fixes #46766.

Change-Id: I0f7fd71fa87ea698919a936b6c68aa5a91afd486
Reviewed-on: https://go-review.googlesource.com/c/go/+/328229
Trust: Cherry Mui <cherryyz@google.com>
Trust: Cuong Manh Le <cuong.manhle.vn@gmail.com>
Run-TryBot: Cherry Mui <cherryyz@google.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: eric fang <eric.fang@arm.com>

diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index ab48632a44b943a279c6382240230ffeef7dc8dd..4cddcf48a466eebf1a09b8e93eb9183dd7d4bb8e 100644 (file)
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -1003,7 +1003,8 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
                                p.errorf("unimplemented two-register form")
                        }
                        a.Index = r1
-                       if scale != 0 && p.arch.Family == sys.ARM64 {
+                       if scale != 0 && scale != 1 && p.arch.Family == sys.ARM64 {
+                               // Support (R1)(R2) (no scaling) and (R1)(R2*1).
                                p.errorf("arm64 doesn't support scaled register format")
                        } else {
                                a.Scale = int16(scale)

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 1146c1a7898db2f3b457fe9f072269be2f5db36f..5f1e68545baa63d85248e0d2d6d20bdcceac0404 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -547,6 +547,7 @@ TEXT        foo(SB), DUPOK|NOSPLIT, $-8
 // shifted or extended register offset.
        MOVD    (R2)(R6.SXTW), R4               // 44c866f8
        MOVD    (R3)(R6), R5                    // 656866f8
+       MOVD    (R3)(R6*1), R5                  // 656866f8
        MOVD    (R2)(R6), R4                    // 446866f8
        MOVWU   (R19)(R20<<2), R20              // 747a74b8
        MOVD    (R2)(R6<<3), R4                 // 447866f8
@@ -579,6 +580,7 @@ TEXT        foo(SB), DUPOK|NOSPLIT, $-8
        MOVB    R4, (R2)(R6.SXTX)               // 44e82638
        MOVB    R8, (R3)(R9.UXTW)               // 68482938
        MOVB    R10, (R5)(R8)                   // aa682838
+       MOVB    R10, (R5)(R8*1)                 // aa682838
        MOVH    R11, (R2)(R7.SXTW<<1)           // 4bd82778
        MOVH    R5, (R1)(R2<<1)                 // 25782278
        MOVH    R7, (R2)(R5.SXTX<<1)            // 47f82578