[dev.ssa] cmd/compile: add register spec to getg

This omission was causing the new regalloc to fail.

Change-Id: If7ba7be38a436dbd0dd443828ddd7ebf6e35be0e
Reviewed-on: https://go-review.googlesource.com/13632
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>

diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index 903eea3057f9e629842885cc576230cffb2d7f30..9e8b2fa018d96ceb236399ad3a8f746793eb1062 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -290,7 +290,7 @@ func init() {
 
                // Pseudo-ops
                {name: "LoweredPanicNilCheck"},
-               {name: "LoweredGetG"},
+               {name: "LoweredGetG", reg: gp01},
        }
 
        var AMD64blocks = []blockData{

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 425c7e468c2cc138bc4d3a36adbe9289832f7adc..6f412806c8873d945680d916672003ab0264407a 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -2123,7 +2123,11 @@ var opcodeTable = [...]opInfo{
        },
        {
                name: "LoweredGetG",
-               reg:  regInfo{},
+               reg: regInfo{
+                       outputs: []regMask{
+                               65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
+                       },
+               },
        },
 
        {