(MULLconst [73] x) => (LEAL8 x (LEAL8 <v.Type> x x))
(MULLconst [81] x) => (LEAL8 (LEAL8 <v.Type> x x) (LEAL8 <v.Type> x x))
-(MULLconst [c] x) && isPowerOfTwo32(c+1) && c >= 15 => (SUBL (SHLLconst <v.Type> [int32(log32(c+1))] x) x)
-(MULLconst [c] x) && isPowerOfTwo32(c-1) && c >= 17 => (LEAL1 (SHLLconst <v.Type> [int32(log32(c-1))] x) x)
-(MULLconst [c] x) && isPowerOfTwo32(c-2) && c >= 34 => (LEAL2 (SHLLconst <v.Type> [int32(log32(c-2))] x) x)
-(MULLconst [c] x) && isPowerOfTwo32(c-4) && c >= 68 => (LEAL4 (SHLLconst <v.Type> [int32(log32(c-4))] x) x)
-(MULLconst [c] x) && isPowerOfTwo32(c-8) && c >= 136 => (LEAL8 (SHLLconst <v.Type> [int32(log32(c-8))] x) x)
-(MULLconst [c] x) && c%3 == 0 && isPowerOfTwo32(c/3) => (SHLLconst [int32(log32(c/3))] (LEAL2 <v.Type> x x))
-(MULLconst [c] x) && c%5 == 0 && isPowerOfTwo32(c/5) => (SHLLconst [int32(log32(c/5))] (LEAL4 <v.Type> x x))
-(MULLconst [c] x) && c%9 == 0 && isPowerOfTwo32(c/9) => (SHLLconst [int32(log32(c/9))] (LEAL8 <v.Type> x x))
+(MULLconst [c] x) && isPowerOfTwo(c+1) && c >= 15 => (SUBL (SHLLconst <v.Type> [int32(log32(c+1))] x) x)
+(MULLconst [c] x) && isPowerOfTwo(c-1) && c >= 17 => (LEAL1 (SHLLconst <v.Type> [int32(log32(c-1))] x) x)
+(MULLconst [c] x) && isPowerOfTwo(c-2) && c >= 34 => (LEAL2 (SHLLconst <v.Type> [int32(log32(c-2))] x) x)
+(MULLconst [c] x) && isPowerOfTwo(c-4) && c >= 68 => (LEAL4 (SHLLconst <v.Type> [int32(log32(c-4))] x) x)
+(MULLconst [c] x) && isPowerOfTwo(c-8) && c >= 136 => (LEAL8 (SHLLconst <v.Type> [int32(log32(c-8))] x) x)
+(MULLconst [c] x) && c%3 == 0 && isPowerOfTwo(c/3) => (SHLLconst [int32(log32(c/3))] (LEAL2 <v.Type> x x))
+(MULLconst [c] x) && c%5 == 0 && isPowerOfTwo(c/5) => (SHLLconst [int32(log32(c/5))] (LEAL4 <v.Type> x x))
+(MULLconst [c] x) && c%9 == 0 && isPowerOfTwo(c/9) => (SHLLconst [int32(log32(c/9))] (LEAL8 <v.Type> x x))
// combine add/shift into LEAL
(ADDL x (SHLLconst [3] y)) => (LEAL8 x y)
(MUL(Q|L)const [73] x) => (LEA(Q|L)8 x (LEA(Q|L)8 <v.Type> x x))
(MUL(Q|L)const [81] x) => (LEA(Q|L)8 (LEA(Q|L)8 <v.Type> x x) (LEA(Q|L)8 <v.Type> x x))
-(MUL(Q|L)const [c] x) && isPowerOfTwo64(int64(c)+1) && c >= 15 => (SUB(Q|L) (SHL(Q|L)const <v.Type> [int8(log64(int64(c)+1))] x) x)
-(MUL(Q|L)const [c] x) && isPowerOfTwo32(c-1) && c >= 17 => (LEA(Q|L)1 (SHL(Q|L)const <v.Type> [int8(log32(c-1))] x) x)
-(MUL(Q|L)const [c] x) && isPowerOfTwo32(c-2) && c >= 34 => (LEA(Q|L)2 (SHL(Q|L)const <v.Type> [int8(log32(c-2))] x) x)
-(MUL(Q|L)const [c] x) && isPowerOfTwo32(c-4) && c >= 68 => (LEA(Q|L)4 (SHL(Q|L)const <v.Type> [int8(log32(c-4))] x) x)
-(MUL(Q|L)const [c] x) && isPowerOfTwo32(c-8) && c >= 136 => (LEA(Q|L)8 (SHL(Q|L)const <v.Type> [int8(log32(c-8))] x) x)
-(MUL(Q|L)const [c] x) && c%3 == 0 && isPowerOfTwo32(c/3) => (SHL(Q|L)const [int8(log32(c/3))] (LEA(Q|L)2 <v.Type> x x))
-(MUL(Q|L)const [c] x) && c%5 == 0 && isPowerOfTwo32(c/5) => (SHL(Q|L)const [int8(log32(c/5))] (LEA(Q|L)4 <v.Type> x x))
-(MUL(Q|L)const [c] x) && c%9 == 0 && isPowerOfTwo32(c/9) => (SHL(Q|L)const [int8(log32(c/9))] (LEA(Q|L)8 <v.Type> x x))
+(MUL(Q|L)const [c] x) && isPowerOfTwo(int64(c)+1) && c >= 15 => (SUB(Q|L) (SHL(Q|L)const <v.Type> [int8(log64(int64(c)+1))] x) x)
+(MUL(Q|L)const [c] x) && isPowerOfTwo(c-1) && c >= 17 => (LEA(Q|L)1 (SHL(Q|L)const <v.Type> [int8(log32(c-1))] x) x)
+(MUL(Q|L)const [c] x) && isPowerOfTwo(c-2) && c >= 34 => (LEA(Q|L)2 (SHL(Q|L)const <v.Type> [int8(log32(c-2))] x) x)
+(MUL(Q|L)const [c] x) && isPowerOfTwo(c-4) && c >= 68 => (LEA(Q|L)4 (SHL(Q|L)const <v.Type> [int8(log32(c-4))] x) x)
+(MUL(Q|L)const [c] x) && isPowerOfTwo(c-8) && c >= 136 => (LEA(Q|L)8 (SHL(Q|L)const <v.Type> [int8(log32(c-8))] x) x)
+(MUL(Q|L)const [c] x) && c%3 == 0 && isPowerOfTwo(c/3) => (SHL(Q|L)const [int8(log32(c/3))] (LEA(Q|L)2 <v.Type> x x))
+(MUL(Q|L)const [c] x) && c%5 == 0 && isPowerOfTwo(c/5) => (SHL(Q|L)const [int8(log32(c/5))] (LEA(Q|L)4 <v.Type> x x))
+(MUL(Q|L)const [c] x) && c%9 == 0 && isPowerOfTwo(c/9) => (SHL(Q|L)const [int8(log32(c/9))] (LEA(Q|L)8 <v.Type> x x))
// combine add/shift into LEAQ/LEAL
(ADD(L|Q) x (SHL(L|Q)const [3] y)) => (LEA(L|Q)8 x y)
(MUL x (MOVWconst [c])) && int32(c) == -1 => (RSBconst [0] x)
(MUL _ (MOVWconst [0])) => (MOVWconst [0])
(MUL x (MOVWconst [1])) => x
-(MUL x (MOVWconst [c])) && isPowerOfTwo32(c) => (SLLconst [int32(log32(c))] x)
-(MUL x (MOVWconst [c])) && isPowerOfTwo32(c-1) && c >= 3 => (ADDshiftLL x x [int32(log32(c-1))])
-(MUL x (MOVWconst [c])) && isPowerOfTwo32(c+1) && c >= 7 => (RSBshiftLL x x [int32(log32(c+1))])
-(MUL x (MOVWconst [c])) && c%3 == 0 && isPowerOfTwo32(c/3) => (SLLconst [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1]))
-(MUL x (MOVWconst [c])) && c%5 == 0 && isPowerOfTwo32(c/5) => (SLLconst [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2]))
-(MUL x (MOVWconst [c])) && c%7 == 0 && isPowerOfTwo32(c/7) => (SLLconst [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3]))
-(MUL x (MOVWconst [c])) && c%9 == 0 && isPowerOfTwo32(c/9) => (SLLconst [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3]))
+(MUL x (MOVWconst [c])) && isPowerOfTwo(c) => (SLLconst [int32(log32(c))] x)
+(MUL x (MOVWconst [c])) && isPowerOfTwo(c-1) && c >= 3 => (ADDshiftLL x x [int32(log32(c-1))])
+(MUL x (MOVWconst [c])) && isPowerOfTwo(c+1) && c >= 7 => (RSBshiftLL x x [int32(log32(c+1))])
+(MUL x (MOVWconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (SLLconst [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1]))
+(MUL x (MOVWconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (SLLconst [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2]))
+(MUL x (MOVWconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (SLLconst [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3]))
+(MUL x (MOVWconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (SLLconst [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3]))
(MULA x (MOVWconst [c]) a) && c == -1 => (SUB a x)
(MULA _ (MOVWconst [0]) a) => a
(MULA x (MOVWconst [1]) a) => (ADD x a)
-(MULA x (MOVWconst [c]) a) && isPowerOfTwo32(c) => (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
-(MULA x (MOVWconst [c]) a) && isPowerOfTwo32(c-1) && c >= 3 => (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
-(MULA x (MOVWconst [c]) a) && isPowerOfTwo32(c+1) && c >= 7 => (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
-(MULA x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo32(c/3) => (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
-(MULA x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo32(c/5) => (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
-(MULA x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo32(c/7) => (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
-(MULA x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo32(c/9) => (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+(MULA x (MOVWconst [c]) a) && isPowerOfTwo(c) => (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULA x (MOVWconst [c]) a) && isPowerOfTwo(c-1) && c >= 3 => (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULA x (MOVWconst [c]) a) && isPowerOfTwo(c+1) && c >= 7 => (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULA x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo(c/3) => (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULA x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo(c/5) => (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULA x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo(c/7) => (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULA x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo(c/9) => (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
(MULA (MOVWconst [c]) x a) && c == -1 => (SUB a x)
(MULA (MOVWconst [0]) _ a) => a
(MULA (MOVWconst [1]) x a) => (ADD x a)
-(MULA (MOVWconst [c]) x a) && isPowerOfTwo32(c) => (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
-(MULA (MOVWconst [c]) x a) && isPowerOfTwo32(c-1) && c >= 3 => (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
-(MULA (MOVWconst [c]) x a) && isPowerOfTwo32(c+1) && c >= 7 => (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
-(MULA (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo32(c/3) => (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
-(MULA (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo32(c/5) => (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
-(MULA (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo32(c/7) => (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
-(MULA (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo32(c/9) => (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+(MULA (MOVWconst [c]) x a) && isPowerOfTwo(c) => (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULA (MOVWconst [c]) x a) && isPowerOfTwo(c-1) && c >= 3 => (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULA (MOVWconst [c]) x a) && isPowerOfTwo(c+1) && c >= 7 => (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULA (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo(c/3) => (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULA (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo(c/5) => (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULA (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo(c/7) => (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULA (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo(c/9) => (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
(MULS x (MOVWconst [c]) a) && c == -1 => (ADD a x)
(MULS _ (MOVWconst [0]) a) => a
(MULS x (MOVWconst [1]) a) => (RSB x a)
-(MULS x (MOVWconst [c]) a) && isPowerOfTwo32(c) => (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
-(MULS x (MOVWconst [c]) a) && isPowerOfTwo32(c-1) && c >= 3 => (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
-(MULS x (MOVWconst [c]) a) && isPowerOfTwo32(c+1) && c >= 7 => (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
-(MULS x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo32(c/3) => (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
-(MULS x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo32(c/5) => (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
-(MULS x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo32(c/7) => (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
-(MULS x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo32(c/9) => (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+(MULS x (MOVWconst [c]) a) && isPowerOfTwo(c) => (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULS x (MOVWconst [c]) a) && isPowerOfTwo(c-1) && c >= 3 => (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULS x (MOVWconst [c]) a) && isPowerOfTwo(c+1) && c >= 7 => (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULS x (MOVWconst [c]) a) && c%3 == 0 && isPowerOfTwo(c/3) => (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULS x (MOVWconst [c]) a) && c%5 == 0 && isPowerOfTwo(c/5) => (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULS x (MOVWconst [c]) a) && c%7 == 0 && isPowerOfTwo(c/7) => (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULS x (MOVWconst [c]) a) && c%9 == 0 && isPowerOfTwo(c/9) => (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
(MULS (MOVWconst [c]) x a) && c == -1 => (ADD a x)
(MULS (MOVWconst [0]) _ a) => a
(MULS (MOVWconst [1]) x a) => (RSB x a)
-(MULS (MOVWconst [c]) x a) && isPowerOfTwo32(c) => (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
-(MULS (MOVWconst [c]) x a) && isPowerOfTwo32(c-1) && c >= 3 => (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
-(MULS (MOVWconst [c]) x a) && isPowerOfTwo32(c+1) && c >= 7 => (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
-(MULS (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo32(c/3) => (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
-(MULS (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo32(c/5) => (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
-(MULS (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo32(c/7) => (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
-(MULS (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo32(c/9) => (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
+(MULS (MOVWconst [c]) x a) && isPowerOfTwo(c) => (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
+(MULS (MOVWconst [c]) x a) && isPowerOfTwo(c-1) && c >= 3 => (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
+(MULS (MOVWconst [c]) x a) && isPowerOfTwo(c+1) && c >= 7 => (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
+(MULS (MOVWconst [c]) x a) && c%3 == 0 && isPowerOfTwo(c/3) => (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
+(MULS (MOVWconst [c]) x a) && c%5 == 0 && isPowerOfTwo(c/5) => (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
+(MULS (MOVWconst [c]) x a) && c%7 == 0 && isPowerOfTwo(c/7) => (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
+(MULS (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo(c/9) => (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
// div by constant
(Select0 (CALLudiv x (MOVWconst [1]))) => x
(Select1 (CALLudiv _ (MOVWconst [1]))) => (MOVWconst [0])
-(Select0 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo32(c) => (SRLconst [int32(log32(c))] x)
-(Select1 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo32(c) => (ANDconst [c-1] x)
+(Select0 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo(c) => (SRLconst [int32(log32(c))] x)
+(Select1 (CALLudiv x (MOVWconst [c]))) && isPowerOfTwo(c) => (ANDconst [c-1] x)
// constant comparisons
(CMPconst (MOVWconst [x]) [y]) => (FlagConstant [subFlags32(x,y)])
(MUL x (MOVDconst [-1])) => (NEG x)
(MUL _ (MOVDconst [0])) => (MOVDconst [0])
(MUL x (MOVDconst [1])) => x
-(MUL x (MOVDconst [c])) && isPowerOfTwo64(c) => (SLLconst [log64(c)] x)
-(MUL x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c >= 3 => (ADDshiftLL x x [log64(c-1)])
-(MUL x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c >= 7 => (ADDshiftLL (NEG <x.Type> x) x [log64(c+1)])
-(MUL x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (SLLconst [log64(c/3)] (ADDshiftLL <x.Type> x x [1]))
-(MUL x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (SLLconst [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))
-(MUL x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (SLLconst [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
-(MUL x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (SLLconst [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))
+(MUL x (MOVDconst [c])) && isPowerOfTwo(c) => (SLLconst [log64(c)] x)
+(MUL x (MOVDconst [c])) && isPowerOfTwo(c-1) && c >= 3 => (ADDshiftLL x x [log64(c-1)])
+(MUL x (MOVDconst [c])) && isPowerOfTwo(c+1) && c >= 7 => (ADDshiftLL (NEG <x.Type> x) x [log64(c+1)])
+(MUL x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (SLLconst [log64(c/3)] (ADDshiftLL <x.Type> x x [1]))
+(MUL x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (SLLconst [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))
+(MUL x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (SLLconst [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
+(MUL x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (SLLconst [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))
(MULW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (NEG <x.Type> x))
(MULW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
(MULW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg x)
-(MULW x (MOVDconst [c])) && isPowerOfTwo64(c) => (MOVWUreg (SLLconst <x.Type> [log64(c)] x))
-(MULW x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c) >= 3 => (MOVWUreg (ADDshiftLL <x.Type> x x [log64(c-1)]))
-(MULW x (MOVDconst [c])) && isPowerOfTwo64(c+1) && int32(c) >= 7 => (MOVWUreg (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
-(MULW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (ADDshiftLL <x.Type> x x [1])))
-(MULW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
-(MULW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
-(MULW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
+(MULW x (MOVDconst [c])) && isPowerOfTwo(c) => (MOVWUreg (SLLconst <x.Type> [log64(c)] x))
+(MULW x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c) >= 3 => (MOVWUreg (ADDshiftLL <x.Type> x x [log64(c-1)]))
+(MULW x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c) >= 7 => (MOVWUreg (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
+(MULW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (ADDshiftLL <x.Type> x x [1])))
+(MULW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
+(MULW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
+(MULW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
// mneg by constant
(MNEG x (MOVDconst [-1])) => x
(MNEG _ (MOVDconst [0])) => (MOVDconst [0])
(MNEG x (MOVDconst [1])) => (NEG x)
-(MNEG x (MOVDconst [c])) && isPowerOfTwo64(c) => (NEG (SLLconst <x.Type> [log64(c)] x))
-(MNEG x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c >= 3 => (NEG (ADDshiftLL <x.Type> x x [log64(c-1)]))
-(MNEG x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c >= 7 => (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
-(MNEG x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2]))
-(MNEG x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (NEG (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
-(MNEG x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3]))
-(MNEG x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (NEG (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
+(MNEG x (MOVDconst [c])) && isPowerOfTwo(c) => (NEG (SLLconst <x.Type> [log64(c)] x))
+(MNEG x (MOVDconst [c])) && isPowerOfTwo(c-1) && c >= 3 => (NEG (ADDshiftLL <x.Type> x x [log64(c-1)]))
+(MNEG x (MOVDconst [c])) && isPowerOfTwo(c+1) && c >= 7 => (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
+(MNEG x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2]))
+(MNEG x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (NEG (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
+(MNEG x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3]))
+(MNEG x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (NEG (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
(MNEGW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg x)
(MNEGW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
(MNEGW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (NEG <x.Type> x))
-(MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c) => (NEG (SLLconst <x.Type> [log64(c)] x))
-(MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c) >= 3 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> x x [log64(c-1)])))
-(MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c+1) && int32(c) >= 7 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)])))
-(MNEGW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2])))
-(MNEGW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))))
-(MNEGW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3])))
-(MNEGW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))))
+(MNEGW x (MOVDconst [c])) && isPowerOfTwo(c) => (NEG (SLLconst <x.Type> [log64(c)] x))
+(MNEGW x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c) >= 3 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> x x [log64(c-1)])))
+(MNEGW x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c) >= 7 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)])))
+(MNEGW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2])))
+(MNEGW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))))
+(MNEGW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3])))
+(MNEGW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))))
(MADD a x (MOVDconst [-1])) => (SUB a x)
(MADD a _ (MOVDconst [0])) => a
(MADD a x (MOVDconst [1])) => (ADD a x)
-(MADD a x (MOVDconst [c])) && isPowerOfTwo64(c) => (ADDshiftLL a x [log64(c)])
-(MADD a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
-(MADD a x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
-(MADD a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
-(MADD a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
-(MADD a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
-(MADD a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
+(MADD a x (MOVDconst [c])) && isPowerOfTwo(c) => (ADDshiftLL a x [log64(c)])
+(MADD a x (MOVDconst [c])) && isPowerOfTwo(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
+(MADD a x (MOVDconst [c])) && isPowerOfTwo(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
+(MADD a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
+(MADD a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
+(MADD a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
+(MADD a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
(MADD a (MOVDconst [-1]) x) => (SUB a x)
(MADD a (MOVDconst [0]) _) => a
(MADD a (MOVDconst [1]) x) => (ADD a x)
-(MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (ADDshiftLL a x [log64(c)])
-(MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
-(MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
-(MADD a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo64(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
-(MADD a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo64(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
-(MADD a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo64(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
-(MADD a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo64(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
+(MADD a (MOVDconst [c]) x) && isPowerOfTwo(c) => (ADDshiftLL a x [log64(c)])
+(MADD a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
+(MADD a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
+(MADD a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
+(MADD a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
+(MADD a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
+(MADD a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
(MADDW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x))
(MADDW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
(MADDW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x))
-(MADDW a x (MOVDconst [c])) && isPowerOfTwo
64(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
-(MADDW a x (MOVDconst [c])) && isPowerOfTwo
64(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
-(MADDW a x (MOVDconst [c])) && isPowerOfTwo
64(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
-(MADDW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo
64(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
-(MADDW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo
64(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
-(MADDW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo
64(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
-(MADDW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo
64(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
+(MADDW a x (MOVDconst [c])) && isPowerOfTwo(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
+(MADDW a x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
+(MADDW a x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
+(MADDW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
+(MADDW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
+(MADDW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
+(MADDW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
(MADDW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x))
(MADDW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a)
(MADDW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x))
-(MADDW a (MOVDconst [c]) x) && isPowerOfTwo
64(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
-(MADDW a (MOVDconst [c]) x) && isPowerOfTwo
64(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
-(MADDW a (MOVDconst [c]) x) && isPowerOfTwo
64(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
-(MADDW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo
64(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
-(MADDW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo
64(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
-(MADDW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo
64(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
-(MADDW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo
64(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
+(MADDW a (MOVDconst [c]) x) && isPowerOfTwo(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
+(MADDW a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
+(MADDW a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
+(MADDW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
+(MADDW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
+(MADDW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
+(MADDW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
(MSUB a x (MOVDconst [-1])) => (ADD a x)
(MSUB a _ (MOVDconst [0])) => a
(MSUB a x (MOVDconst [1])) => (SUB a x)
-(MSUB a x (MOVDconst [c])) && isPowerOfTwo64(c) => (SUBshiftLL a x [log64(c)])
-(MSUB a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
-(MSUB a x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
-(MSUB a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
-(MSUB a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
-(MSUB a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
-(MSUB a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
+(MSUB a x (MOVDconst [c])) && isPowerOfTwo(c) => (SUBshiftLL a x [log64(c)])
+(MSUB a x (MOVDconst [c])) && isPowerOfTwo(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
+(MSUB a x (MOVDconst [c])) && isPowerOfTwo(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
+(MSUB a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
+(MSUB a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
+(MSUB a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
+(MSUB a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
(MSUB a (MOVDconst [-1]) x) => (ADD a x)
(MSUB a (MOVDconst [0]) _) => a
(MSUB a (MOVDconst [1]) x) => (SUB a x)
-(MSUB a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (SUBshiftLL a x [log64(c)])
-(MSUB a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
-(MSUB a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
-(MSUB a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo64(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
-(MSUB a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo64(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
-(MSUB a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo64(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
-(MSUB a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo64(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
+(MSUB a (MOVDconst [c]) x) && isPowerOfTwo(c) => (SUBshiftLL a x [log64(c)])
+(MSUB a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
+(MSUB a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
+(MSUB a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
+(MSUB a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
+(MSUB a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
+(MSUB a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
(MSUBW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
(MSUBW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
(MSUBW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
-(MSUBW a x (MOVDconst [c])) && isPowerOfTwo
64(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
-(MSUBW a x (MOVDconst [c])) && isPowerOfTwo
64(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
-(MSUBW a x (MOVDconst [c])) && isPowerOfTwo
64(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
-(MSUBW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo
64(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
-(MSUBW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo
64(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
-(MSUBW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo
64(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
-(MSUBW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo
64(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
+(MSUBW a x (MOVDconst [c])) && isPowerOfTwo(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
+(MSUBW a x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
+(MSUBW a x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
+(MSUBW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
+(MSUBW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
+(MSUBW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
+(MSUBW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
(MSUBW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
(MSUBW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a)
(MSUBW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
-(MSUBW a (MOVDconst [c]) x) && isPowerOfTwo
64(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
-(MSUBW a (MOVDconst [c]) x) && isPowerOfTwo
64(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
-(MSUBW a (MOVDconst [c]) x) && isPowerOfTwo
64(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
-(MSUBW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo
64(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
-(MSUBW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo
64(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
-(MSUBW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo
64(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
-(MSUBW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo
64(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
+(MSUBW a (MOVDconst [c]) x) && isPowerOfTwo(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
+(MSUBW a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
+(MSUBW a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
+(MSUBW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
+(MSUBW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
+(MSUBW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
+(MSUBW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
// div by constant
(UDIV x (MOVDconst [1])) => x
-(UDIV x (MOVDconst [c])) && isPowerOfTwo64(c) => (SRLconst [log64(c)] x)
+(UDIV x (MOVDconst [c])) && isPowerOfTwo(c) => (SRLconst [log64(c)] x)
(UDIVW x (MOVDconst [c])) && uint32(c)==1 => (MOVWUreg x)
-(UDIVW x (MOVDconst [c])) && isPowerOfTwo64(c) && is32Bit(c) => (SRLconst [log64(c)] (MOVWUreg <v.Type> x))
+(UDIVW x (MOVDconst [c])) && isPowerOfTwo(c) && is32Bit(c) => (SRLconst [log64(c)] (MOVWUreg <v.Type> x))
(UMOD _ (MOVDconst [1])) => (MOVDconst [0])
-(UMOD x (MOVDconst [c])) && isPowerOfTwo64(c) => (ANDconst [c-1] x)
+(UMOD x (MOVDconst [c])) && isPowerOfTwo(c) => (ANDconst [c-1] x)
(UMODW _ (MOVDconst [c])) && uint32(c)==1 => (MOVDconst [0])
-(UMODW x (MOVDconst [c])) && isPowerOfTwo64(c) && is32Bit(c) => (ANDconst [c-1] x)
+(UMODW x (MOVDconst [c])) && isPowerOfTwo(c) && is32Bit(c) => (ANDconst [c-1] x)
// generic simplifications
(ADD x (NEG y)) => (SUB x y)
(MULV x (MOVVconst [-1])) => (NEGV x)
(MULV _ (MOVVconst [0])) => (MOVVconst [0])
(MULV x (MOVVconst [1])) => x
-(MULV x (MOVVconst [c])) && isPowerOfTwo64(c) => (SLLVconst [log64(c)] x)
+(MULV x (MOVVconst [c])) && isPowerOfTwo(c) => (SLLVconst [log64(c)] x)
// div by constant
(DIVVU x (MOVVconst [1])) => x
-(DIVVU x (MOVVconst [c])) && isPowerOfTwo64(c) => (SRLVconst [log64(c)] x)
+(DIVVU x (MOVVconst [c])) && isPowerOfTwo(c) => (SRLVconst [log64(c)] x)
(REMVU _ (MOVVconst [1])) => (MOVVconst [0]) // mod
-(REMVU x (MOVVconst [c])) && isPowerOfTwo64(c) => (ANDconst [c-1] x) // mod
+(REMVU x (MOVVconst [c])) && isPowerOfTwo(c) => (ANDconst [c-1] x) // mod
// generic simplifications
(ADDV x (NEGV y)) => (SUBV x y)
(Select0 (MULTU (MOVWconst [1]) _ )) => (MOVWconst [0])
(Select1 (MULTU (MOVWconst [-1]) x )) => (NEG <x.Type> x)
(Select0 (MULTU (MOVWconst [-1]) x )) => (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
-(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo64(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
-(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo64(int64(uint32(c))) => (SRLconst [int32(32-log2uint32(int64(c)))] x)
+(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
+(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) => (SRLconst [int32(32-log2uint32(int64(c)))] x)
(MUL (MOVWconst [0]) _ ) => (MOVWconst [0])
(MUL (MOVWconst [1]) x ) => x
(MUL (MOVWconst [-1]) x ) => (NEG x)
-(MUL (MOVWconst [c]) x ) && isPowerOfTwo64(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
+(MUL (MOVWconst [c]) x ) && isPowerOfTwo(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
// generic simplifications
(ADD x (NEG y)) => (SUB x y)
(Select1 (MULVU x (MOVVconst [-1]))) => (NEGV x)
(Select1 (MULVU _ (MOVVconst [0]))) => (MOVVconst [0])
(Select1 (MULVU x (MOVVconst [1]))) => x
-(Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SLLVconst [log64(c)] x)
+(Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (SLLVconst [log64(c)] x)
// div by constant
(Select1 (DIVVU x (MOVVconst [1]))) => x
-(Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SRLVconst [log64(c)] x)
+(Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (SRLVconst [log64(c)] x)
(Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod
-(Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (ANDconst [c-1] x) // mod
+(Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (ANDconst [c-1] x) // mod
// generic simplifications
(ADDV x (NEGV y)) => (SUBV x y)
//
// Notes:
// - the generic rules have already matched single powers of two so we ignore them here
-// - isPowerOfTwo32 asserts that its argument is greater than 0
+// - isPowerOfTwo asserts that its argument is greater than 0
// - c&(c-1) = clear rightmost bit
// - c&^(c-1) = isolate rightmost bit
// c = 2ˣ + 2ʸ => c - 2ˣ = 2ʸ
-(MULL(D|W)const <t> x [c]) && isPowerOfTwo32(c&(c-1))
+(MULL(D|W)const <t> x [c]) && isPowerOfTwo(c&(c-1))
=> ((ADD|ADDW) (SL(D|W)const <t> x [uint8(log32(c&(c-1)))])
(SL(D|W)const <t> x [uint8(log32(c&^(c-1)))]))
// c = 2ʸ - 2ˣ => c + 2ˣ = 2ʸ
-(MULL(D|W)const <t> x [c]) && isPowerOfTwo32(c+(c&^(c-1)))
+(MULL(D|W)const <t> x [c]) && isPowerOfTwo(c+(c&^(c-1)))
=> ((SUB|SUBW) (SL(D|W)const <t> x [uint8(log32(c+(c&^(c-1))))])
(SL(D|W)const <t> x [uint8(log32(c&^(c-1)))]))
// c = 2ˣ - 2ʸ => -c + 2ˣ = 2ʸ
-(MULL(D|W)const <t> x [c]) && isPowerOfTwo32(-c+(-c&^(-c-1)))
+(MULL(D|W)const <t> x [c]) && isPowerOfTwo(-c+(-c&^(-c-1)))
=> ((SUB|SUBW) (SL(D|W)const <t> x [uint8(log32(-c&^(-c-1)))])
(SL(D|W)const <t> x [uint8(log32(-c+(-c&^(-c-1))))]))
(Or(8|16|32|64) <t> (Com(8|16|32|64) x) (Com(8|16|32|64) y)) => (Com(8|16|32|64) (And(8|16|32|64) <t> x y))
// Convert multiplication by a power of two to a shift.
-(Mul8 <t> n (Const8 [c])) && isPowerOfTwo8(c) => (Lsh8x64 <t> n (Const64 <typ.UInt64> [log8(c)]))
-(Mul16 <t> n (Const16 [c])) && isPowerOfTwo16(c) => (Lsh16x64 <t> n (Const64 <typ.UInt64> [log16(c)]))
-(Mul32 <t> n (Const32 [c])) && isPowerOfTwo32(c) => (Lsh32x64 <t> n (Const64 <typ.UInt64> [log32(c)]))
-(Mul64 <t> n (Const64 [c])) && isPowerOfTwo64(c) => (Lsh64x64 <t> n (Const64 <typ.UInt64> [log64(c)]))
-(Mul8 <t> n (Const8 [c])) && t.IsSigned() && isPowerOfTwo8(-c) => (Neg8 (Lsh8x64 <t> n (Const64 <typ.UInt64> [log8(-c)])))
-(Mul16 <t> n (Const16 [c])) && t.IsSigned() && isPowerOfTwo16(-c) => (Neg16 (Lsh16x64 <t> n (Const64 <typ.UInt64> [log16(-c)])))
-(Mul32 <t> n (Const32 [c])) && t.IsSigned() && isPowerOfTwo32(-c) => (Neg32 (Lsh32x64 <t> n (Const64 <typ.UInt64> [log32(-c)])))
-(Mul64 <t> n (Const64 [c])) && t.IsSigned() && isPowerOfTwo64(-c) => (Neg64 (Lsh64x64 <t> n (Const64 <typ.UInt64> [log64(-c)])))
+(Mul8 <t> n (Const8 [c])) && isPowerOfTwo(c) => (Lsh8x64 <t> n (Const64 <typ.UInt64> [log8(c)]))
+(Mul16 <t> n (Const16 [c])) && isPowerOfTwo(c) => (Lsh16x64 <t> n (Const64 <typ.UInt64> [log16(c)]))
+(Mul32 <t> n (Const32 [c])) && isPowerOfTwo(c) => (Lsh32x64 <t> n (Const64 <typ.UInt64> [log32(c)]))
+(Mul64 <t> n (Const64 [c])) && isPowerOfTwo(c) => (Lsh64x64 <t> n (Const64 <typ.UInt64> [log64(c)]))
+(Mul8 <t> n (Const8 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg8 (Lsh8x64 <t> n (Const64 <typ.UInt64> [log8(-c)])))
+(Mul16 <t> n (Const16 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg16 (Lsh16x64 <t> n (Const64 <typ.UInt64> [log16(-c)])))
+(Mul32 <t> n (Const32 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg32 (Lsh32x64 <t> n (Const64 <typ.UInt64> [log32(-c)])))
+(Mul64 <t> n (Const64 [c])) && t.IsSigned() && isPowerOfTwo(-c) => (Neg64 (Lsh64x64 <t> n (Const64 <typ.UInt64> [log64(-c)])))
(Mod8 (Const8 [c]) (Const8 [d])) && d != 0 => (Const8 [c % d])
(Mod16 (Const16 [c]) (Const16 [d])) && d != 0 => (Const16 [c % d])
// See ../magic.go for a detailed description of these algorithms.
// Unsigned divide by power of 2. Strength reduce to a shift.
-(Div8u n (Const8 [c])) && isPowerOfTwo8(c) => (Rsh8Ux64 n (Const64 <typ.UInt64> [log8(c)]))
-(Div16u n (Const16 [c])) && isPowerOfTwo16(c) => (Rsh16Ux64 n (Const64 <typ.UInt64> [log16(c)]))
-(Div32u n (Const32 [c])) && isPowerOfTwo32(c) => (Rsh32Ux64 n (Const64 <typ.UInt64> [log32(c)]))
-(Div64u n (Const64 [c])) && isPowerOfTwo64(c) => (Rsh64Ux64 n (Const64 <typ.UInt64> [log64(c)]))
+(Div8u n (Const8 [c])) && isPowerOfTwo(c) => (Rsh8Ux64 n (Const64 <typ.UInt64> [log8(c)]))
+(Div16u n (Const16 [c])) && isPowerOfTwo(c) => (Rsh16Ux64 n (Const64 <typ.UInt64> [log16(c)]))
+(Div32u n (Const32 [c])) && isPowerOfTwo(c) => (Rsh32Ux64 n (Const64 <typ.UInt64> [log32(c)]))
+(Div64u n (Const64 [c])) && isPowerOfTwo(c) => (Rsh64Ux64 n (Const64 <typ.UInt64> [log64(c)]))
(Div64u n (Const64 [-1<<63])) => (Rsh64Ux64 n (Const64 <typ.UInt64> [63]))
// Signed non-negative divide by power of 2.
-(Div8 n (Const8 [c])) && isNonNegative(n) && isPowerOfTwo8(c) => (Rsh8Ux64 n (Const64 <typ.UInt64> [log8(c)]))
-(Div16 n (Const16 [c])) && isNonNegative(n) && isPowerOfTwo16(c) => (Rsh16Ux64 n (Const64 <typ.UInt64> [log16(c)]))
-(Div32 n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo32(c) => (Rsh32Ux64 n (Const64 <typ.UInt64> [log32(c)]))
-(Div64 n (Const64 [c])) && isNonNegative(n) && isPowerOfTwo64(c) => (Rsh64Ux64 n (Const64 <typ.UInt64> [log64(c)]))
+(Div8 n (Const8 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh8Ux64 n (Const64 <typ.UInt64> [log8(c)]))
+(Div16 n (Const16 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh16Ux64 n (Const64 <typ.UInt64> [log16(c)]))
+(Div32 n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh32Ux64 n (Const64 <typ.UInt64> [log32(c)]))
+(Div64 n (Const64 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (Rsh64Ux64 n (Const64 <typ.UInt64> [log64(c)]))
(Div64 n (Const64 [-1<<63])) && isNonNegative(n) => (Const64 [0])
// Unsigned divide, not a power of 2. Strength reduce to a multiply.
// n / c = n >> log(c) if n >= 0
// = (n+c-1) >> log(c) if n < 0
// We conditionally add c-1 by adding n>>63>>(64-log(c)) (first shift signed, second shift unsigned).
-(Div8 <t> n (Const8 [c])) && isPowerOfTwo8(c) =>
+(Div8 <t> n (Const8 [c])) && isPowerOfTwo(c) =>
(Rsh8x64
(Add8 <t> n (Rsh8Ux64 <t> (Rsh8x64 <t> n (Const64 <typ.UInt64> [ 7])) (Const64 <typ.UInt64> [int64( 8-log8(c))])))
(Const64 <typ.UInt64> [int64(log8(c))]))
-(Div16 <t> n (Const16 [c])) && isPowerOfTwo16(c) =>
+(Div16 <t> n (Const16 [c])) && isPowerOfTwo(c) =>
(Rsh16x64
(Add16 <t> n (Rsh16Ux64 <t> (Rsh16x64 <t> n (Const64 <typ.UInt64> [15])) (Const64 <typ.UInt64> [int64(16-log16(c))])))
(Const64 <typ.UInt64> [int64(log16(c))]))
-(Div32 <t> n (Const32 [c])) && isPowerOfTwo32(c) =>
+(Div32 <t> n (Const32 [c])) && isPowerOfTwo(c) =>
(Rsh32x64
(Add32 <t> n (Rsh32Ux64 <t> (Rsh32x64 <t> n (Const64 <typ.UInt64> [31])) (Const64 <typ.UInt64> [int64(32-log32(c))])))
(Const64 <typ.UInt64> [int64(log32(c))]))
-(Div64 <t> n (Const64 [c])) && isPowerOfTwo64(c) =>
+(Div64 <t> n (Const64 [c])) && isPowerOfTwo(c) =>
(Rsh64x64
(Add64 <t> n (Rsh64Ux64 <t> (Rsh64x64 <t> n (Const64 <typ.UInt64> [63])) (Const64 <typ.UInt64> [int64(64-log64(c))])))
(Const64 <typ.UInt64> [int64(log64(c))]))
(Const64 <typ.UInt64> [63])))
// Unsigned mod by power of 2 constant.
-(Mod8u <t> n (Const8 [c])) && isPowerOfTwo8(c) => (And8 n (Const8 <t> [c-1]))
-(Mod16u <t> n (Const16 [c])) && isPowerOfTwo16(c) => (And16 n (Const16 <t> [c-1]))
-(Mod32u <t> n (Const32 [c])) && isPowerOfTwo32(c) => (And32 n (Const32 <t> [c-1]))
-(Mod64u <t> n (Const64 [c])) && isPowerOfTwo64(c) => (And64 n (Const64 <t> [c-1]))
+(Mod8u <t> n (Const8 [c])) && isPowerOfTwo(c) => (And8 n (Const8 <t> [c-1]))
+(Mod16u <t> n (Const16 [c])) && isPowerOfTwo(c) => (And16 n (Const16 <t> [c-1]))
+(Mod32u <t> n (Const32 [c])) && isPowerOfTwo(c) => (And32 n (Const32 <t> [c-1]))
+(Mod64u <t> n (Const64 [c])) && isPowerOfTwo(c) => (And64 n (Const64 <t> [c-1]))
(Mod64u <t> n (Const64 [-1<<63])) => (And64 n (Const64 <t> [1<<63-1]))
// Signed non-negative mod by power of 2 constant.
-(Mod8 <t> n (Const8 [c])) && isNonNegative(n) && isPowerOfTwo8(c) => (And8 n (Const8 <t> [c-1]))
-(Mod16 <t> n (Const16 [c])) && isNonNegative(n) && isPowerOfTwo16(c) => (And16 n (Const16 <t> [c-1]))
-(Mod32 <t> n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo32(c) => (And32 n (Const32 <t> [c-1]))
-(Mod64 <t> n (Const64 [c])) && isNonNegative(n) && isPowerOfTwo64(c) => (And64 n (Const64 <t> [c-1]))
+(Mod8 <t> n (Const8 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And8 n (Const8 <t> [c-1]))
+(Mod16 <t> n (Const16 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And16 n (Const16 <t> [c-1]))
+(Mod32 <t> n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And32 n (Const32 <t> [c-1]))
+(Mod64 <t> n (Const64 [c])) && isNonNegative(n) && isPowerOfTwo(c) => (And64 n (Const64 <t> [c-1]))
(Mod64 n (Const64 [-1<<63])) && isNonNegative(n) => n
// Signed mod by negative constant.
}
// isPowerOfTwoX functions report whether n is a power of 2.
-func isPowerOfTwo8(n int8) bool {
- return n > 0 && n&(n-1) == 0
-}
-func isPowerOfTwo16(n int16) bool {
- return n > 0 && n&(n-1) == 0
-}
-func isPowerOfTwo32(n int32) bool {
- return n > 0 && n&(n-1) == 0
-}
-func isPowerOfTwo64(n int64) bool {
+func isPowerOfTwo[T int8 | int16 | int32 | int64](n T) bool {
return n > 0 && n&(n-1) == 0
}
// checks if mask >> rshift applied at lsb is a valid arm64 bitfield op mask.
func isARM64BFMask(lsb, mask, rshift int64) bool {
shiftedMask := int64(uint64(mask) >> uint64(rshift))
- return shiftedMask != 0 && isPowerOfTwo64(shiftedMask+1) && nto(shiftedMask)+lsb < 64
+ return shiftedMask != 0 && isPowerOfTwo(shiftedMask+1) && nto(shiftedMask)+lsb < 64
}
// returns the bitfield width of mask >> rshift for arm64 bitfield ops.
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c+1) && c >= 15
+ // cond: isPowerOfTwo(c+1) && c >= 15
// result: (SUBL (SHLLconst <v.Type> [int32(log32(c+1))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c+1) && c >= 15) {
+ if !(isPowerOfTwo(c+1) && c >= 15) {
break
}
v.reset(Op386SUBL)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-1) && c >= 17
+ // cond: isPowerOfTwo(c-1) && c >= 17
// result: (LEAL1 (SHLLconst <v.Type> [int32(log32(c-1))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-1) && c >= 17) {
+ if !(isPowerOfTwo(c-1) && c >= 17) {
break
}
v.reset(Op386LEAL1)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-2) && c >= 34
+ // cond: isPowerOfTwo(c-2) && c >= 34
// result: (LEAL2 (SHLLconst <v.Type> [int32(log32(c-2))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-2) && c >= 34) {
+ if !(isPowerOfTwo(c-2) && c >= 34) {
break
}
v.reset(Op386LEAL2)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-4) && c >= 68
+ // cond: isPowerOfTwo(c-4) && c >= 68
// result: (LEAL4 (SHLLconst <v.Type> [int32(log32(c-4))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-4) && c >= 68) {
+ if !(isPowerOfTwo(c-4) && c >= 68) {
break
}
v.reset(Op386LEAL4)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-8) && c >= 136
+ // cond: isPowerOfTwo(c-8) && c >= 136
// result: (LEAL8 (SHLLconst <v.Type> [int32(log32(c-8))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-8) && c >= 136) {
+ if !(isPowerOfTwo(c-8) && c >= 136) {
break
}
v.reset(Op386LEAL8)
return true
}
// match: (MULLconst [c] x)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SHLLconst [int32(log32(c/3))] (LEAL2 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(Op386SHLLconst)
return true
}
// match: (MULLconst [c] x)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SHLLconst [int32(log32(c/5))] (LEAL4 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(Op386SHLLconst)
return true
}
// match: (MULLconst [c] x)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SHLLconst [int32(log32(c/9))] (LEAL8 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(Op386SHLLconst)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo64(int64(c)+1) && c >= 15
+ // cond: isPowerOfTwo(int64(c)+1) && c >= 15
// result: (SUBL (SHLLconst <v.Type> [int8(log64(int64(c)+1))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo64(int64(c)+1) && c >= 15) {
+ if !(isPowerOfTwo(int64(c)+1) && c >= 15) {
break
}
v.reset(OpAMD64SUBL)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-1) && c >= 17
+ // cond: isPowerOfTwo(c-1) && c >= 17
// result: (LEAL1 (SHLLconst <v.Type> [int8(log32(c-1))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-1) && c >= 17) {
+ if !(isPowerOfTwo(c-1) && c >= 17) {
break
}
v.reset(OpAMD64LEAL1)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-2) && c >= 34
+ // cond: isPowerOfTwo(c-2) && c >= 34
// result: (LEAL2 (SHLLconst <v.Type> [int8(log32(c-2))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-2) && c >= 34) {
+ if !(isPowerOfTwo(c-2) && c >= 34) {
break
}
v.reset(OpAMD64LEAL2)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-4) && c >= 68
+ // cond: isPowerOfTwo(c-4) && c >= 68
// result: (LEAL4 (SHLLconst <v.Type> [int8(log32(c-4))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-4) && c >= 68) {
+ if !(isPowerOfTwo(c-4) && c >= 68) {
break
}
v.reset(OpAMD64LEAL4)
return true
}
// match: (MULLconst [c] x)
- // cond: isPowerOfTwo32(c-8) && c >= 136
+ // cond: isPowerOfTwo(c-8) && c >= 136
// result: (LEAL8 (SHLLconst <v.Type> [int8(log32(c-8))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-8) && c >= 136) {
+ if !(isPowerOfTwo(c-8) && c >= 136) {
break
}
v.reset(OpAMD64LEAL8)
return true
}
// match: (MULLconst [c] x)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SHLLconst [int8(log32(c/3))] (LEAL2 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpAMD64SHLLconst)
return true
}
// match: (MULLconst [c] x)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SHLLconst [int8(log32(c/5))] (LEAL4 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpAMD64SHLLconst)
return true
}
// match: (MULLconst [c] x)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SHLLconst [int8(log32(c/9))] (LEAL8 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpAMD64SHLLconst)
return true
}
// match: (MULQconst [c] x)
- // cond: isPowerOfTwo64(int64(c)+1) && c >= 15
+ // cond: isPowerOfTwo(int64(c)+1) && c >= 15
// result: (SUBQ (SHLQconst <v.Type> [int8(log64(int64(c)+1))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo64(int64(c)+1) && c >= 15) {
+ if !(isPowerOfTwo(int64(c)+1) && c >= 15) {
break
}
v.reset(OpAMD64SUBQ)
return true
}
// match: (MULQconst [c] x)
- // cond: isPowerOfTwo32(c-1) && c >= 17
+ // cond: isPowerOfTwo(c-1) && c >= 17
// result: (LEAQ1 (SHLQconst <v.Type> [int8(log32(c-1))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-1) && c >= 17) {
+ if !(isPowerOfTwo(c-1) && c >= 17) {
break
}
v.reset(OpAMD64LEAQ1)
return true
}
// match: (MULQconst [c] x)
- // cond: isPowerOfTwo32(c-2) && c >= 34
+ // cond: isPowerOfTwo(c-2) && c >= 34
// result: (LEAQ2 (SHLQconst <v.Type> [int8(log32(c-2))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-2) && c >= 34) {
+ if !(isPowerOfTwo(c-2) && c >= 34) {
break
}
v.reset(OpAMD64LEAQ2)
return true
}
// match: (MULQconst [c] x)
- // cond: isPowerOfTwo32(c-4) && c >= 68
+ // cond: isPowerOfTwo(c-4) && c >= 68
// result: (LEAQ4 (SHLQconst <v.Type> [int8(log32(c-4))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-4) && c >= 68) {
+ if !(isPowerOfTwo(c-4) && c >= 68) {
break
}
v.reset(OpAMD64LEAQ4)
return true
}
// match: (MULQconst [c] x)
- // cond: isPowerOfTwo32(c-8) && c >= 136
+ // cond: isPowerOfTwo(c-8) && c >= 136
// result: (LEAQ8 (SHLQconst <v.Type> [int8(log32(c-8))] x) x)
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c-8) && c >= 136) {
+ if !(isPowerOfTwo(c-8) && c >= 136) {
break
}
v.reset(OpAMD64LEAQ8)
return true
}
// match: (MULQconst [c] x)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SHLQconst [int8(log32(c/3))] (LEAQ2 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpAMD64SHLQconst)
return true
}
// match: (MULQconst [c] x)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SHLQconst [int8(log32(c/5))] (LEAQ4 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpAMD64SHLQconst)
return true
}
// match: (MULQconst [c] x)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SHLQconst [int8(log32(c/9))] (LEAQ8 <v.Type> x x))
for {
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpAMD64SHLQconst)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (SLLconst [int32(log32(c))] x)
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpARMSLLconst)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: isPowerOfTwo32(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (ADDshiftLL x x [int32(log32(c-1))])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
continue
}
v.reset(OpARMADDshiftLL)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: isPowerOfTwo32(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (RSBshiftLL x x [int32(log32(c+1))])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
continue
}
v.reset(OpARMRSBshiftLL)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SLLconst [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
continue
}
v.reset(OpARMSLLconst)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SLLconst [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
continue
}
v.reset(OpARMSLLconst)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (SLLconst [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
continue
}
v.reset(OpARMSLLconst)
break
}
// match: (MUL x (MOVWconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SLLconst [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
continue
}
v.reset(OpARMSLLconst)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: isPowerOfTwo32(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo32(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: isPowerOfTwo32(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo32(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA x (MOVWconst [c]) a)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (ADD (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: isPowerOfTwo32(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (ADD (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo32(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: isPowerOfTwo32(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (ADD (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo32(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULA (MOVWconst [c]) x a)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (ADD (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARMADD)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: isPowerOfTwo32(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo32(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: isPowerOfTwo32(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(isPowerOfTwo32(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS x (MOVWconst [c]) a)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
x := v_0
}
c := auxIntToInt32(v_1.AuxInt)
a := v_2
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (RSB (SLLconst <x.Type> [int32(log32(c))] x) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: isPowerOfTwo32(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (RSB (ADDshiftLL <x.Type> x x [int32(log32(c-1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo32(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: isPowerOfTwo32(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (RSB (RSBshiftLL <x.Type> x x [int32(log32(c+1))]) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(isPowerOfTwo32(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%3 == 0 && isPowerOfTwo32(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/3))] (ADDshiftLL <x.Type> x x [1])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%3 == 0 && isPowerOfTwo32(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%5 == 0 && isPowerOfTwo32(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/5))] (ADDshiftLL <x.Type> x x [2])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%5 == 0 && isPowerOfTwo32(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%7 == 0 && isPowerOfTwo32(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/7))] (RSBshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%7 == 0 && isPowerOfTwo32(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (MULS (MOVWconst [c]) x a)
- // cond: c%9 == 0 && isPowerOfTwo32(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (RSB (SLLconst <x.Type> [int32(log32(c/9))] (ADDshiftLL <x.Type> x x [3])) a)
for {
if v_0.Op != OpARMMOVWconst {
c := auxIntToInt32(v_0.AuxInt)
x := v_1
a := v_2
- if !(c%9 == 0 && isPowerOfTwo32(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARMRSB)
return true
}
// match: (Select0 (CALLudiv x (MOVWconst [c])))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (SRLconst [int32(log32(c))] x)
for {
if v_0.Op != OpARMCALLudiv {
break
}
c := auxIntToInt32(v_0_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARMSRLconst)
return true
}
// match: (Select1 (CALLudiv x (MOVWconst [c])))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (ANDconst [c-1] x)
for {
if v_0.Op != OpARMCALLudiv {
break
}
c := auxIntToInt32(v_0_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARMANDconst)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (ADDshiftLL a x [log64(c)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && c>=3
+ // cond: isPowerOfTwo(c-1) && c>=3
// result: (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARM64ADD)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && c>=7
+ // cond: isPowerOfTwo(c+1) && c>=7
// result: (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARM64SUB)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MADD a x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (ADDshiftLL a x [log64(c)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c-1) && c>=3
+ // cond: isPowerOfTwo(c-1) && c>=3
// result: (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARM64ADD)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c+1) && c>=7
+ // cond: isPowerOfTwo(c+1) && c>=7
// result: (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARM64SUB)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: c%3 == 0 && isPowerOfTwo64(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%3 == 0 && isPowerOfTwo64(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: c%5 == 0 && isPowerOfTwo64(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%5 == 0 && isPowerOfTwo64(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: c%7 == 0 && isPowerOfTwo64(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%7 == 0 && isPowerOfTwo64(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MADD a (MOVDconst [c]) x)
- // cond: c%9 == 0 && isPowerOfTwo64(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%9 == 0 && isPowerOfTwo64(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && int32(c)>=3
+ // cond: isPowerOfTwo(c-1) && int32(c)>=3
// result: (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && int32(c)>=7
+ // cond: isPowerOfTwo(c+1) && int32(c)>=7
// result: (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c-1) && int32(c)>=3
+ // cond: isPowerOfTwo(c-1) && int32(c)>=3
// result: (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c+1) && int32(c)>=7
+ // cond: isPowerOfTwo(c+1) && int32(c)>=7
// result: (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MADDW a (MOVDconst [c]) x)
- // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (NEG (SLLconst <x.Type> [log64(c)] x))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpARM64NEG)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (NEG (ADDshiftLL <x.Type> x x [log64(c-1)]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
continue
}
v.reset(OpARM64NEG)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
continue
}
v.reset(OpARM64NEG)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (NEG (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
continue
}
v.reset(OpARM64NEG)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MNEG x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (NEG (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
continue
}
v.reset(OpARM64NEG)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (NEG (SLLconst <x.Type> [log64(c)] x))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpARM64NEG)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && int32(c) >= 3
+ // cond: isPowerOfTwo(c-1) && int32(c) >= 3
// result: (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> x x [log64(c-1)])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && int32(c) >= 7
+ // cond: isPowerOfTwo(c+1) && int32(c) >= 7
// result: (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
// result: (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MNEGW x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
// result: (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SUBshiftLL a x [log64(c)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && c>=3
+ // cond: isPowerOfTwo(c-1) && c>=3
// result: (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARM64SUB)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && c>=7
+ // cond: isPowerOfTwo(c+1) && c>=7
// result: (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARM64ADD)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MSUB a x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SUBshiftLL a x [log64(c)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c-1) && c>=3
+ // cond: isPowerOfTwo(c-1) && c>=3
// result: (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
break
}
v.reset(OpARM64SUB)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c+1) && c>=7
+ // cond: isPowerOfTwo(c+1) && c>=7
// result: (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
break
}
v.reset(OpARM64ADD)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: c%3 == 0 && isPowerOfTwo64(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%3 == 0 && isPowerOfTwo64(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: c%5 == 0 && isPowerOfTwo64(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%5 == 0 && isPowerOfTwo64(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: c%7 == 0 && isPowerOfTwo64(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%7 == 0 && isPowerOfTwo64(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
break
}
v.reset(OpARM64ADDshiftLL)
return true
}
// match: (MSUB a (MOVDconst [c]) x)
- // cond: c%9 == 0 && isPowerOfTwo64(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%9 == 0 && isPowerOfTwo64(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
break
}
v.reset(OpARM64SUBshiftLL)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && int32(c)>=3
+ // cond: isPowerOfTwo(c-1) && int32(c)>=3
// result: (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && int32(c)>=7
+ // cond: isPowerOfTwo(c+1) && int32(c)>=7
// result: (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(isPowerOfTwo64(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
for {
a := v_0
break
}
c := auxIntToInt64(v_2.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c-1) && int32(c)>=3
+ // cond: isPowerOfTwo(c-1) && int32(c)>=3
// result: (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: isPowerOfTwo64(c+1) && int32(c)>=7
+ // cond: isPowerOfTwo(c+1) && int32(c)>=7
// result: (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(isPowerOfTwo64(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
// result: (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (MSUBW a (MOVDconst [c]) x)
- // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
// result: (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
for {
a := v_0
}
c := auxIntToInt64(v_1.AuxInt)
x := v_2
- if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
break
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SLLconst [log64(c)] x)
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && c >= 3
+ // cond: isPowerOfTwo(c-1) && c >= 3
// result: (ADDshiftLL x x [log64(c-1)])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c-1) && c >= 3) {
+ if !(isPowerOfTwo(c-1) && c >= 3) {
continue
}
v.reset(OpARM64ADDshiftLL)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && c >= 7
+ // cond: isPowerOfTwo(c+1) && c >= 7
// result: (ADDshiftLL (NEG <x.Type> x) x [log64(c+1)])
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c+1) && c >= 7) {
+ if !(isPowerOfTwo(c+1) && c >= 7) {
continue
}
v.reset(OpARM64ADDshiftLL)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3)
// result: (SLLconst [log64(c/3)] (ADDshiftLL <x.Type> x x [1]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5)
// result: (SLLconst [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7)
// result: (SLLconst [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MUL x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9)
// result: (SLLconst [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9)) {
continue
}
v.reset(OpARM64SLLconst)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c)] x))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c-1) && int32(c) >= 3
+ // cond: isPowerOfTwo(c-1) && int32(c) >= 3
// result: (MOVWUreg (ADDshiftLL <x.Type> x x [log64(c-1)]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c-1) && int32(c) >= 3) {
+ if !(isPowerOfTwo(c-1) && int32(c) >= 3) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c+1) && int32(c) >= 7
+ // cond: isPowerOfTwo(c+1) && int32(c) >= 7
// result: (MOVWUreg (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c+1) && int32(c) >= 7) {
+ if !(isPowerOfTwo(c+1) && int32(c) >= 7) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)
+ // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (ADDshiftLL <x.Type> x x [1])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) {
+ if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)
+ // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) {
+ if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)
+ // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) {
+ if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
break
}
// match: (MULW x (MOVDconst [c]))
- // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)
+ // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)
// result: (MOVWUreg (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) {
+ if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) {
continue
}
v.reset(OpARM64MOVWUreg)
return true
}
// match: (UDIV x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SRLconst [log64(c)] x)
for {
x := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64SRLconst)
return true
}
// match: (UDIVW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c) && is32Bit(c)
+ // cond: isPowerOfTwo(c) && is32Bit(c)
// result: (SRLconst [log64(c)] (MOVWUreg <v.Type> x))
for {
x := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c) && is32Bit(c)) {
+ if !(isPowerOfTwo(c) && is32Bit(c)) {
break
}
v.reset(OpARM64SRLconst)
return true
}
// match: (UMOD x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (ANDconst [c-1] x)
for {
x := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpARM64ANDconst)
return true
}
// match: (UMODW x (MOVDconst [c]))
- // cond: isPowerOfTwo64(c) && is32Bit(c)
+ // cond: isPowerOfTwo(c) && is32Bit(c)
// result: (ANDconst [c-1] x)
for {
x := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c) && is32Bit(c)) {
+ if !(isPowerOfTwo(c) && is32Bit(c)) {
break
}
v.reset(OpARM64ANDconst)
return true
}
// match: (DIVVU x (MOVVconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SRLVconst [log64(c)] x)
for {
x := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpLOONG64SRLVconst)
break
}
// match: (MULV x (MOVVconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SLLVconst [log64(c)] x)
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpLOONG64SLLVconst)
return true
}
// match: (REMVU x (MOVVconst [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (ANDconst [c-1] x)
for {
x := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpLOONG64ANDconst)
break
}
// match: (MUL (MOVWconst [c]) x )
- // cond: isPowerOfTwo64(int64(uint32(c)))
+ // cond: isPowerOfTwo(int64(uint32(c)))
// result: (SLLconst [int32(log2uint32(int64(c)))] x)
for {
for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
}
c := auxIntToInt32(v_0.AuxInt)
x := v_1
- if !(isPowerOfTwo64(int64(uint32(c)))) {
+ if !(isPowerOfTwo(int64(uint32(c)))) {
continue
}
v.reset(OpMIPSSLLconst)
break
}
// match: (Select0 (MULTU (MOVWconst [c]) x ))
- // cond: isPowerOfTwo64(int64(uint32(c)))
+ // cond: isPowerOfTwo(int64(uint32(c)))
// result: (SRLconst [int32(32-log2uint32(int64(c)))] x)
for {
if v_0.Op != OpMIPSMULTU {
}
c := auxIntToInt32(v_0_0.AuxInt)
x := v_0_1
- if !(isPowerOfTwo64(int64(uint32(c)))) {
+ if !(isPowerOfTwo(int64(uint32(c)))) {
continue
}
v.reset(OpMIPSSRLconst)
break
}
// match: (Select1 (MULTU (MOVWconst [c]) x ))
- // cond: isPowerOfTwo64(int64(uint32(c)))
+ // cond: isPowerOfTwo(int64(uint32(c)))
// result: (SLLconst [int32(log2uint32(int64(c)))] x)
for {
if v_0.Op != OpMIPSMULTU {
}
c := auxIntToInt32(v_0_0.AuxInt)
x := v_0_1
- if !(isPowerOfTwo64(int64(uint32(c)))) {
+ if !(isPowerOfTwo(int64(uint32(c)))) {
continue
}
v.reset(OpMIPSSLLconst)
return true
}
// match: (Select0 (DIVVU x (MOVVconst [c])))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (ANDconst [c-1] x)
for {
if v_0.Op != OpMIPS64DIVVU {
break
}
c := auxIntToInt64(v_0_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpMIPS64ANDconst)
break
}
// match: (Select1 (MULVU x (MOVVconst [c])))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SLLVconst [log64(c)] x)
for {
if v_0.Op != OpMIPS64MULVU {
continue
}
c := auxIntToInt64(v_0_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpMIPS64SLLVconst)
return true
}
// match: (Select1 (DIVVU x (MOVVconst [c])))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (SRLVconst [log64(c)] x)
for {
if v_0.Op != OpMIPS64DIVVU {
break
}
c := auxIntToInt64(v_0_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpMIPS64SRLVconst)
v_0 := v.Args[0]
b := v.Block
// match: (MULLDconst <t> x [c])
- // cond: isPowerOfTwo32(c&(c-1))
+ // cond: isPowerOfTwo(c&(c-1))
// result: (ADD (SLDconst <t> x [uint8(log32(c&(c-1)))]) (SLDconst <t> x [uint8(log32(c&^(c-1)))]))
for {
t := v.Type
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c & (c - 1))) {
+ if !(isPowerOfTwo(c & (c - 1))) {
break
}
v.reset(OpS390XADD)
return true
}
// match: (MULLDconst <t> x [c])
- // cond: isPowerOfTwo32(c+(c&^(c-1)))
+ // cond: isPowerOfTwo(c+(c&^(c-1)))
// result: (SUB (SLDconst <t> x [uint8(log32(c+(c&^(c-1))))]) (SLDconst <t> x [uint8(log32(c&^(c-1)))]))
for {
t := v.Type
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c + (c &^ (c - 1)))) {
+ if !(isPowerOfTwo(c + (c &^ (c - 1)))) {
break
}
v.reset(OpS390XSUB)
return true
}
// match: (MULLDconst <t> x [c])
- // cond: isPowerOfTwo32(-c+(-c&^(-c-1)))
+ // cond: isPowerOfTwo(-c+(-c&^(-c-1)))
// result: (SUB (SLDconst <t> x [uint8(log32(-c&^(-c-1)))]) (SLDconst <t> x [uint8(log32(-c+(-c&^(-c-1))))]))
for {
t := v.Type
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(-c + (-c &^ (-c - 1)))) {
+ if !(isPowerOfTwo(-c + (-c &^ (-c - 1)))) {
break
}
v.reset(OpS390XSUB)
v_0 := v.Args[0]
b := v.Block
// match: (MULLWconst <t> x [c])
- // cond: isPowerOfTwo32(c&(c-1))
+ // cond: isPowerOfTwo(c&(c-1))
// result: (ADDW (SLWconst <t> x [uint8(log32(c&(c-1)))]) (SLWconst <t> x [uint8(log32(c&^(c-1)))]))
for {
t := v.Type
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c & (c - 1))) {
+ if !(isPowerOfTwo(c & (c - 1))) {
break
}
v.reset(OpS390XADDW)
return true
}
// match: (MULLWconst <t> x [c])
- // cond: isPowerOfTwo32(c+(c&^(c-1)))
+ // cond: isPowerOfTwo(c+(c&^(c-1)))
// result: (SUBW (SLWconst <t> x [uint8(log32(c+(c&^(c-1))))]) (SLWconst <t> x [uint8(log32(c&^(c-1)))]))
for {
t := v.Type
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(c + (c &^ (c - 1)))) {
+ if !(isPowerOfTwo(c + (c &^ (c - 1)))) {
break
}
v.reset(OpS390XSUBW)
return true
}
// match: (MULLWconst <t> x [c])
- // cond: isPowerOfTwo32(-c+(-c&^(-c-1)))
+ // cond: isPowerOfTwo(-c+(-c&^(-c-1)))
// result: (SUBW (SLWconst <t> x [uint8(log32(-c&^(-c-1)))]) (SLWconst <t> x [uint8(log32(-c+(-c&^(-c-1))))]))
for {
t := v.Type
c := auxIntToInt32(v.AuxInt)
x := v_0
- if !(isPowerOfTwo32(-c + (-c &^ (-c - 1)))) {
+ if !(isPowerOfTwo(-c + (-c &^ (-c - 1)))) {
break
}
v.reset(OpS390XSUBW)
return true
}
// match: (Div16 n (Const16 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo16(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (Rsh16Ux64 n (Const64 <typ.UInt64> [log16(c)]))
for {
n := v_0
break
}
c := auxIntToInt16(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo16(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpRsh16Ux64)
return true
}
// match: (Div16 <t> n (Const16 [c]))
- // cond: isPowerOfTwo16(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh16x64 (Add16 <t> n (Rsh16Ux64 <t> (Rsh16x64 <t> n (Const64 <typ.UInt64> [15])) (Const64 <typ.UInt64> [int64(16-log16(c))]))) (Const64 <typ.UInt64> [int64(log16(c))]))
for {
t := v.Type
break
}
c := auxIntToInt16(v_1.AuxInt)
- if !(isPowerOfTwo16(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh16x64)
return true
}
// match: (Div16u n (Const16 [c]))
- // cond: isPowerOfTwo16(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh16Ux64 n (Const64 <typ.UInt64> [log16(c)]))
for {
n := v_0
break
}
c := auxIntToInt16(v_1.AuxInt)
- if !(isPowerOfTwo16(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh16Ux64)
return true
}
// match: (Div32 n (Const32 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo32(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (Rsh32Ux64 n (Const64 <typ.UInt64> [log32(c)]))
for {
n := v_0
break
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo32(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpRsh32Ux64)
return true
}
// match: (Div32 <t> n (Const32 [c]))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh32x64 (Add32 <t> n (Rsh32Ux64 <t> (Rsh32x64 <t> n (Const64 <typ.UInt64> [31])) (Const64 <typ.UInt64> [int64(32-log32(c))]))) (Const64 <typ.UInt64> [int64(log32(c))]))
for {
t := v.Type
break
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh32x64)
return true
}
// match: (Div32u n (Const32 [c]))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh32Ux64 n (Const64 <typ.UInt64> [log32(c)]))
for {
n := v_0
break
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh32Ux64)
return true
}
// match: (Div64 n (Const64 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo64(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (Rsh64Ux64 n (Const64 <typ.UInt64> [log64(c)]))
for {
n := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo64(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpRsh64Ux64)
return true
}
// match: (Div64 <t> n (Const64 [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh64x64 (Add64 <t> n (Rsh64Ux64 <t> (Rsh64x64 <t> n (Const64 <typ.UInt64> [63])) (Const64 <typ.UInt64> [int64(64-log64(c))]))) (Const64 <typ.UInt64> [int64(log64(c))]))
for {
t := v.Type
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh64x64)
return true
}
// match: (Div64u n (Const64 [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh64Ux64 n (Const64 <typ.UInt64> [log64(c)]))
for {
n := v_0
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh64Ux64)
return true
}
// match: (Div8 n (Const8 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo8(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (Rsh8Ux64 n (Const64 <typ.UInt64> [log8(c)]))
for {
n := v_0
break
}
c := auxIntToInt8(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo8(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpRsh8Ux64)
return true
}
// match: (Div8 <t> n (Const8 [c]))
- // cond: isPowerOfTwo8(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh8x64 (Add8 <t> n (Rsh8Ux64 <t> (Rsh8x64 <t> n (Const64 <typ.UInt64> [ 7])) (Const64 <typ.UInt64> [int64( 8-log8(c))]))) (Const64 <typ.UInt64> [int64(log8(c))]))
for {
t := v.Type
break
}
c := auxIntToInt8(v_1.AuxInt)
- if !(isPowerOfTwo8(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh8x64)
return true
}
// match: (Div8u n (Const8 [c]))
- // cond: isPowerOfTwo8(c)
+ // cond: isPowerOfTwo(c)
// result: (Rsh8Ux64 n (Const64 <typ.UInt64> [log8(c)]))
for {
n := v_0
break
}
c := auxIntToInt8(v_1.AuxInt)
- if !(isPowerOfTwo8(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpRsh8Ux64)
return true
}
// match: (Mod16 <t> n (Const16 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo16(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (And16 n (Const16 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt16(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo16(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpAnd16)
return true
}
// match: (Mod16u <t> n (Const16 [c]))
- // cond: isPowerOfTwo16(c)
+ // cond: isPowerOfTwo(c)
// result: (And16 n (Const16 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt16(v_1.AuxInt)
- if !(isPowerOfTwo16(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpAnd16)
return true
}
// match: (Mod32 <t> n (Const32 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo32(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (And32 n (Const32 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo32(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpAnd32)
return true
}
// match: (Mod32u <t> n (Const32 [c]))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (And32 n (Const32 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpAnd32)
return true
}
// match: (Mod64 <t> n (Const64 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo64(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (And64 n (Const64 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo64(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpAnd64)
return true
}
// match: (Mod64u <t> n (Const64 [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (And64 n (Const64 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpAnd64)
return true
}
// match: (Mod8 <t> n (Const8 [c]))
- // cond: isNonNegative(n) && isPowerOfTwo8(c)
+ // cond: isNonNegative(n) && isPowerOfTwo(c)
// result: (And8 n (Const8 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt8(v_1.AuxInt)
- if !(isNonNegative(n) && isPowerOfTwo8(c)) {
+ if !(isNonNegative(n) && isPowerOfTwo(c)) {
break
}
v.reset(OpAnd8)
return true
}
// match: (Mod8u <t> n (Const8 [c]))
- // cond: isPowerOfTwo8(c)
+ // cond: isPowerOfTwo(c)
// result: (And8 n (Const8 <t> [c-1]))
for {
t := v.Type
break
}
c := auxIntToInt8(v_1.AuxInt)
- if !(isPowerOfTwo8(c)) {
+ if !(isPowerOfTwo(c)) {
break
}
v.reset(OpAnd8)
break
}
// match: (Mul16 <t> n (Const16 [c]))
- // cond: isPowerOfTwo16(c)
+ // cond: isPowerOfTwo(c)
// result: (Lsh16x64 <t> n (Const64 <typ.UInt64> [log16(c)]))
for {
t := v.Type
continue
}
c := auxIntToInt16(v_1.AuxInt)
- if !(isPowerOfTwo16(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpLsh16x64)
break
}
// match: (Mul16 <t> n (Const16 [c]))
- // cond: t.IsSigned() && isPowerOfTwo16(-c)
+ // cond: t.IsSigned() && isPowerOfTwo(-c)
// result: (Neg16 (Lsh16x64 <t> n (Const64 <typ.UInt64> [log16(-c)])))
for {
t := v.Type
continue
}
c := auxIntToInt16(v_1.AuxInt)
- if !(t.IsSigned() && isPowerOfTwo16(-c)) {
+ if !(t.IsSigned() && isPowerOfTwo(-c)) {
continue
}
v.reset(OpNeg16)
break
}
// match: (Mul32 <t> n (Const32 [c]))
- // cond: isPowerOfTwo32(c)
+ // cond: isPowerOfTwo(c)
// result: (Lsh32x64 <t> n (Const64 <typ.UInt64> [log32(c)]))
for {
t := v.Type
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(isPowerOfTwo32(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpLsh32x64)
break
}
// match: (Mul32 <t> n (Const32 [c]))
- // cond: t.IsSigned() && isPowerOfTwo32(-c)
+ // cond: t.IsSigned() && isPowerOfTwo(-c)
// result: (Neg32 (Lsh32x64 <t> n (Const64 <typ.UInt64> [log32(-c)])))
for {
t := v.Type
continue
}
c := auxIntToInt32(v_1.AuxInt)
- if !(t.IsSigned() && isPowerOfTwo32(-c)) {
+ if !(t.IsSigned() && isPowerOfTwo(-c)) {
continue
}
v.reset(OpNeg32)
break
}
// match: (Mul64 <t> n (Const64 [c]))
- // cond: isPowerOfTwo64(c)
+ // cond: isPowerOfTwo(c)
// result: (Lsh64x64 <t> n (Const64 <typ.UInt64> [log64(c)]))
for {
t := v.Type
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(isPowerOfTwo64(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpLsh64x64)
break
}
// match: (Mul64 <t> n (Const64 [c]))
- // cond: t.IsSigned() && isPowerOfTwo64(-c)
+ // cond: t.IsSigned() && isPowerOfTwo(-c)
// result: (Neg64 (Lsh64x64 <t> n (Const64 <typ.UInt64> [log64(-c)])))
for {
t := v.Type
continue
}
c := auxIntToInt64(v_1.AuxInt)
- if !(t.IsSigned() && isPowerOfTwo64(-c)) {
+ if !(t.IsSigned() && isPowerOfTwo(-c)) {
continue
}
v.reset(OpNeg64)
break
}
// match: (Mul8 <t> n (Const8 [c]))
- // cond: isPowerOfTwo8(c)
+ // cond: isPowerOfTwo(c)
// result: (Lsh8x64 <t> n (Const64 <typ.UInt64> [log8(c)]))
for {
t := v.Type
continue
}
c := auxIntToInt8(v_1.AuxInt)
- if !(isPowerOfTwo8(c)) {
+ if !(isPowerOfTwo(c)) {
continue
}
v.reset(OpLsh8x64)
break
}
// match: (Mul8 <t> n (Const8 [c]))
- // cond: t.IsSigned() && isPowerOfTwo8(-c)
+ // cond: t.IsSigned() && isPowerOfTwo(-c)
// result: (Neg8 (Lsh8x64 <t> n (Const64 <typ.UInt64> [log8(-c)])))
for {
t := v.Type
continue
}
c := auxIntToInt8(v_1.AuxInt)
- if !(t.IsSigned() && isPowerOfTwo8(-c)) {
+ if !(t.IsSigned() && isPowerOfTwo(-c)) {
continue
}
v.reset(OpNeg8)