cmd/compile/internal: add ABI register info for riscv64

This CL adds register information for riscv64

Updates #40724

Change-Id: If2275d9135596ff856d096881e4fe8bd1eeaacb2
Reviewed-on: https://go-review.googlesource.com/c/go/+/359337
Trust: mzh <mzh@golangcn.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: mzh <mzh@golangcn.org>
TryBot-Result: Gopher Robot <gobot@golang.org>

diff --git a/src/cmd/compile/internal/riscv64/ssa.go b/src/cmd/compile/internal/riscv64/ssa.go
index fc52e9427d61f31f9f9eb5f4b62930f0b8ea9001..d4faee9ee3424427f8a758f73667349b4956e5be 100644 (file)
--- a/src/cmd/compile/internal/riscv64/ssa.go
+++ b/src/cmd/compile/internal/riscv64/ssa.go
@@ -230,6 +230,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
                p.From.Type = obj.TYPE_REG
                p.From.Reg = v.Args[0].Reg()
                ssagen.AddrAuto(&p.To, v)
+       case ssa.OpArgIntReg, ssa.OpArgFloatReg:
+               ssagen.CheckArgReg(v)
        case ssa.OpSP, ssa.OpSB, ssa.OpGetG:
                // nothing to do
        case ssa.OpRISCV64MOVBreg, ssa.OpRISCV64MOVHreg, ssa.OpRISCV64MOVWreg,

diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go
index 5ab7240acf683da59192ba04fc91c12770bfe664..fa5b02b325fde7ee692ade0b5be20d8d4a98f827 100644 (file)
--- a/src/cmd/compile/internal/ssa/config.go
+++ b/src/cmd/compile/internal/ssa/config.go
@@ -296,6 +296,8 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo
                c.registers = registersRISCV64[:]
                c.gpRegMask = gpRegMaskRISCV64
                c.fpRegMask = fpRegMaskRISCV64
+               // c.intParamRegs = paramIntRegRISCV64
+               // c.floatParamRegs = paramFloatRegRISCV64
                c.FPReg = framepointerRegRISCV64
                c.hasGReg = true
        case "wasm":

diff --git a/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go b/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
index 171fa23c6c3eb5a5fe073466857462aef76cdaaf..0093fa158d2c3ca4cf8dbc78e21fc713cfa1fec4 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
@@ -477,5 +477,9 @@ func init() {
                gpregmask:       gpMask,
                fpregmask:       fpMask,
                framepointerreg: -1, // not used
+               // Integer parameters passed in register X10-X17, X8-X9, X18-X23
+               ParamIntRegNames: "X10 X11 X12 X13 X14 X15 X16 X17 X8 X9 X18 X19 X20 X21 X22 X23",
+               // Float parameters passed in register F10-F17, F8-F9, F18-F23
+               ParamFloatRegNames: "F10 F11 F12 F13 F14 F15 F16 F17 F8 F9 F18 F19 F20 F21 F22 F23",
        })
 }

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 3ea3b7368455e9c59a5df4b9d4c9e46e31b54eca..dfd9bc5f02459d23623b63ae4401647122c1a5f6 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -37356,8 +37356,8 @@ var registersRISCV64 = [...]Register{
        {62, riscv.REG_F31, -1, "F31"},
        {63, 0, -1, "SB"},
 }
-var paramIntRegRISCV64 = []int8(nil)
-var paramFloatRegRISCV64 = []int8(nil)
+var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22}
+var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54}
 var gpRegMaskRISCV64 = regMask(1006632944)
 var fpRegMaskRISCV64 = regMask(9223372034707292160)
 var specialRegMaskRISCV64 = regMask(0)