cmd/compile: don't reserve X15 for float sub/div any more

We used to reserve X15 to implement the 3-operand floating-point
sub/div ops with the 2-operand sub/div that 386/amd64 gives us.

Now that resultInArg0 is implemented, we no longer need to
reserve X15 (X7 on 386).

Fixes #15584

Change-Id: I978e6c0a35236e89641bfc027538cede66004e82
Reviewed-on: https://go-review.googlesource.com/28272
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: David Chase <drchase@google.com>

diff --git a/src/cmd/compile/internal/ssa/gen/386Ops.go b/src/cmd/compile/internal/ssa/gen/386Ops.go
index c0cd7c6b2009876af03979c0e7e420c62bc6ca3c..83dd468c24ec997520fa3f8bff0f41b9609a1d94 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/386Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/386Ops.go
@@ -88,7 +88,6 @@ func init() {
                dx         = buildReg("DX")
                gp         = buildReg("AX CX DX BX BP SI DI")
                fp         = buildReg("X0 X1 X2 X3 X4 X5 X6 X7")
-               x7         = buildReg("X7")
                gpsp       = gp | buildReg("SP")
                gpspsb     = gpsp | buildReg("SB")
                callerSave = gp | fp
@@ -133,10 +132,8 @@ func init() {
                gpstoreidx      = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}}
                gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}}
 
-               fp01   = regInfo{inputs: nil, outputs: fponly}
-               fp21   = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
-               fp21x7 = regInfo{inputs: []regMask{fp &^ x7, fp &^ x7},
-                       clobbers: x7, outputs: []regMask{fp &^ x7}}
+               fp01     = regInfo{inputs: nil, outputs: fponly}
+               fp21     = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
                fpgp     = regInfo{inputs: fponly, outputs: gponly}
                gpfp     = regInfo{inputs: gponly, outputs: fponly}
                fp11     = regInfo{inputs: fponly, outputs: fponly}
@@ -153,12 +150,12 @@ func init() {
                // fp ops
                {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, // fp32 add
                {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, // fp64 add
-               {name: "SUBSS", argLength: 2, reg: fp21x7, asm: "SUBSS", resultInArg0: true},                  // fp32 sub
-               {name: "SUBSD", argLength: 2, reg: fp21x7, asm: "SUBSD", resultInArg0: true},                  // fp64 sub
+               {name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true},                    // fp32 sub
+               {name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true},                    // fp64 sub
                {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul
                {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
-               {name: "DIVSS", argLength: 2, reg: fp21x7, asm: "DIVSS", resultInArg0: true},                  // fp32 div
-               {name: "DIVSD", argLength: 2, reg: fp21x7, asm: "DIVSD", resultInArg0: true},                  // fp64 div
+               {name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},                    // fp32 div
+               {name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true},                    // fp64 div
 
                {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff"},            // fp32 load
                {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff"},            // fp64 load

diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index 235da876932ab5c4a5173943c02c88738430cc7b..d8659a51b03d718d05853b6931b07d506f74d98c 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -92,7 +92,6 @@ func init() {
                ax         = buildReg("AX")
                cx         = buildReg("CX")
                dx         = buildReg("DX")
-               x15        = buildReg("X15")
                gp         = buildReg("AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15")
                fp         = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15")
                gpsp       = gp | buildReg("SP")
@@ -137,10 +136,8 @@ func init() {
                gpstorexchg     = regInfo{inputs: []regMask{gp, gp, 0}, outputs: []regMask{gp}}
                cmpxchg         = regInfo{inputs: []regMask{gp, ax, gp, 0}, outputs: []regMask{gp, 0}, clobbers: ax}
 
-               fp01    = regInfo{inputs: nil, outputs: fponly}
-               fp21    = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
-               fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15},
-                       clobbers: x15, outputs: []regMask{fp &^ x15}}
+               fp01     = regInfo{inputs: nil, outputs: fponly}
+               fp21     = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
                fpgp     = regInfo{inputs: fponly, outputs: gponly}
                gpfp     = regInfo{inputs: gponly, outputs: fponly}
                fp11     = regInfo{inputs: fponly, outputs: fponly}
@@ -157,12 +154,12 @@ func init() {
                // fp ops
                {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, // fp32 add
                {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, // fp64 add
-               {name: "SUBSS", argLength: 2, reg: fp21x15, asm: "SUBSS", resultInArg0: true},                 // fp32 sub
-               {name: "SUBSD", argLength: 2, reg: fp21x15, asm: "SUBSD", resultInArg0: true},                 // fp64 sub
+               {name: "SUBSS", argLength: 2, reg: fp21, asm: "SUBSS", resultInArg0: true},                    // fp32 sub
+               {name: "SUBSD", argLength: 2, reg: fp21, asm: "SUBSD", resultInArg0: true},                    // fp64 sub
                {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul
                {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
-               {name: "DIVSS", argLength: 2, reg: fp21x15, asm: "DIVSS", resultInArg0: true},                 // fp32 div
-               {name: "DIVSD", argLength: 2, reg: fp21x15, asm: "DIVSD", resultInArg0: true},                 // fp64 div
+               {name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},                    // fp32 div
+               {name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true},                    // fp64 div
 
                {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff"},            // fp32 load
                {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff"},            // fp64 load

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 5e62fab2ff62fd5593b22bee5cc9cbe16f6b5747..7e332025b3f63df142dd3198c93d1f3ecd800346 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -1561,12 +1561,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
-                               {1, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
+                               {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
-                       clobbers: 32768, // X7
                        outputs: []outputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
                },
        },
@@ -1577,12 +1576,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
-                               {1, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
+                               {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
-                       clobbers: 32768, // X7
                        outputs: []outputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
                },
        },
@@ -1625,12 +1623,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ADIVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
-                               {1, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
+                               {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
-                       clobbers: 32768, // X7
                        outputs: []outputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
                },
        },
@@ -1641,12 +1638,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ADIVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
-                               {1, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
+                               {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
-                       clobbers: 32768, // X7
                        outputs: []outputInfo{
-                               {0, 32512}, // X0 X1 X2 X3 X4 X5 X6
+                               {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
                        },
                },
        },
@@ -3954,12 +3950,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
-                       clobbers: 2147483648, // X15
                        outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -3970,12 +3965,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ASUBSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
-                       clobbers: 2147483648, // X15
                        outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -4018,12 +4012,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ADIVSS,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
-                       clobbers: 2147483648, // X15
                        outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },
@@ -4034,12 +4027,11 @@ var opcodeTable = [...]opInfo{
                asm:          x86.ADIVSD,
                reg: regInfo{
                        inputs: []inputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
-                               {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
+                               {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
-                       clobbers: 2147483648, // X15
                        outputs: []outputInfo{
-                               {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
+                               {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
                        },
                },
        },