]> Cypherpunks repositories - gostls13.git/commitdiff
cmd/compile: fix ADDSDmem comment and order in list
authorAlberto Donizetti <alb.donizetti@gmail.com>
Mon, 31 Jul 2017 09:38:13 +0000 (11:38 +0200)
committerAlberto Donizetti <alb.donizetti@gmail.com>
Tue, 8 Aug 2017 09:21:25 +0000 (09:21 +0000)
ADDSDmem comment said f32 (likely a copy-paste mistake).

Also swap ADDSSmem and ADDSDmem positions in the list to uniform the
list order.

Fixes #21225

Change-Id: I26bb116900c1cf4c4e6faeef613d7318c9c85b98
Reviewed-on: https://go-review.googlesource.com/52071
Run-TryBot: Alberto Donizetti <alb.donizetti@gmail.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Ilya Tocar <ilya.tocar@intel.com>
Reviewed-by: Keith Randall <khr@golang.org>
src/cmd/compile/internal/ssa/gen/AMD64Ops.go
src/cmd/compile/internal/ssa/opGen.go

index c51cbd2238cb95cc75b7f88ee32da8ae9a0c2356..df0d13c3f727b9ac17db6aeacf9e9be7be6c2c20 100644 (file)
@@ -179,8 +179,8 @@ func init() {
                {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"},                // fp64 indexed by i store
                {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"},                // fp64 indexed by 8i store
 
-               {name: "ADDSDmem", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
                {name: "ADDSSmem", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
+               {name: "ADDSDmem", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
                {name: "SUBSSmem", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
                {name: "SUBSDmem", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
                {name: "MULSSmem", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
index ae2dd5f5500c867731e05d65b61d19f044087956..17a5e7020440cb0369dc1e8fedd5c375fcd018f3 100644 (file)
@@ -427,8 +427,8 @@ const (
        OpAMD64MOVSSstoreidx4
        OpAMD64MOVSDstoreidx1
        OpAMD64MOVSDstoreidx8
-       OpAMD64ADDSDmem
        OpAMD64ADDSSmem
+       OpAMD64ADDSDmem
        OpAMD64SUBSSmem
        OpAMD64SUBSDmem
        OpAMD64MULSSmem
@@ -4683,13 +4683,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "ADDSDmem",
+               name:           "ADDSSmem",
                auxType:        auxSymOff,
                argLen:         3,
                resultInArg0:   true,
                faultOnNilArg1: true,
                symEffect:      SymRead,
-               asm:            x86.AADDSD,
+               asm:            x86.AADDSS,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
@@ -4701,13 +4701,13 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:           "ADDSSmem",
+               name:           "ADDSDmem",
                auxType:        auxSymOff,
                argLen:         3,
                resultInArg0:   true,
                faultOnNilArg1: true,
                symEffect:      SymRead,
-               asm:            x86.AADDSS,
+               asm:            x86.AADDSD,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15