cmd/internal/obj/s390x: add MVCLE instruction

MVCLE (Move Long Extended) instruction is used to move large data storage-to-storage.
This change will add MVCLE into the Go asm for s390x architecture.
Upcoming PR of runtime/memmove_s390x.s will use this instruction for performance improvement.

Change-Id: I3bbb6668c736a36849917887398c74cebb1c3a99
Reviewed-on: https://go-review.googlesource.com/c/go/+/677455
Reviewed-by: Srinivas Pokala <Pokala.Srinivas@ibm.com>
Reviewed-by: Keith Randall <khr@golang.org>
Auto-Submit: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Keith Randall <khr@google.com>
Reviewed-by: Michael Munday <mikemndy@gmail.com>
Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>

diff --git a/src/cmd/asm/internal/asm/testdata/s390x.s b/src/cmd/asm/internal/asm/testdata/s390x.s
index 95a8c50dab0acc7a5e0442c47a653ac8ae2e0522..a19292b263640190ccb7972ddd33dcb249194070 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/s390x.s
+++ b/src/cmd/asm/internal/asm/testdata/s390x.s
@@ -263,10 +263,15 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16-
        NC      $8, (R15), n-8(SP)       // d407f010f000
        OC      $8, (R15), n-8(SP)       // d607f010f000
        MVC     $8, (R15), n-8(SP)       // d207f010f000
+       MVC     $256, 8192(R1), 8192(R2) // b90400a2c2a800002000b90400b1c2b800002000d2ffa000b000
        MVCIN   $8, (R15), n-8(SP)       // e807f010f000
        CLC     $8, (R15), n-8(SP)       // d507f000f010
        XC      $256, -8(R15), -8(R15)   // b90400afc2a8fffffff8d7ffa000a000
-       MVC     $256, 8192(R1), 8192(R2) // b90400a2c2a800002000b90400b1c2b800002000d2ffa000b000
+       MVCLE   0, R4, R6                // a8640000
+       MVCLE   4095, R4, R6             // a8640fff
+       MVCLE   $4095, R4, R6            // a8640fff
+       MVCLE   (R3), R4, R6             // a8643000
+       MVCLE   10(R3), R4, R6           // a864300a
 
        CMP     R1, R2                 // b9200012
        CMP     R3, $32767             // a73f7fff

diff --git a/src/cmd/internal/obj/s390x/a.out.go b/src/cmd/internal/obj/s390x/a.out.go
index 3eed4624b12930e4b9c13b9be862fbed74cf71d2..1a64370efa87673d6d508e4d520d00a89e11e78e 100644 (file)
--- a/src/cmd/internal/obj/s390x/a.out.go
+++ b/src/cmd/internal/obj/s390x/a.out.go
@@ -444,6 +444,7 @@ const (
        // storage-and-storage
        AMVC
        AMVCIN
+       AMVCLE
        ACLC
        AXC
        AOC

diff --git a/src/cmd/internal/obj/s390x/anames.go b/src/cmd/internal/obj/s390x/anames.go
index ae86d2092b0ea28f5b2eee4026231ca9126bf04d..c0a0c401fa09a061008def835f0d848cd14d472d 100644 (file)
--- a/src/cmd/internal/obj/s390x/anames.go
+++ b/src/cmd/internal/obj/s390x/anames.go
@@ -181,6 +181,7 @@ var Anames = []string{
        "CMPUBNE",
        "MVC",
        "MVCIN",
+       "MVCLE",
        "CLC",
        "XC",
        "OC",

diff --git a/src/cmd/internal/obj/s390x/asmz.go b/src/cmd/internal/obj/s390x/asmz.go
index 6511549eeb3e5b31382a120a467314bc2af5922a..72d92abbaf2a26807bfe2e34ce8327014984139a 100644 (file)
--- a/src/cmd/internal/obj/s390x/asmz.go
+++ b/src/cmd/internal/obj/s390x/asmz.go
@@ -449,6 +449,10 @@ var optab = []Optab{
 
        // VRR-f
        {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
+
+       // MVC storage and storage
+       {i: 127, as: AMVCLE, a1: C_LOREG, a2: C_REG, a6: C_REG},
+       {i: 127, as: AMVCLE, a1: C_SCON, a2: C_REG, a6: C_REG},
 }
 
 var oprange [ALAST & obj.AMask][]Optab
@@ -4453,6 +4457,24 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
                        }
                }
                zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
+
+       case 127:
+               // NOTE: Mapping MVCLE operands is as follows:
+               // Instruction Format: MVCLE R1,R3,D2(B2)
+               // R1 - prog.To (for Destination)
+               // R3 - prog.Reg (for Source)
+               // B2 - prog.From (for Padding Byte)
+               d2 := c.regoff(&p.From)
+               if p.To.Reg&1 != 0 {
+                       c.ctxt.Diag("output argument must be even register in %v", p)
+               }
+               if p.Reg&1 != 0 {
+                       c.ctxt.Diag("input argument must be an even register in %v", p)
+               }
+               if (p.From.Reg == p.To.Reg) || (p.From.Reg == p.Reg) {
+                       c.ctxt.Diag("padding byte register cannot be same as input or output register %v", p)
+               }
+               zRS(op_MVCLE, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), uint32(d2), asm)
        }
 }