SB $0, X5, X6 // 23005300
SB $4, X5, X6 // 23025300
+ // 5.2: Integer Computational Instructions (RV64I)
+ ADDIW $1, X5, X6 // 1b831200
+ SLLIW $1, X5, X6 // 1b931200
+ SRLIW $1, X5, X6 // 1bd31200
+ SRAIW $1, X5, X6 // 1bd31240
+ ADDW X5, X6, X7 // bb035300
+ SLLW X5, X6, X7 // bb135300
+ SRLW X5, X6, X7 // bb535300
+ SUBW X5, X6, X7 // bb035340
+ SRAW X5, X6, X7 // bb535340
+
// 5.3: Load and Store Instructions (RV64I)
LD $0, X5, X6 // 03b30200
LD $4, X5, X6 // 03b34200
ASH & obj.AMask: sIEncoding,
ASB & obj.AMask: sIEncoding,
+ // 5.2: Integer Computational Instructions (RV64I)
+ AADDIW & obj.AMask: iIEncoding,
+ ASLLIW & obj.AMask: iIEncoding,
+ ASRLIW & obj.AMask: iIEncoding,
+ ASRAIW & obj.AMask: iIEncoding,
+ AADDW & obj.AMask: rIIIEncoding,
+ ASLLW & obj.AMask: rIIIEncoding,
+ ASRLW & obj.AMask: rIIIEncoding,
+ ASUBW & obj.AMask: rIIIEncoding,
+ ASRAW & obj.AMask: rIIIEncoding,
+
// 5.3: Load and Store Instructions (RV64I)
ALD & obj.AMask: iIEncoding,
ASD & obj.AMask: sIEncoding,