cmd/internal/obj/arm64: fix an encoding error of CMPW instruction

For arm64 CMP, ADD and other similar extended register instructions,
if there is no extension, the default extion is LSL<<0, but the default
encoding value (the value of 'option' field) of 32-bit instruction and
64-bit instruction is different, 32-bit is 2 and 64-bit is 3. But the
current assembler incorrectly encodes the value of 32-bit instruction
to 3. This CL fixes this error.

Change-Id: I0e09af2c9c5047a4ed2db7d1183290283db9c31c
Reviewed-on: https://go-review.googlesource.com/c/go/+/329749
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: eric fang <eric.fang@arm.com>
Run-TryBot: Cherry Mui <cherryyz@google.com>
Trust: Dmitri Shuralyov <dmitshur@golang.org>

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 5f1e68545baa63d85248e0d2d6d20bdcceac0404..d8a20edfc13039d205c10a0579ab9414a54daa54 100644 (file)
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -89,7 +89,7 @@ TEXT  foo(SB), DUPOK|NOSPLIT, $-8
        CMP     R1<<33, R2
        CMP     R22.SXTX, RSP                    // ffe336eb
        CMP     $0x22220000, RSP                 // CMP $572653568, RSP   // 5b44a4d2ff633beb
-       CMPW    $0x22220000, RSP                 // CMPW $572653568, RSP  // 5b44a452ff633b6b
+       CMPW    $0x22220000, RSP                 // CMPW $572653568, RSP  // 5b44a452ff433b6b
        CCMN    MI, ZR, R1, $4                   // e44341ba
        // MADD Rn,Rm,Ra,Rd
        MADD    R1, R2, R3, R4                   // 6408019b
@@ -377,6 +377,7 @@ TEXT        foo(SB), DUPOK|NOSPLIT, $-8
        MOVD    $0x1000100010001000, RSP      // MOVD   $1152939097061330944, RSP   // ff8304b2
        MOVW    $0x10001000, RSP              // MOVW   $268439552, RSP             // ff830432
        ADDW    $0x10001000, R1               // ADDW   $268439552, R1              // fb83043221001b0b
+       ADDW    $0x22220000, RSP, R3          // ADDW   $572653568, RSP, R3         // 5b44a452e3433b0b
 
 // move a large constant to a Vd.
        VMOVS   $0x80402010, V11                                      // VMOVS  $2151686160, V11

diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index b8c3cd97c76aa4f5f0455595cd14a836c4c35873..d99afa3d27606f362798eeeed403e8e1420dc4c2 100644 (file)
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -4333,8 +4333,10 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                if p.To.Reg == REG_RSP && isADDSop(p.As) {
                        c.ctxt.Diag("illegal destination register: %v\n", p)
                }
+               lsl0 := LSL0_64
                if isADDWop(p.As) || isANDWop(p.As) {
                        o1 = c.omovconst(AMOVW, p, &p.From, REGTMP)
+                       lsl0 = LSL0_32
                } else {
                        o1 = c.omovconst(AMOVD, p, &p.From, REGTMP)
                }
@@ -4350,7 +4352,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) {
                if p.To.Reg == REGSP || r == REGSP {
                        o2 = c.opxrrr(p, p.As, false)
                        o2 |= REGTMP & 31 << 16
-                       o2 |= LSL0_64
+                       o2 |= uint32(lsl0)
                } else {
                        o2 = c.oprrr(p, p.As)
                        o2 |= REGTMP & 31 << 16 /* shift is 0 */