"LDP (R0), (F0, F1)" and "STP (F1, F2), (R0)" are
silently accepted by the arm64 assembler without
any error message. And this CL fixes that bug.
fixes #26556.
Change-Id: Ib6fae81956deb39a4ffd95e9409acc8dad3ab2d2
Reviewed-on: https://go-review.googlesource.com/125637
Run-TryBot: Ben Shi <powerman1st@163.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
CSEL LT, R1, R2 // ERROR "illegal combination"
AND $0x22220000, R2, RSP // ERROR "illegal combination"
ANDS $0x22220000, R2, RSP // ERROR "illegal combination"
+ LDP (R0), (F0, F1) // ERROR "invalid register pair"
+ STP (F2, F3), (R0) // ERROR "invalid register pair"
RET
default:
c.ctxt.Diag("invalid instruction %v\n", p)
}
+ switch p.As {
+ case ALDP, ALDPW, ALDPSW:
+ if rl < REG_R0 || REG_R30 < rl || rh < REG_R0 || REG_R30 < rh {
+ c.ctxt.Diag("invalid register pair %v\n", p)
+ }
+ case ASTP, ASTPW:
+ if rl < REG_R0 || REG_R31 < rl || rh < REG_R0 || REG_R31 < rh {
+ c.ctxt.Diag("invalid register pair %v\n", p)
+ }
+ }
switch o.scond {
case C_XPOST:
ret |= 1 << 23