internal/cpu: add MIPS64x feature detection

Change-Id: Iacdad1758aa15e4703fccef38c08ecb338b95fd7
Reviewed-on: https://go-review.googlesource.com/c/go/+/200579
Run-TryBot: Meng Zhuo <mengzhuo1203@gmail.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>

diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go
index f326b063321a745ed06ad6488c763bdf2c498256..84df6472eb62e75d13161d8d6cc1b97b760513d7 100644 (file)
--- a/src/internal/cpu/cpu.go
+++ b/src/internal/cpu/cpu.go
@@ -134,6 +134,14 @@ type s390x struct {
        _         CacheLinePad
 }
 
+var MIPS64X mips64x
+
+type mips64x struct {
+       _      CacheLinePad
+       HasMSA bool // MIPS SIMD architecture
+       _      CacheLinePad
+}
+
 // Initialize examines the processor and sets the relevant variables above.
 // This is called by the runtime package early in program initialization,
 // before normal init functions are run. env is set by runtime if the OS supports

diff --git a/src/internal/cpu/cpu_mips64.go b/src/internal/cpu/cpu_mips64.go
deleted file mode 100644 (file)
index 0f821e4..0000000
--- a/src/internal/cpu/cpu_mips64.go
+++ /dev/null
@@ -1,7 +0,0 @@
-// Copyright 2017 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-package cpu
-
-const CacheLinePadSize = 32

diff --git a/src/internal/cpu/cpu_mips64le.go b/src/internal/cpu/cpu_mips64le.go
deleted file mode 100644 (file)
index 0f821e4..0000000
--- a/src/internal/cpu/cpu_mips64le.go
+++ /dev/null
@@ -1,7 +0,0 @@
-// Copyright 2017 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-package cpu
-
-const CacheLinePadSize = 32

diff --git a/src/internal/cpu/cpu_mips64x.go b/src/internal/cpu/cpu_mips64x.go
new file mode 100644 (file)
index 0000000..9b0a824
--- /dev/null
+++ b/src/internal/cpu/cpu_mips64x.go
@@ -0,0 +1,32 @@
+// Copyright 2019 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build mips64 mips64le
+
+package cpu
+
+const CacheLinePadSize = 32
+
+// These are initialized by archauxv in runtime/os_linux_mips64x.go.
+// These should not be changed after they are initialized.
+var HWCap uint
+
+// HWCAP bits. These are exposed by the Linux kernel 5.4.
+const (
+       // CPU features
+       hwcap_MIPS_MSA = 1 << 1
+)
+
+func doinit() {
+       options = []option{
+               {Name: "msa", Feature: &MIPS64X.HasMSA},
+       }
+
+       // HWCAP feature bits
+       MIPS64X.HasMSA = isSet(HWCap, hwcap_MIPS_MSA)
+}
+
+func isSet(hwc uint, value uint) bool {
+       return hwc&value != 0
+}

diff --git a/src/internal/cpu/cpu_no_init.go b/src/internal/cpu/cpu_no_init.go
index d4b2be8cf4f61fc37e2874bf66b07e29d1ac96d4..fb381e1ce2d61b3080ec58eb54727a509bfd3822 100644 (file)
--- a/src/internal/cpu/cpu_no_init.go
+++ b/src/internal/cpu/cpu_no_init.go
@@ -9,6 +9,8 @@
 // +build !ppc64
 // +build !ppc64le
 // +build !s390x
+// +build !mips64
+// +build !mips64le
 
 package cpu
 

diff --git a/src/runtime/os_linux_mips64x.go b/src/runtime/os_linux_mips64x.go
index 464a26a8a46460e2c679dddb9909ef4b6f1dad7c..4ff66f9538a7e71d77e3edec699e65faa710effd 100644 (file)
--- a/src/runtime/os_linux_mips64x.go
+++ b/src/runtime/os_linux_mips64x.go
@@ -7,7 +7,13 @@
 
 package runtime
 
+import "internal/cpu"
+
 func archauxv(tag, val uintptr) {
+       switch tag {
+       case _AT_HWCAP:
+               cpu.HWCap = uint(val)
+       }
 }
 
 func osArchInit() {}