C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */
C_XOREG /* An reg+reg memory arg */
C_FPSCR /* The fpscr register */
- C_XER /* The xer, holds the carry bit */
C_LR /* The link register */
C_CTR /* The count register */
C_ANY /* Any argument */
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_CR1}, C_CREG},
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_CR1SO}, C_CRBIT},
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0}, C_SPR},
- {obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 1}, C_XER},
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 8}, C_LR},
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 9}, C_CTR},
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_FPSCR}, C_FPSCR},