FLDPD (R1), (F2, F2) // ERROR "constrained unpredictable behavior"
FLDPS (R2), (F3, F3) // ERROR "constrained unpredictable behavior"
FSTPD (R1, R2), (R0) // ERROR "invalid register pair"
+ FMOVS (F2), F0 // ERROR "illegal combination"
+ FMOVD F0, (F1) // ERROR "illegal combination"
RET
return C_LIST
case obj.TYPE_MEM:
+ // The base register should be an integer register.
+ if int16(REG_F0) <= a.Reg && a.Reg <= int16(REG_V31) {
+ break
+ }
switch a.Name {
case obj.NAME_EXTERN, obj.NAME_STATIC:
if a.Sym == nil {
}
case 22: /* movT (R)O!,R; movT O(R)!, R -> ldrT */
- if p.As != AFMOVS && p.As != AFMOVD && p.From.Reg != REGSP && p.From.Reg == p.To.Reg {
+ if p.From.Reg != REGSP && p.From.Reg == p.To.Reg {
c.ctxt.Diag("constrained unpredictable behavior: %v", p)
}
o1 |= ((uint32(v) & 0x1FF) << 12) | (uint32(p.From.Reg&31) << 5) | uint32(p.To.Reg&31)
case 23: /* movT R,(R)O!; movT O(R)!, R -> strT */
- if p.As != AFMOVS && p.As != AFMOVD && p.To.Reg != REGSP && p.From.Reg == p.To.Reg {
+ if p.To.Reg != REGSP && p.From.Reg == p.To.Reg {
c.ctxt.Diag("constrained unpredictable behavior: %v", p)
}