]> Cypherpunks repositories - gostls13.git/commitdiff
cmd/internal/obj/loong64: add support for FSEL instruction
authorXiaolin Zhao <zhaoxiaolin@loongson.cn>
Wed, 6 Aug 2025 03:07:57 +0000 (11:07 +0800)
committerabner chenc <chenguoqi@loongson.cn>
Fri, 8 Aug 2025 02:04:20 +0000 (19:04 -0700)
Go asm syntax:
FSEL FCC, FK, FJ, FD

Equivalent platform assembler syntax:
fsel fd, fj, fk, ca

Change-Id: If75f16fca0adfc03f4952f8a5143d22da33ed425
Reviewed-on: https://go-review.googlesource.com/c/go/+/693457
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Mark Freeman <markfreeman@google.com>
src/cmd/asm/internal/asm/testdata/loong64enc1.s
src/cmd/internal/obj/loong64/a.out.go
src/cmd/internal/obj/loong64/anames.go
src/cmd/internal/obj/loong64/asm.go

index 845c1b16be2f18949b139d13ec660a748d236960..8990a99557d71078730dbe8477925d6a0333d7b0 100644 (file)
@@ -376,6 +376,10 @@ lable2:
        FTINTRNEVF      F0, F2          // 02e41a01
        FTINTRNEVD      F0, F2          // 02e81a01
 
+       // FSEL instruction
+       FSEL    FCC0, F1, F2, F3        // 4304000d
+       FSEL    FCC1, F1, F2            // 4284000d
+
        // LDX.{B,BU,H,HU,W,WU,D} instructions
        MOVB            (R14)(R13), R12 // cc350038
        MOVBU           (R14)(R13), R12 // cc352038
index 46bb0b5b91171a83dc09362b55ece0888766d56c..f5d20cfabe76d5c7f882b2e4b1d9b71f1a84f9a5 100644 (file)
@@ -748,6 +748,9 @@ const (
        AFTINTRNEVF
        AFTINTRNEVD
 
+       // 3.2.4.2
+       AFSEL
+
        // LSX and LASX memory access instructions
        AVMOVQ
        AXVMOVQ
index 02c392be76919025fa34bf55deacff7e3fac081c..67b5f2fc80992747b10da1269dd25aa1e934ca96 100644 (file)
@@ -264,6 +264,7 @@ var Anames = []string{
        "FTINTRNEWD",
        "FTINTRNEVF",
        "FTINTRNEVD",
+       "FSEL",
        "VMOVQ",
        "XVMOVQ",
        "VADDB",
index 4e66ddd6cd9109e19a7bbec2df53d42b1c7fab59..1d10ad67d927aa3f5ed477cb9c6c7fbc77983e8e 100644 (file)
@@ -154,6 +154,9 @@ var optab = []Optab{
        {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
        {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
 
+       {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
+       {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
+
        {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
        {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
        {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
@@ -1517,6 +1520,7 @@ func buildop(ctxt *obj.Link) {
                        AWORD,
                        APRELD,
                        APRELDX,
+                       AFSEL,
                        obj.ANOP,
                        obj.ATEXT,
                        obj.AFUNCDATA,
@@ -2387,6 +2391,16 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
                }
                o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
 
+       case 33: // fsel ca, fk, [fj], fd
+               ca := uint32(p.From.Reg)
+               fk := uint32(p.Reg)
+               fd := uint32(p.To.Reg)
+               fj := fd
+               if len(p.RestArgs) > 0 {
+                       fj = uint32(p.GetFrom3().Reg)
+               }
+               o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
+
        case 34: // mov $con,fr
                v := c.regoff(&p.From)
                a := AADDU