continue
}
+ mustBeFirst := func(v *Value) bool {
+ return v.Op == OpPhi || v.Op.isLoweredGetClosurePtr() ||
+ v.Op == OpArgIntReg || v.Op == OpArgFloatReg
+ }
+
zeroWidthPending := false
- apcChangedSize := 0 // size of changedVars for leading Args, Phi, ClosurePtr
+ blockPrologComplete := false // set to true at first non-zero-width op
+ apcChangedSize := 0 // size of changedVars for leading Args, Phi, ClosurePtr
// expect to see values in pattern (apc)* (zerowidth|real)*
for _, v := range b.Values {
slots := state.valueNames[v.ID]
if opcodeTable[v.Op].zeroWidth {
if changed {
- if hasAnyArgOp(v) || v.Op == OpPhi || v.Op.isLoweredGetClosurePtr() {
+ if mustBeFirst(v) || v.Op == OpArg {
// These ranges begin at true beginning of block, not after first instruction
- if zeroWidthPending {
- panic(fmt.Errorf("Unexpected op '%s' mixed with OpArg/OpPhi/OpLoweredGetClosurePtr at beginning of block %s in %s\n%s", v.LongString(), b, b.Func.Name, b.Func))
+ if blockPrologComplete && mustBeFirst(v) {
+ panic(fmt.Errorf("Unexpected placement of op '%s' appearing after non-pseudo-op at beginning of block %s in %s\n%s", v.LongString(), b, b.Func.Name, b.Func))
}
apcChangedSize = len(state.changedVars.contents())
+ // Other zero-width ops must wait on a "real" op.
+ zeroWidthPending = true
continue
}
- // Other zero-width ops must wait on a "real" op.
- zeroWidthPending = true
}
continue
}
// Not zero-width; i.e., a "real" instruction.
zeroWidthPending = false
+ blockPrologComplete = true
for i, varID := range state.changedVars.contents() {
if i < apcChangedSize { // buffered true start-of-block changes
state.updateVar(VarID(varID), v.Block, BlockStart)