(XOR x (MOVWconst [c])) => (XORconst [c] x)
(BIC x (MOVWconst [c])) => (BICconst [c] x)
-(SLL x (MOVWconst [c])) => (SLLconst x [c&31]) // Note: I don't think we ever generate bad constant shifts (i.e. c>=32)
-(SRL x (MOVWconst [c])) => (SRLconst x [c&31])
-(SRA x (MOVWconst [c])) => (SRAconst x [c&31])
+(SLL x (MOVWconst [c])) && 0 <= c && c < 32 => (SLLconst x [c])
+(SRL x (MOVWconst [c])) && 0 <= c && c < 32 => (SRLconst x [c])
+(SRA x (MOVWconst [c])) && 0 <= c && c < 32 => (SRAconst x [c])
(CMP x (MOVWconst [c])) => (CMPconst [c] x)
(CMP (MOVWconst [c]) x) => (InvertFlags (CMPconst [c] x))
(CMNshiftRL x (MOVWconst [c]) [d]) => (CMNconst x [int32(uint32(c)>>uint64(d))])
(CMNshiftRA x (MOVWconst [c]) [d]) => (CMNconst x [c>>uint64(d)])
-(ADDshiftLLreg x y (MOVWconst [c])) => (ADDshiftLL x y [c])
-(ADDshiftRLreg x y (MOVWconst [c])) => (ADDshiftRL x y [c])
-(ADDshiftRAreg x y (MOVWconst [c])) => (ADDshiftRA x y [c])
-(ADCshiftLLreg x y (MOVWconst [c]) flags) => (ADCshiftLL x y [c] flags)
-(ADCshiftRLreg x y (MOVWconst [c]) flags) => (ADCshiftRL x y [c] flags)
-(ADCshiftRAreg x y (MOVWconst [c]) flags) => (ADCshiftRA x y [c] flags)
-(ADDSshiftLLreg x y (MOVWconst [c])) => (ADDSshiftLL x y [c])
-(ADDSshiftRLreg x y (MOVWconst [c])) => (ADDSshiftRL x y [c])
-(ADDSshiftRAreg x y (MOVWconst [c])) => (ADDSshiftRA x y [c])
-(SUBshiftLLreg x y (MOVWconst [c])) => (SUBshiftLL x y [c])
-(SUBshiftRLreg x y (MOVWconst [c])) => (SUBshiftRL x y [c])
-(SUBshiftRAreg x y (MOVWconst [c])) => (SUBshiftRA x y [c])
-(SBCshiftLLreg x y (MOVWconst [c]) flags) => (SBCshiftLL x y [c] flags)
-(SBCshiftRLreg x y (MOVWconst [c]) flags) => (SBCshiftRL x y [c] flags)
-(SBCshiftRAreg x y (MOVWconst [c]) flags) => (SBCshiftRA x y [c] flags)
-(SUBSshiftLLreg x y (MOVWconst [c])) => (SUBSshiftLL x y [c])
-(SUBSshiftRLreg x y (MOVWconst [c])) => (SUBSshiftRL x y [c])
-(SUBSshiftRAreg x y (MOVWconst [c])) => (SUBSshiftRA x y [c])
-(RSBshiftLLreg x y (MOVWconst [c])) => (RSBshiftLL x y [c])
-(RSBshiftRLreg x y (MOVWconst [c])) => (RSBshiftRL x y [c])
-(RSBshiftRAreg x y (MOVWconst [c])) => (RSBshiftRA x y [c])
-(RSCshiftLLreg x y (MOVWconst [c]) flags) => (RSCshiftLL x y [c] flags)
-(RSCshiftRLreg x y (MOVWconst [c]) flags) => (RSCshiftRL x y [c] flags)
-(RSCshiftRAreg x y (MOVWconst [c]) flags) => (RSCshiftRA x y [c] flags)
-(RSBSshiftLLreg x y (MOVWconst [c])) => (RSBSshiftLL x y [c])
-(RSBSshiftRLreg x y (MOVWconst [c])) => (RSBSshiftRL x y [c])
-(RSBSshiftRAreg x y (MOVWconst [c])) => (RSBSshiftRA x y [c])
-(ANDshiftLLreg x y (MOVWconst [c])) => (ANDshiftLL x y [c])
-(ANDshiftRLreg x y (MOVWconst [c])) => (ANDshiftRL x y [c])
-(ANDshiftRAreg x y (MOVWconst [c])) => (ANDshiftRA x y [c])
-(ORshiftLLreg x y (MOVWconst [c])) => (ORshiftLL x y [c])
-(ORshiftRLreg x y (MOVWconst [c])) => (ORshiftRL x y [c])
-(ORshiftRAreg x y (MOVWconst [c])) => (ORshiftRA x y [c])
-(XORshiftLLreg x y (MOVWconst [c])) => (XORshiftLL x y [c])
-(XORshiftRLreg x y (MOVWconst [c])) => (XORshiftRL x y [c])
-(XORshiftRAreg x y (MOVWconst [c])) => (XORshiftRA x y [c])
-(BICshiftLLreg x y (MOVWconst [c])) => (BICshiftLL x y [c])
-(BICshiftRLreg x y (MOVWconst [c])) => (BICshiftRL x y [c])
-(BICshiftRAreg x y (MOVWconst [c])) => (BICshiftRA x y [c])
-(MVNshiftLLreg x (MOVWconst [c])) => (MVNshiftLL x [c])
-(MVNshiftRLreg x (MOVWconst [c])) => (MVNshiftRL x [c])
-(MVNshiftRAreg x (MOVWconst [c])) => (MVNshiftRA x [c])
-(CMPshiftLLreg x y (MOVWconst [c])) => (CMPshiftLL x y [c])
-(CMPshiftRLreg x y (MOVWconst [c])) => (CMPshiftRL x y [c])
-(CMPshiftRAreg x y (MOVWconst [c])) => (CMPshiftRA x y [c])
-(TSTshiftLLreg x y (MOVWconst [c])) => (TSTshiftLL x y [c])
-(TSTshiftRLreg x y (MOVWconst [c])) => (TSTshiftRL x y [c])
-(TSTshiftRAreg x y (MOVWconst [c])) => (TSTshiftRA x y [c])
-(TEQshiftLLreg x y (MOVWconst [c])) => (TEQshiftLL x y [c])
-(TEQshiftRLreg x y (MOVWconst [c])) => (TEQshiftRL x y [c])
-(TEQshiftRAreg x y (MOVWconst [c])) => (TEQshiftRA x y [c])
-(CMNshiftLLreg x y (MOVWconst [c])) => (CMNshiftLL x y [c])
-(CMNshiftRLreg x y (MOVWconst [c])) => (CMNshiftRL x y [c])
-(CMNshiftRAreg x y (MOVWconst [c])) => (CMNshiftRA x y [c])
+(ADDshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDshiftLL x y [c])
+(ADDshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDshiftRL x y [c])
+(ADDshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDshiftRA x y [c])
+(ADCshiftLLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (ADCshiftLL x y [c] flags)
+(ADCshiftRLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (ADCshiftRL x y [c] flags)
+(ADCshiftRAreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (ADCshiftRA x y [c] flags)
+(ADDSshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDSshiftLL x y [c])
+(ADDSshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDSshiftRL x y [c])
+(ADDSshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ADDSshiftRA x y [c])
+(SUBshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBshiftLL x y [c])
+(SUBshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBshiftRL x y [c])
+(SUBshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBshiftRA x y [c])
+(SBCshiftLLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (SBCshiftLL x y [c] flags)
+(SBCshiftRLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (SBCshiftRL x y [c] flags)
+(SBCshiftRAreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (SBCshiftRA x y [c] flags)
+(SUBSshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBSshiftLL x y [c])
+(SUBSshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBSshiftRL x y [c])
+(SUBSshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (SUBSshiftRA x y [c])
+(RSBshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBshiftLL x y [c])
+(RSBshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBshiftRL x y [c])
+(RSBshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBshiftRA x y [c])
+(RSCshiftLLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (RSCshiftLL x y [c] flags)
+(RSCshiftRLreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (RSCshiftRL x y [c] flags)
+(RSCshiftRAreg x y (MOVWconst [c]) flags) && 0 <= c && c < 32 => (RSCshiftRA x y [c] flags)
+(RSBSshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBSshiftLL x y [c])
+(RSBSshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBSshiftRL x y [c])
+(RSBSshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (RSBSshiftRA x y [c])
+(ANDshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ANDshiftLL x y [c])
+(ANDshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ANDshiftRL x y [c])
+(ANDshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ANDshiftRA x y [c])
+(ORshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ORshiftLL x y [c])
+(ORshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ORshiftRL x y [c])
+(ORshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (ORshiftRA x y [c])
+(XORshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (XORshiftLL x y [c])
+(XORshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (XORshiftRL x y [c])
+(XORshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (XORshiftRA x y [c])
+(BICshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (BICshiftLL x y [c])
+(BICshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (BICshiftRL x y [c])
+(BICshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (BICshiftRA x y [c])
+(MVNshiftLLreg x (MOVWconst [c])) && 0 <= c && c < 32 => (MVNshiftLL x [c])
+(MVNshiftRLreg x (MOVWconst [c])) && 0 <= c && c < 32 => (MVNshiftRL x [c])
+(MVNshiftRAreg x (MOVWconst [c])) && 0 <= c && c < 32 => (MVNshiftRA x [c])
+(CMPshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMPshiftLL x y [c])
+(CMPshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMPshiftRL x y [c])
+(CMPshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMPshiftRA x y [c])
+(TSTshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TSTshiftLL x y [c])
+(TSTshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TSTshiftRL x y [c])
+(TSTshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TSTshiftRA x y [c])
+(TEQshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TEQshiftLL x y [c])
+(TEQshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TEQshiftRL x y [c])
+(TEQshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (TEQshiftRA x y [c])
+(CMNshiftLLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMNshiftLL x y [c])
+(CMNshiftRLreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMNshiftRL x y [c])
+(CMNshiftRAreg x y (MOVWconst [c])) && 0 <= c && c < 32 => (CMNshiftRA x y [c])
// Generate rotates
(ADDshiftLL [c] (SRLconst x [32-c]) x) => (SRRconst [32-c] x)
return true
}
// match: (ADCshiftLLreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (ADCshiftLL x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADCshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (ADCshiftRAreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (ADCshiftRA x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADCshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (ADCshiftRLreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (ADCshiftRL x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADCshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (ADDSshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ADDSshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADDSshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ADDSshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ADDSshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADDSshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ADDSshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ADDSshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADDSshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ADDshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ADDshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADDshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ADDshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ADDshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADDshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ADDshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ADDshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMADDshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ANDshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ANDshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMANDshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ANDshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ANDshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMANDshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ANDshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ANDshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMANDshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (BICshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (BICshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMBICshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (BICshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (BICshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMBICshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (BICshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (BICshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMBICshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (CMNshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (CMNshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMCMNshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (CMNshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (CMNshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMCMNshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (CMNshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (CMNshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMCMNshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (CMPshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (CMPshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMCMPshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (CMPshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (CMPshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMCMPshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (CMPshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (CMPshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMCMPshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (MVNshiftLLreg x (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (MVNshiftLL x [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_1.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMMVNshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg(x)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (MVNshiftRAreg x (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (MVNshiftRA x [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_1.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMMVNshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg(x)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (MVNshiftRLreg x (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (MVNshiftRL x [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_1.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMMVNshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg(x)
return true
}
// match: (ORshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ORshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMORshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ORshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ORshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMORshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (ORshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (ORshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMORshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSBSshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (RSBSshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSBSshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSBSshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (RSBSshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSBSshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSBSshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (RSBSshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSBSshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSBshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (RSBshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSBshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSBshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (RSBshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSBshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSBshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (RSBshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSBshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (RSCshiftLLreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (RSCshiftLL x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSCshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (RSCshiftRAreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (RSCshiftRA x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSCshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (RSCshiftRLreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (RSCshiftRL x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMRSCshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (SBCshiftLLreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (SBCshiftLL x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSBCshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (SBCshiftRAreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (SBCshiftRA x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSBCshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
return true
}
// match: (SBCshiftRLreg x y (MOVWconst [c]) flags)
+ // cond: 0 <= c && c < 32
// result: (SBCshiftRL x y [c] flags)
for {
x := v_0
}
c := auxIntToInt32(v_2.AuxInt)
flags := v_3
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSBCshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg3(x, y, flags)
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (SLL x (MOVWconst [c]))
- // result: (SLLconst x [c&31])
+ // cond: 0 <= c && c < 32
+ // result: (SLLconst x [c])
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := auxIntToInt32(v_1.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSLLconst)
- v.AuxInt = int32ToAuxInt(c & 31)
+ v.AuxInt = int32ToAuxInt(c)
v.AddArg(x)
return true
}
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (SRA x (MOVWconst [c]))
- // result: (SRAconst x [c&31])
+ // cond: 0 <= c && c < 32
+ // result: (SRAconst x [c])
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := auxIntToInt32(v_1.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSRAconst)
- v.AuxInt = int32ToAuxInt(c & 31)
+ v.AuxInt = int32ToAuxInt(c)
v.AddArg(x)
return true
}
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (SRL x (MOVWconst [c]))
- // result: (SRLconst x [c&31])
+ // cond: 0 <= c && c < 32
+ // result: (SRLconst x [c])
for {
x := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := auxIntToInt32(v_1.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSRLconst)
- v.AuxInt = int32ToAuxInt(c & 31)
+ v.AuxInt = int32ToAuxInt(c)
v.AddArg(x)
return true
}
return true
}
// match: (SUBSshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (SUBSshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSUBSshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (SUBSshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (SUBSshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSUBSshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (SUBSshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (SUBSshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSUBSshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (SUBshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (SUBshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSUBshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (SUBshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (SUBshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSUBshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (SUBshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (SUBshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMSUBshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (TEQshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (TEQshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMTEQshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (TEQshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (TEQshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMTEQshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (TEQshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (TEQshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMTEQshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (TSTshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (TSTshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMTSTshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (TSTshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (TSTshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMTSTshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (TSTshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (TSTshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMTSTshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (XORshiftLLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (XORshiftLL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMXORshiftLL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (XORshiftRAreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (XORshiftRA x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMXORshiftRA)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)
return true
}
// match: (XORshiftRLreg x y (MOVWconst [c]))
+ // cond: 0 <= c && c < 32
// result: (XORshiftRL x y [c])
for {
x := v_0
break
}
c := auxIntToInt32(v_2.AuxInt)
+ if !(0 <= c && c < 32) {
+ break
+ }
v.reset(OpARMXORshiftRL)
v.AuxInt = int32ToAuxInt(c)
v.AddArg2(x, y)