obj/riscv: fix link to risc-v dwarf register numbers

The repository name and structure in the RISC-V GitHub org has been
modified, rendering the existing link invalid. This updates to point at
the new location of the RISC-V DWARF specification.

Change occured in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/208

Change-Id: I8ca4c390bee2d7ce20418cdd00e4945a426cf5f7
Reviewed-on: https://go-review.googlesource.com/c/go/+/363355
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
Trust: Brad Fitzpatrick <bradfitz@golang.org>
Trust: Than McIntosh <thanm@google.com>

diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index ed88f621d9b76d632f778ddba3a0ee24f1bd1a51..d9434e74158ba8daeed3768333836ac260ea0296 100644 (file)
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -183,7 +183,7 @@ const (
        REGG  = REG_G
 )
 
-// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers
+// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
 var RISCV64DWARFRegisters = map[int16]int16{
        // Integer Registers.
        REG_X0:  0,