[dev.power64] cmd/9g: do not ignore move instructions even if from and to are samaddr()

Those moves might be significant (e.g. narrowing or widening): on Power64,
we don't distinguish between MOVWD and MOVW.

This fixes divmode.go and bug447.go.

LGTM=rsc
R=rsc, iant
CC=golang-codereviews
https://golang.org/cl/125200043

diff --git a/src/cmd/9g/gg.h b/src/cmd/9g/gg.h
index 319702200c675edd2efa56e0921b7590bfd23a0e..6aa00117f8fdb83065147d12bf05773d97b6fc64 100644 (file)
--- a/src/cmd/9g/gg.h
+++ b/src/cmd/9g/gg.h
@@ -62,7 +62,6 @@ vlong fieldoffset(Type*, Node*);
 void   sgen(Node*, Node*, int64);
 void   gmove(Node*, Node*);
 Prog*  gins(int, Node*, Node*);
-int    samaddr(Node*, Node*);
 void   naddr(Node*, Addr*, int);
 void   cgen_aret(Node*, Node*);
 int    componentgen(Node*, Node*);

diff --git a/src/cmd/9g/gsubr.c b/src/cmd/9g/gsubr.c
index a5ce5f141f67d98427d733a8339b4ad5f78f12cf..d8842796a80056010c779b3a39b874f7f8cc67aa 100644 (file)
--- a/src/cmd/9g/gsubr.c
+++ b/src/cmd/9g/gsubr.c
@@ -1006,21 +1006,6 @@ hard:
        return;
 }
 
-int
-samaddr(Node *f, Node *t)
-{
-       if(f->op != t->op)
-               return 0;
-
-       switch(f->op) {
-       case OREGISTER:
-               if(f->val.u.reg != t->val.u.reg)
-                       break;
-               return 1;
-       }
-       return 0;
-}
-
 /*
  * generate one instruction:
  *     as f, t
@@ -1032,16 +1017,6 @@ gins(int as, Node *f, Node *t)
        Prog *p;
        Addr af, at;
 
-       switch(as) {
-       case AMOVW:
-       case AMOVD:
-       case AFMOVS:
-       case AFMOVD:
-               if(f != N && t != N && samaddr(f, t))
-                       return nil;
-               break;
-       }
-
        memset(&af, 0, sizeof af);
        memset(&at, 0, sizeof at);
        if(f != N)