cmd/compile: enforce strongly typed rules for ARM (mergesym)

Replace mergeSym by mergeSymTyped.
L435-L459

toolstash-check successful.

Change-Id: Icbefe5c3589ed4ecdbca3dff9b3a758bdba3b34b
Reviewed-on: https://go-review.googlesource.com/c/go/+/257642
Reviewed-by: Keith Randall <khr@golang.org>
Trust: Alberto Donizetti <alb.donizetti@gmail.com>

diff --git a/src/cmd/compile/internal/ssa/gen/ARM.rules b/src/cmd/compile/internal/ssa/gen/ARM.rules
index 840b93bb5365f68b97e99e83de531904bb8d2d9e..9490805f46d9f353c6ec838db46c5b85365dac76 100644 (file)
--- a/src/cmd/compile/internal/ssa/gen/ARM.rules
+++ b/src/cmd/compile/internal/ssa/gen/ARM.rules
@@ -432,31 +432,31 @@
 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) => (MOVDstore [off1+off2] {sym} ptr val mem)
 (MOVDstore [off1] {sym} (SUBconst [off2] ptr) val mem) => (MOVDstore [off1-off2] {sym} ptr val mem)
 
-(MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-(MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-(MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-(MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-(MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-(MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-(MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
-       (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
-
-(MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
-       (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
-(MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
-       (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
-(MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
-       (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
-(MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
-       (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
-(MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
-       (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+(MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+(MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+(MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+(MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+(MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+(MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+(MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
+       (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
+
+(MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
+       (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
+(MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
+       (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
+(MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
+       (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
+(MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
+       (MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
+(MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
+       (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 
 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x)

diff --git a/src/cmd/compile/internal/ssa/rewriteARM.go b/src/cmd/compile/internal/ssa/rewriteARM.go
index b790d28cacfbf7c1084c8c2dc78dd1c32c4e7537..4e4416516958b08a0ca95881e1a19fe799ae2ff7 100644 (file)
--- a/src/cmd/compile/internal/ssa/rewriteARM.go
+++ b/src/cmd/compile/internal/ssa/rewriteARM.go
@@ -4563,23 +4563,23 @@ func rewriteValueARM_OpARMMOVBUload(v *Value) bool {
        }
        // match: (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVBUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVBUload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -4781,23 +4781,23 @@ func rewriteValueARM_OpARMMOVBload(v *Value) bool {
        }
        // match: (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVBload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVBload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -4993,15 +4993,15 @@ func rewriteValueARM_OpARMMOVBstore(v *Value) bool {
        }
        // match: (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       // result: (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                val := v_1
                mem := v_2
@@ -5009,8 +5009,8 @@ func rewriteValueARM_OpARMMOVBstore(v *Value) bool {
                        break
                }
                v.reset(OpARMMOVBstore)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg3(ptr, val, mem)
                return true
        }
@@ -5182,23 +5182,23 @@ func rewriteValueARM_OpARMMOVDload(v *Value) bool {
        }
        // match: (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVDload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -5266,15 +5266,15 @@ func rewriteValueARM_OpARMMOVDstore(v *Value) bool {
        }
        // match: (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       // result: (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                val := v_1
                mem := v_2
@@ -5282,8 +5282,8 @@ func rewriteValueARM_OpARMMOVDstore(v *Value) bool {
                        break
                }
                v.reset(OpARMMOVDstore)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg3(ptr, val, mem)
                return true
        }
@@ -5328,23 +5328,23 @@ func rewriteValueARM_OpARMMOVFload(v *Value) bool {
        }
        // match: (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVFload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVFload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -5412,15 +5412,15 @@ func rewriteValueARM_OpARMMOVFstore(v *Value) bool {
        }
        // match: (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       // result: (MOVFstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                val := v_1
                mem := v_2
@@ -5428,8 +5428,8 @@ func rewriteValueARM_OpARMMOVFstore(v *Value) bool {
                        break
                }
                v.reset(OpARMMOVFstore)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg3(ptr, val, mem)
                return true
        }
@@ -5476,23 +5476,23 @@ func rewriteValueARM_OpARMMOVHUload(v *Value) bool {
        }
        // match: (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVHUload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVHUload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -5716,23 +5716,23 @@ func rewriteValueARM_OpARMMOVHload(v *Value) bool {
        }
        // match: (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVHload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -5972,15 +5972,15 @@ func rewriteValueARM_OpARMMOVHstore(v *Value) bool {
        }
        // match: (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       // result: (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                val := v_1
                mem := v_2
@@ -5988,8 +5988,8 @@ func rewriteValueARM_OpARMMOVHstore(v *Value) bool {
                        break
                }
                v.reset(OpARMMOVHstore)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg3(ptr, val, mem)
                return true
        }
@@ -6129,23 +6129,23 @@ func rewriteValueARM_OpARMMOVWload(v *Value) bool {
        }
        // match: (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
+       // result: (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                mem := v_1
                if !(canMergeSym(sym1, sym2)) {
                        break
                }
                v.reset(OpARMMOVWload)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg2(ptr, mem)
                return true
        }
@@ -6604,15 +6604,15 @@ func rewriteValueARM_OpARMMOVWstore(v *Value) bool {
        }
        // match: (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem)
        // cond: canMergeSym(sym1,sym2)
-       // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
+       // result: (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
        for {
-               off1 := v.AuxInt
-               sym1 := v.Aux
+               off1 := auxIntToInt32(v.AuxInt)
+               sym1 := auxToSym(v.Aux)
                if v_0.Op != OpARMMOVWaddr {
                        break
                }
-               off2 := v_0.AuxInt
-               sym2 := v_0.Aux
+               off2 := auxIntToInt32(v_0.AuxInt)
+               sym2 := auxToSym(v_0.Aux)
                ptr := v_0.Args[0]
                val := v_1
                mem := v_2
@@ -6620,8 +6620,8 @@ func rewriteValueARM_OpARMMOVWstore(v *Value) bool {
                        break
                }
                v.reset(OpARMMOVWstore)
-               v.AuxInt = off1 + off2
-               v.Aux = mergeSym(sym1, sym2)
+               v.AuxInt = int32ToAuxInt(off1 + off2)
+               v.Aux = symToAux(mergeSymTyped(sym1, sym2))
                v.AddArg3(ptr, val, mem)
                return true
        }