Add support of more ARM VFP instructions in the assembler.
They were introduced in ARM VFPv4.
"FMULAF/FMULAD Fm, Fn, Fd": Fd = Fd + Fn*Fm
"FNMULAF/FNMULAD Fm, Fn, Fd": Fd = -(Fd + Fn*Fm)
"FMULSF/FMULSD Fm, Fn, Fd": Fd = Fd - Fn*Fm
"FNMULSF/FNMULSD Fm, Fn, Fd": Fd = -(Fd - Fn*Fm)
The multiplication results are not rounded.
Change-Id: Id9cc52fd8e1b9a708103cd1e514c85a9e1cb3f47
Reviewed-on: https://go-review.googlesource.com/62550
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
NMULAF F0, F1 // ERROR "illegal combination"
NMULSD F0, F1 // ERROR "illegal combination"
NMULSF F0, F1 // ERROR "illegal combination"
+ FMULAD F0, F1 // ERROR "illegal combination"
+ FMULAF F0, F1 // ERROR "illegal combination"
+ FMULSD F0, F1 // ERROR "illegal combination"
+ FMULSF F0, F1 // ERROR "illegal combination"
+ FNMULAD F0, F1 // ERROR "illegal combination"
+ FNMULAF F0, F1 // ERROR "illegal combination"
+ FNMULSD F0, F1 // ERROR "illegal combination"
+ FNMULSF F0, F1 // ERROR "illegal combination"
NEGF F0, F1, F2 // ERROR "illegal combination"
NEGD F0, F1, F2 // ERROR "illegal combination"
ABSF F0, F1, F2 // ERROR "illegal combination"
NMULAD F5, F6, F7 // 057b16ee
NMULSF F5, F6, F7 // 457a16ee
NMULSD F5, F6, F7 // 457b16ee
+ FMULAF F5, F6, F7 // 057aa6ee
+ FMULAD F5, F6, F7 // 057ba6ee
+ FMULSF F5, F6, F7 // 457aa6ee
+ FMULSD F5, F6, F7 // 457ba6ee
+ FNMULAF F5, F6, F7 // 457a96ee
+ FNMULAD F5, F6, F7 // 457b96ee
+ FNMULSF F5, F6, F7 // 057a96ee
+ FNMULSD F5, F6, F7 // 057b96ee
DIVF F0, F1, F2 // 002a81ee
DIVD.EQ F3, F4, F5 // 035b840e
DIVF.NE F0, F2 // 002a821e
AMULSD
ANMULSF
ANMULSD
+ AFMULAF
+ AFMULAD
+ AFNMULAF
+ AFNMULAD
+ AFMULSF
+ AFMULSD
+ AFNMULSF
+ AFNMULSD
ADIVF
ADIVD
ASQRTF
"MULSD",
"NMULSF",
"NMULSD",
+ "FMULAF",
+ "FMULAD",
+ "FNMULAF",
+ "FNMULAD",
+ "FMULSF",
+ "FMULSD",
+ "FNMULSF",
+ "FNMULSD",
"DIVF",
"DIVD",
"SQRTF",
opset(ANMULAD, r0)
opset(ANMULSF, r0)
opset(ANMULSD, r0)
+ opset(AFMULAF, r0)
+ opset(AFMULAD, r0)
+ opset(AFMULSF, r0)
+ opset(AFMULSD, r0)
+ opset(AFNMULAF, r0)
+ opset(AFNMULAD, r0)
+ opset(AFNMULSF, r0)
+ opset(AFNMULSD, r0)
opset(ADIVF, r0)
opset(ADIVD, r0)
r := int(p.Reg)
if r == 0 {
switch p.As {
- case AMULAD, AMULAF, AMULSF, AMULSD, ANMULAF, ANMULAD, ANMULSF, ANMULSD:
+ case AMULAD, AMULAF, AMULSF, AMULSD, ANMULAF, ANMULAD, ANMULSF, ANMULSD,
+ AFMULAD, AFMULAF, AFMULSF, AFMULSD, AFNMULAF, AFNMULAD, AFNMULSF, AFNMULSD:
c.ctxt.Diag("illegal combination: %v", p)
default:
r = rt
return o | 0xe<<24 | 0x1<<20 | 0xb<<8 | 0x4<<4
case ANMULSF:
return o | 0xe<<24 | 0x1<<20 | 0xa<<8 | 0x4<<4
+ case AFMULAD:
+ return o | 0xe<<24 | 0xa<<20 | 0xb<<8
+ case AFMULAF:
+ return o | 0xe<<24 | 0xa<<20 | 0xa<<8
+ case AFMULSD:
+ return o | 0xe<<24 | 0xa<<20 | 0xb<<8 | 0x4<<4
+ case AFMULSF:
+ return o | 0xe<<24 | 0xa<<20 | 0xa<<8 | 0x4<<4
+ case AFNMULAD:
+ return o | 0xe<<24 | 0x9<<20 | 0xb<<8 | 0x4<<4
+ case AFNMULAF:
+ return o | 0xe<<24 | 0x9<<20 | 0xa<<8 | 0x4<<4
+ case AFNMULSD:
+ return o | 0xe<<24 | 0x9<<20 | 0xb<<8
+ case AFNMULSF:
+ return o | 0xe<<24 | 0x9<<20 | 0xa<<8
case ADIVD:
return o | 0xe<<24 | 0x8<<20 | 0xb<<8 | 0<<4
case ADIVF: